File List

Here is a list of all files with brief descriptions:

[detail level 123]

► axi
axibram_read.v	Read block RAM memory over AXI PS Master GP0
axibram_write.v	Read block RAM memory (or memories?) over AXI PS Master GP0 Memory is supposed to be fast enough
cmprs_afi_mux.v	Writes comressor data from up to 4 channels to system memory over AXI_HP
cmprs_afi_mux_ptr.v	Maintain 4-channel chunk pointers (before AXI) Advance 32-byte chunk pointers for each AXI burst and each frame (4*2=8 pointers)
cmprs_afi_mux_ptr_wresp.v	Maintain 4-channel chunk pointers for wrirte response Advance 32-byte chunk pointers for each AXI burst and each frame (4*2=8 pointers)
cmprs_afi_mux_status.v	Prepare and send per-channel chunk pointer information as status Using 4 consecutive locations. Each channel can provide one of the 4 pointers: frame pointer in the write channel, current chunk pointer in the write channel and the same for the write response channel (confirmed written to the system memory
histogram_saxi.v	Histograms transfer to the system memory over S_AXI
membridge.v	Bi-directional bridge between system and video memory over axi_hp
mul_saxi_wr_chn.v	One channel of the mult_saxi_wr (read/write common buffer)
mult_saxi_wr.v	Send data from up to 4 sources to the system memory over S_AXI. Each source should have a 32-bit wide buffer running at the same clock (mclk). Buffer should contain at least burst size (4,8,16,32,64 bytes) Burst size parameter-configurable (per-port)
mult_saxi_wr_inbuf.v	Channel buffer with width conversion to 32 to use with mult_saxi_wr
mult_saxi_wr_pointers.v	Process pointers for mult_saxi_wr
► cocotb
socket_command.py
x393_cocotb_server.py
x393_dut.v	Top DUT module for trying cocotb Initially will include other simulation modules, leaving just AXI for communicating with Cocotb
x393interfaces.py
► compressor_jp
bit_stuffer_27_32.v	Aggregate MSB aligned variable-length (1..27) data to 32-bit words
bit_stuffer_escape.v	Escapes each 0xff with 0x00, 32-bit input and output
bit_stuffer_metadata.v	Bit stuffer combines variable length fragments (up to 16 bits long) from the Huffman encoder to a byte stream, escapes every 0xff byte with 0x00 and adds file length and timestamp metadata
cmprs_buf_average.v	Saves Y and C components to buffers, caculates averages during write, then subtracts them during read and provides to the after DCT to restore DC
cmprs_cmd_decode.v	Decode compressor command/modes, reclock some signals
cmprs_frame_sync.v	Synchronizes memory channels (sensor and compressor)
cmprs_macroblock_buf_iface.v	Communicates with compressor memory buffer, generates pixel stream matching selected color mode, accommodates for the buffer latency, acts as a pacemaker for the whole compressor (next stages are able to keep up)
cmprs_out_fifo.v	Compressor output FIFO
cmprs_out_fifo32.v	Compressor output FIFO, modified to use 32-bit input and xclk
cmprs_pixel_buf_iface.v	Communicates with compressor memory buffer, generates pixel stream matching selected color mode, accommodates for the buffer latency, acts as a pacemaker for the whole compressor (next stages are able to keep up)
cmprs_status.v	Generate compressor status word
cmprs_tile_mode2_decode.v	Decode mode parameters, registered at pre-start of the macroblock data to color conversion module
cmprs_tile_mode_decode.v	Decode tile/macroblocks parameters from compressor type
compressor393.v	Top module containg all compressor channels
csconvert.v	Color space convert: combine differnt color modes
csconvert18a.v	Color space converter (bayer-> YCbCr 4:2:1) for JPEG compressor. Uses 18x18 pixel overlapping macroblocks for color conversion
csconvert_jp4.v	Color conversion for JP4 mode
csconvert_jp4diff.v	Color conversion for JP4 differential
csconvert_mono.v	Convert JPEG monochrome
dcc_sync393.v	Synchronises output of DC components Syncronizes dcc data with dma1 output, adds 16..31 16-bit zero words for Axis DMA Was not used in late NC353 camera (DMA channel used fro IMU logger)
encoderDCAC393.v	RLL encoder for JPEG compressor
focus_sharp393.v	Module to determine focus sharpness on by integrating DCT coefficient, multiplied my 8x8 array and squared
huff_fifo393.v	Part of Huffman encoder for JPEG compressor - FIFO for Huffman encoder based on earlier design that used 2x clock. Superseded by huffman_stuffer_meta
huffman393.v	Huffman encoder for JPEG compressor based on previous design that used 2x clock. Superseded by huffman_stuffer_meta module
huffman_merge_code_literal.v	Merge 1-16 bits of Huffman code with 0..11 bits of literal data, align result to MSB : {huffman,literal, {n{1'b0}}
huffman_snglclk.v	Huffman encoder for JPEG compressor, redesigned to use single rate pixel clock
huffman_stuffer_meta.v	Wrapper fior several JPEG/JP4 compression modules. It includes
jp_channel.v	Top module of JPEG/JP4 compressor channel
quantizer393.v	Quantizer module for JPEG/JP4 compressor
stuffer393.v	Bit stuffer for JPEG/JP4 compressor based on earlier design Now used for comparison only, functionality is reimplemented in bit_stuffer_metadata module
varlen_encode393.v	Part of the Huffman encoder for JPEG compressor - variable length encoder. Used double clock rate, superseded by varlen_encode_snglclk, left for comparison.Encoder will work 2 cycles per "normal" word, 1 cycle for codes "00" and "f0", only magnitude output is needed ASAP (2 cycles, the value out should be valid on the 5-th cycle - it will latency 4 cycles run each other cycle. Later implementsed a shortcut - all codes processed in 2 cycles
varlen_encode_snglclk.v	Part of the Huffman encoder for JPEG compressor - variable length encoder. Uses single pixel clock rate
► dsp
dct1d_chen.v	1d 8-point DCT based on Chen algorithm
dct1d_chen_reorder_in.v	Reorder scan-line pixel stream for dct1d_chen module
dct1d_chen_reorder_out.v	Reorder data from dct1d_chen output to natural sequence
dct2d8x8_chen.v	2-d DCT implementation of Chen algorithm
dct_chen_transpose.v	Reorder+transpose data between two 1-d DCT passes
dsp_addsub_simd.v	SIMD adder/subtracter
dsp_ma.v	DSP with multi-input multiplier and accumulator
dsp_ma_preadd.v	DSP with multi-input multiplier and accumulator with pre-adder
► includes
ahci_defaults.vh
ahci_localparams.vh
ahci_types.vh
ahxi_fsm_code.vh
coring.dat.vh
fis_types.vh
focus_filt.dat.vh
huffman.dat.vh
linear1028rgb.dat.vh
quantization_100.dat.vh
ram18_declare_init.vh
ram18_pass_init.vh
ram36_declare_init.vh
ram36_pass_init.vh
tasks_tests_memory.vh
x393_cur_params_target.vh
x393_cur_params_target_simulation.vh
x393_localparams.vh
x393_mcontr_encode_cmd.vh
x393_parameters.vh
x393_simulation_parameters.vh
x393_tasks01.vh
x393_tasks_afi.vh
x393_tasks_mcntrl_buffers.vh
x393_tasks_mcntrl_en_dis_priority.vh
x393_tasks_mcntrl_timing.vh
x393_tasks_pio_sequences.vh
x393_tasks_ps_pio.vh
x393_tasks_status.vh
► logger
buf_xclk_mclk16_393.v	Move data from xclk to mclk domain
event_logger.v	Top module of the event logger (ported from imu_logger)
imu_exttime393.v	Get external timestamp (for image)
imu_message393.v	Logs events from the odometer (can be software triggered), or other external source
imu_spi393.v	SPI interface for the IMU
imu_timestamps393.v	Acquire timestmps for events
logger_arbiter393.v	Arbiter for the event_logger
nmea_decoder393.v	Decode some of the NMEA sentences (to compress them)
rs232_rcv393.v	Rs232 receiver
► memctrl
► phy
byte_lane.v	DDR3 byte lane, including DQS I/O, 8xDQ I/O and DM output
cmd_addr.v	DDR3 command/address signals
cmda_single.v	Single-bit CMD/address output
dm_single.v	Single-bit DDR3 DQ I/O, same used for DM
dq_single.v	Single-bit DDR3 DQ I/O, same used for DM
dqs_single.v	Single-bit DDR3 DQS I/O
dqs_single_nofine.v	Single-bit DDR3 DQS I/O
mcontr_sequencer.v	Ddr3 sequnecer
phy_cmd.v	Executes a stream of commands to DDR3 phy at 1/2 ddr3 clock, global (also proveides r/w interface to the x64 external buffer)
phy_top.v	Top module of the DDR3 phy
cmd_encod_4mux.v	4-to-1 mux to cmbine memory sequences sources
cmd_encod_linear_mux.v	Multiplex parameters from multiple channels sharing the same linear command encoders (cmd_encod_linear_rd and cmd_encod_linear_wr) Latency 1 clcok cycle
cmd_encod_linear_rd.v	Command sequencer generator for reading a sequential up to 1KB page single page access, bank and row will not be changed
cmd_encod_linear_rw.v	Combining 2 modules:cmd_encod_linear_rd and cmd_encod_linear_wr
cmd_encod_linear_wr.v	Command sequencer generator for writing a sequential up to 1KB page single page access, bank and row will not be changed
cmd_encod_tiled_32_rd.v	Command sequencer generator for reading a tiled area up to 1 kB. Memory is mapped so 8 consecuitive rows have same RA, CA and alternating BA (0 to 7). Data will be read in columns 32 bytes wide, then proceding to the next column (if >1). This is a modification of module: cmd_encod_tiled_32_rd, just reading 32 bytes per row instead of the 16 - that eases timing Start burst should be even (LSB is ignored)
cmd_encod_tiled_32_rw.v	Combines cmd_encod_tiled_32_rd and cmd_encod_tiled_32_wr modules
cmd_encod_tiled_32_wr.v	Command sequencer generator for writing a tiled area up to 1 kB. Memory is mapped so 8 consecuitive rows have same RA, CA and alternating BA (0 to 7). Data will be read in columns 16 bytes wide, then proceding to the next column (if >1). This is a modification of module: cmd_encod_tiled_32_wr, just writing 32 bytes per row instead of the 16 - that eases timing Start burst should be even (LSB is ignored)
cmd_encod_tiled_mux.v	Multiplex parameters from multiple channels sharing the same tiled command encoders (cmd_encod_tiled_rd and cmd_encod_tiled_wr) Latency 1 clcok cycle
cmd_encod_tiled_rd.v	Command sequencer generator for reading a tiled area up to 1 kB
cmd_encod_tiled_rw.v	Combines cmd_encod_tiled_rd and cmd_encod_tiled_wr modules
cmd_encod_tiled_wr.v	Command sequencer generator for writing a tiled area up to 1 kB
ddr_refresh.v	DDR3 memory refresh request module
mcntrl393.v	Top level memory controller for 393 camera, includes channel buffers
mcntrl393_test01.v	Temporary module to interface mcntrl393 control signals
mcntrl_1kx32r.v	Paged buffer for ddr3 controller read channel with address autoincrement. 32 bit external data
mcntrl_1kx32w.v	Paged buffer for ddr3 controller write channel with address autoincrement. 32 bit external data. Extends rd to regen
mcntrl_buf_rd.v	Paged buffer for ddr3 controller read channel with address autoincrement. Variable width external data
mcntrl_buf_wr.v	Paged buffer for ddr3 controller write channel with address autoincrement. 32 bit external data. Extends rd to regen
mcntrl_linear_rw.v	Organize paged R/W from DDR3 memory in scan-line order with window support
mcntrl_ps_pio.v	Read/write channels to DDR3 memory with software-programmable command sequence
mcntrl_tiled_rw.v	Organize paged R/W from DDR3 memory in tiled order with window support Tiles spreading over two different frames is not yet supported (needed for line-scan mode in JPEG (JP4 - OK)
memctrl16.v	16-channel memory controller
scheduler16.v	16-channel programmable DDR memory access scheduler
► sensor
lens_flat393.v	Correction of lens+sensor vignetting. Initially it is just a quadratic function that can be improved later by a piece-linear table function T() of the calculated f(x,y)=p*(x-x0)^2 + q(y-yo)^2 + c. T(f(x,y)) can be used to approximate cos^4). or other vignetting functions
pxd_clock.v	Pixel clock line input
pxd_single.v	Pixel data line input
sens_10398.v	Top level module for the 10398 SFE (with MT9F002 sensor)
sens_gamma.v	Table based piecewise-linear conversion of 16 -> 8 bit data
sens_hispi12l4.v	Decode HiSPi 4-lane, 12 bits Packetized-SP data from the sensor
sens_hispi_clock.v	Recover iclk/iclk2x from the HiSPi differntial clock
sens_hispi_din.v	Input differential receivers for HiSPi lanes
sens_hispi_fifo.v	Cross-clock FIFO with special handling of 'run' output
sens_hispi_lane.v	Decode a single lane of the HiSPi data assuming packetized-SP protocol
sens_histogram.v	Calculates per-color histogram over the specified rectangular region
sens_histogram_mux.v	Readout multiplexer for 4 histogram modules
sens_histogram_snglclk.v	Calculates per-color histogram over the specified rectangular region. Modified from the original sens_histogram to avoid using double frequency clock
sens_parallel12.v	Sensor interface with 12-bit for parallel bus
sens_sync.v	Handle linescan mode, sensor trigger and late frame sync
sensor_channel.v	Top module for a sensor channel
sensor_fifo.v	Cross clock boundary for sensor data, synchronize to HACT
sensor_i2c.v	I2c write-only sequencer to control image sensor
sensor_i2c_io.v	Sensor_i2c with I/O pad elements
sensor_i2c_prot.v	Generate i2c R/W sequence from a 32-bit word and LUT
sensor_i2c_scl_sda.v	Generation of i2c signals
sensor_membuf.v	Memory buffer for one sensor channel
sensors393.v	4-channel sensor subsystem Uniform, assuming the same sensors/multiplexers, common pixel clock
► simulation_modules
par12_hispi_psp4l.v	Convertp parallel 12bit to HiSPi packetized-SP 4 lanes
sim_clk_div.v	Divide clock frequency by integer number
sim_frac_clk_delay.v	Delay clock-synchronous signal by fractional number of periods
sim_soc_interrupts.v	SOC interrupts simulation
simul_axi_fifo_out.v
simul_axi_hp_rd.v	Simplified model of AXI_HP read channel (64-bit only)
simul_axi_hp_wr.v	Simplified model of AXI_HP write channel (64-bit only)
simul_axi_master_rdaddr.v	Simulation model for AXI read address channel
simul_axi_master_wdata.v	Simulation model for AXI write data channel
simul_axi_master_wraddr.v	Simulation model for AXI write address channel
simul_axi_read.v	Simulation of read data through maxi channel
simul_axi_slow_ready.v	Simulation model for AXI: slow ready generation
simul_clk.v	Generate clocks for simulation
simul_clk_div_mult.v	Simulation clock rational multiplier
simul_clk_mult.v	Clock multiplier
simul_clk_mult_div.v	Simulation clock rational multiplier
simul_fifo.v	Simple fifo for simulation
simul_saxi_gp_wr.v	Simplified model of AXI_GP write channel
simul_sensor12bits.v	Generate sensor data
► timing
camsync393.v	Synchronization between cameras using GPIO lines:
rtc393.v	Adjustable real time clock, generate 1 microsecond resolution, timestamps. Provides seconds (32 bit) and microseconds (20 bits), allows 24-bit accummulator-based fine adjustment
timestamp_fifo.v	Receives 64-bit timestamp data over 8-bit bus, copies it to the outputr register set at 'advance' leading edge and then reads through the different clock domain 8-bit bus
timestamp_snapshot.v	Take timestamp snapshot and send the ts message over the 8-bit bus
timestamp_to_parallel.v	Convert byte-parallel timestamp message to parallel sec, usec compatible to the x353 code (for NC353 camera)
timestamp_to_serial.v	Convert legacy parallel timestamp data to a byte-parallel message
timing393.v	Timestamp realrted functionality, extrenal synchronization
► unisims_extra
IBUFG.v	Module name "known" to synthesis, but missing in unisims
IBUFGDS.v	Module name "known" to synthesis, but missing in unisims
► util_modules
axi_hp_clk.v	Generate global clock for axi_hp
clk_to_clk2x.v	Move data between clk and clk2x (nominally posedge aligned)
clocks393.v	Generating global clocks for x393 (excluding memcntrl and SATA)
clocks393m.v	Generating global clocks for x393 (excluding memcntrl and SATA)
cmd_deser.v	Expand command address/data from a byte-wide
cmd_frame_sequencer.v	Store/dispatch commands on per-frame basis
cmd_mux.v	Command multiplexer between AXI and frame-based command sequencer
cmd_readback.v	Store control register data and readback
cmd_seq_mux.v	Command multiplexer from 4 channels of frame-based command sequencers
debug_master.v	Debug master module to send/receive serial debug data
debug_slave.v	Send/receive debug data over the serial ring
dly01_16.v	Synchronous delay by 1-16 clock cycles with reset (will map to primitive)
dly_16.v	Synchronous delay by 1-16 clock cycles with reset (will map to primitives)
dual_clock_source.v	Generate clk and clk2x with configurable output buffers
elastic_cross_clock.v	Generate a train of pulses through the clock domains boundary
fifo_1cycle.v	Configurable synchronous FIFO using the same clock for read and write Single clock cycle latency - simple fifo using sync in, async out RAM, no registers on input and output
fifo_2regs.v	Simple two-register FIFO, no over/under check, behaves correctly only for correct inputs
fifo_cross_clocks.v	Configurable FIFO with separate read and write clocks
fifo_same_clock.v	Configurable synchronous FIFO using the same clock for read and write
fifo_same_clock_fill.v	Configurable synchronous FIFO using the same clock for read and write. Provides fill level - number of words currently in FIFO
fifo_sameclock_control.v	BRAM-based fifo control, uses BARM output registers
frame_num_sync.v	Propagating frame number from acquisition to compressor output
gpio393.v	Control of the 10 GPIO signals of the 10393 board Converted from twelve_ios.v of the x353 project (2005)
index_max_16.v	Find index of the maximal of 16 values (masked), 4 cycle latency
level_cross_clocks.v	Re-sample signal to a different clock to reduce metastability
masked_max_reg.v	Finds maximal of two masked values, registers result
mcont_common_chnbuf_reg.v	Registering data from channel buffer to memory controller
mcont_from_chnbuf_reg.v	Registering data from channel buffer to memory controller
mcont_to_chnbuf_reg.v	Registering data from memory controller to channel buffer
multipulse_cross_clock.v	Generate a train of pulses through clock domains boundary
pri1hot16.v	Priority select one of 16 inputs
pulse_cross_clock.v	Propagate a single pulse through clock domain boundary For same frequencies input pulses can have 1:3 duty cycle EXTRA_DLY=0 and 1:5 for EXTRA_DLY=1
resync_data.v	Resynchronize data between clock domains. No over/underruns are checker, start with half FIFO full. Async reset sets specifies output values regardless of the clocks
round_robin.v	Round-robin arbiter
status_generate.v	Generate byte-serial status data
status_read.v	Receives status read data (low bandwidth) from multiple subsystems byte-serial, stores in axi-addressable memory 8-bita ddress is received from the source module, as well as another (optional) byte of sequence number (set in write command) Sequence number (received first afther the address) is stored as a high byte, lower bytes are the actual payload, starting from lower byte (not all 3 are required. Single-bit responsen can be combined in the same byte with the sequence number to use just 2-byte packets? TODO: add interrupt capabilities
status_router16.v	Routes status data from 16 sources
status_router2.v	2:1 status data router/mux
status_router4.v	Routes status data from 4 sources
status_router8.v	Routes status data from 8 sources
sync_resets.v	Generate synchronous resets for several clocks, leaving room for generous register duplication
table_ad_receive.v	Receive tabble address/data sent by table_ad_transmit
table_ad_transmit.v	Transmit byte-wide table address/data from 32-bit cmd_desr In 32-bit mode we duty cycle is >= 6, so there will always be gaps in chn_stb[i] active
► wrap
dci_reset.v	DCIRESET primitivbe wrapper
ddr3_wrap.v	Ddr3 model wrapper to include delays matching hardware
ibuf_ibufg.v	Wrapper for IBUFG primitive
ibufds_ibufgds.v	Wrapper for IBUFDS primitive
ibufg.v	Wrapper for IBUFG primitive
ibufgds.v	Wrapper for IBUFDS primitive
idelay_ctrl.v	IDELAYCTRL wrapper
idelay_fine_pipe.v	IDELAYE2_FINEDELAY wrapper with fine control pipelined
idelay_nofine.v	IDELAYE2 wrapper without fine delay
iobuf.v	Wrapper for IOBUF primitive
iserdes_mem.v	ISERDESE2/ISERDESE1 wrapper to use for DDR3 memory w/o phasers
latch_g_ce.v	Multi-bit wrapper for the transparent latch primitive
mmcm_adv.v	MMCME2_ADV wrapper
mmcm_phase_cntr.v	MMCME2_ADV with phase counter, supporting absolute phase setting
mpullup.v	Wrapper for PULLUP primitive
obuf.v	Wrapper for OBUF primitive
obufds.v	Wrapper for OBUFDS primitive
oddr.v	ODDR wrapper
oddr_ds.v	Wrapper for ODDR+OBUFDS
oddr_ss.v	Wrapper for ODDR+OBUFT
odelay_fine_pipe.v	ODELAYE2_FINEDELAY wrapper with fine control pipelined
odelay_pipe.v	ODELAYE2 wrapper pipelined
oserdes_mem.v	OSERDESE2/OSERDESE1 wrapper to use for DDR3 memory w/o phasers
pll_base.v	PLLE2_ADV wrapper for PLL_BASE functionality
ram18_var_w_var_r.v	Half-BRAM module wrapper to use as a variable width R/W, no parity
ram18p_var_w_var_r.v	Dual port memory wrapper, with variable width write and variable width read using "SDP" or "TDP" mode of RAMB18E1 (half of RAMB18E1) Uses parity bits to extend total data width (minimal width should be >=8)
ram18t_var_w_var_r.v	Dual port memory wrapper, with variable width write and variable width read, using "TDP" mode of RAMB36E1. Same R/W widths in each port. Does not use parity bits to increase total data width, width down to 1 are valid
ram18tp_var_w_var_r.v	Dual port memory wrapper, with variable width write and variable width read, using "TDP" mode of RAMB18E1. Same R/W widths in each port. Uses parity bits to increase total data width. Widths down to 9 are valid
ram_1kx32_1kx32.v	32-bit in/32-bit out memory buffer
ram_1kx32w_512x64r.v	Block RAM wrapper for the external memory write buffer
ram_512x64w_1kx32r.v	Block RAM wrapper for the external memory read buffer
ram_var_w_var_r.v	Dual port memory wrapper, with variable width write and variable width read using "SDP" ot "TDP" modes of RAMB36E1
ramp_var_w_var_r.v	Dual port memory wrapper, with variable width write and variable width read using "SDP" mode of RAMB36E1 Uses parity bits to extend total data width (minimal width should be >=8)
ramt_var_w_var_r.v	Dual port memory wrapper, with variable width write and variable width read, using "TDP" mode of RAMB36E1. Same R/W widths in each port. Does not use parity bits to increase total data width, width down to 1 are valid
ramt_var_wb_var_r.v	Dual port memory wrapper, with variable width write (with mask) and variable width read, using "TDP" mode of RAMB36E1. Same R/W widths in each port. Does not use parity bits to increase total data width, width down to 1 are valid
ramtp_var_w_var_r.v	Dual port memory wrapper, with variable width write and variable width read, using "TDP" mode of RAMB36E1. Same R/W widths in each port. Uses parity bits to increase total data width. Widths down to 9 are valid
select_clk_buf.v	Select one of the clock buffers primitives by parameter
► x393_sata
► ahci
ahci_ctrl_stat.v	Copy of significant register fields, updating them in axi_ahci_regs registers (software accessible)
ahci_dma.v	DMA R/W over 64-AXI channel for AHCI implementation
ahci_dma_rd_fifo.v	Cross clocks, word-realign, 64->32 Convertion from x64 QWORD-aligned AXI data to 32-bit word-aligned data at mclk
ahci_dma_rd_stuff.v	Stuff DWORD data with missing words into continuous 32-bit data
ahci_dma_wr_fifo.v	Cross clocks, word-realign, 32 -> 64 with byte write mask Convertion from x32 DWORD data received from FIS-es @ mclk to QWORD-aligned AXI data
ahci_fis_receive.v	Receives incoming FIS-es, forwards DMA ones to DMA engine Stores received FIS-es if requested
ahci_fis_transmit.v	Fetches commands, command tables, creates/sends FIS
ahci_fsm.v	AHCI host+port0 state machine
ahci_sata_layers.v	Link and PHY SATA layers
ahci_top.v	Top module of the AHCI implementation
axi_ahci_regs.v	Registers for single-port AHCI over AXI implementation Combination of PCI Headers, PCI power management, and HBA memory 128 DWORD registers Registers, with bits being RO, RW, RWC, RW1
axi_hp_abort.v	Trying to gracefully reset AXI HP after aborted transmission For read channel - just keep afi_rready on until RD FIFO is empty (afi_rcount ==0) For write - keep track aof all what was sent so far, assuming aw is always ahead of w Reset only by global reset (system POR) - probably it is not possible to just reset PL or relaod bitfile,
freq_meter.v	Measure device clock frequency to set the local clock
sata_ahci_top.v	Top of the AHCI implementation of the host adapter
► device
oob_dev.v	Sata oob unit implementation
sata_phy_dev.v	Phy-level, including oob, clock generation and GTXE2
► generated
action_decoder.v	Decode sequencer code to 1-hot actions
condition_mux.v	Select condition
► host
crc.v	Crc calculations for the link layer
drp_other_registers.v	Additional registers controlled/read back over DRP
elastic1632.v	Elastic buffer with 16-bit data input and 32-bit output
gtx_10x8dec.v	8x10 encoder implementation
gtx_10x8dec_init.v
gtx_10x8dec_init_stub.v
gtx_8x10enc.v	8x10 encoder implementation
gtx_8x10enc_init.v
gtx_8x10enc_init_stub.v
gtx_comma_align.v	Comma aligner implementation
gtx_elastic.v	Elastic buffer implementation
gtx_wrap.v	Shall replace gtx's PCS part functions, bypassing PCS itself in gtx
link.v	Sata link layer implementation
oob.v	Sata oob unit implementation
oob_ctrl.v	Module to start oob sequences and to handle errors
sata_phy.v	Phy-level, including oob, clock generation and GTXE2
scrambler.v	Scrambler for the link layer
► wrapper
clock_inverter.v	Glitch-free clock controlled inverter
gtxe2_channel_wrapper.v	Wrapper to switch between closed unisims primitive and open-source one
GTXE2_GPL.v	Emulates GTXE2_CHANNEL primitive behaviour. The file is gathered from multiple files
fpga_version.vh
system_defines.vh
x393.v	Elphel NC393 camera FPGA top module
x393_global.tcl
x393_placement.tcl
x393_timing.tcl