x393  1.0
FPGAcodeforElphelNC393camera
x393_tasks01.vh
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1 /*!
2  * @file x393_tasks01.vh
3  * @date 2015-02-07
4  * @author Andrey Filippov
5  *
6  * @brief Simulation tasks for the x393 (low level)
7  *
8  * @copyright Copyright (c) 2015 Elphel, Inc.
9  *
10  * <b>License:</b>
11  *
12  * x393_tasks01.vh is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License as published by
14  * the Free Software Foundation, either version 3 of the License, or
15  * (at your option) any later version.
16  *
17  * x393_tasks01.vh is distributed in the hope that it will be useful,
18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20  * GNU General Public License for more details.
21  *
22  * You should have received a copy of the GNU General Public License
23  * along with this program. If not, see <http://www.gnu.org/licenses/> .
24  *
25  * Additional permission under GNU GPL version 3 section 7:
26  * If you modify this Program, or any covered work, by linking or combining it
27  * with independent modules provided by the FPGA vendor only (this permission
28  * does not extend to any 3-rd party modules, "soft cores" or macros) under
29  * different license terms solely for the purpose of generating binary "bitstream"
30  * files and/or simulating the code, the copyright holders of this Program give
31  * you the right to distribute the covered work without those independent modules
32  * as long as the source code for them is available from the FPGA vendor free of
33  * charge, and there is no dependence on any encrypted modules for simulating of
34  * the combined code. This permission applies to you if the distributed code
35  * contains all the components and scripts required to completely simulate it
36  * with at least one of the Free Software programs.
37  */
38  // Low-level tasks
39 // alternative way to check for empty read queue (without a separate counter)
40 
41  task write_contol_register;
42  input [29:0] reg_addr;
43 // input integer reg_addr;
44  input [31:0] data;
45  begin
46  axi_write_single_w(CONTROL_ADDR+reg_addr, data);
47  end
48  endtask
49 
50  task read_contol_register;
51  input [29:0] reg_addr;
52  begin
53  read_and_wait_w(CONTROL_RBACK_ADDR+reg_addr);
54  end
55  endtask
56 
57  task wait_read_queue_empty;
58  begin
59  wait (~rvalid && rready && (rid==LAST_ARID)); // nothing left in read queue?
60  SIMUL_AXI_FULL<=1'b0;
61  end
62  endtask
63  task axi_set_rd_lag;
64  input [3:0] lag;
65  begin
66  @(posedge CLK);
67  RD_LAG <= lag;
68  end
69  endtask
70 
71  task axi_set_b_lag;
72  input [3:0] lag;
73  begin
74  @(posedge CLK);
75  B_LAG <= lag;
76  end
77  endtask
78 
79  task read_and_wait_w;
80  input [29:0] address;
81  begin
82  read_and_wait ({address,2'b0});
83  end
84  endtask
85 
86 
87  task read_and_wait;
88  input [31:0] address;
89  begin
90  IRQ_EN = 0;
91  wait (CLK);
92  while (!MAIN_GO) begin
93  wait (!CLK);
94  wait (CLK);
95  end
96  axi_read_addr_inner(
97  GLOBAL_READ_ID, // id
98  address & 32'hfffffffc, // addr
99  4'h0, // len - single
100  1 // burst type - increment
101  );
102  GLOBAL_READ_ID <= GLOBAL_READ_ID+1;
103  wait (!CLK && rvalid && rready);
104  wait (CLK);
105  registered_rdata <= rdata;
106  wait (!CLK); // registered_rdata should be valid on exit
107  IRQ_EN = 1;
108  if (IRQS) begin
109  @(posedge CLK);
110  @(negedge CLK);
111  end
112  end
113  endtask
114 
115  task axi_write_single_w; // address in dwords
116  input [29:0] address;
117  input [31:0] data;
118  begin
119 `ifdef DEBUG_WR_SINGLE
120  $display("axi_write_single_w %h:%h @ %t",address,data,$time);
121 `endif
122  axi_write_single ({address,2'b0},data);
123  end
124  endtask
125 
126  task axi_write_single; // address in bytes, not words
127  input [31:0] address;
128  input [31:0] data;
129  begin
130  axi_write_addr_data(
131  GLOBAL_WRITE_ID, // id
132 // address << 2, // addr
133  address & 32'hfffffffc, // addr
134  data,
135  4'h0, // len - single
136  1, // burst type - increment
137  1'b1, // data_en
138  4'hf, // wstrb
139  1'b1 // last
140  );
141  GLOBAL_WRITE_ID <= GLOBAL_WRITE_ID+1;
142  #0.1; // without this delay axi_write_addr_data() used old value of GLOBAL_WRITE_ID
143  end
144  endtask
145 
146  task axi_write_addr_data;
147  input [11:0] id;
148  input [31:0] addr;
149  input [31:0] data;
150  input [ 3:0] len;
151  input [ 1:0] burst;
152  input data_en; // if 0 - do not send data, only address
153  input [ 3:0] wstrb;
154  input last;
155  begin
156  IRQ_EN = 0;
157  wait (CLK);
158  while (!MAIN_GO) begin
159  wait (!CLK);
160  wait (CLK);
161  end
162  axi_write_addr_data_inner (id, addr, data, len, burst, data_en, wstrb, last);
163  IRQ_EN = 1;
164  if (IRQS) begin
165  @(posedge CLK);
166  @(negedge CLK);
167  end
168  end
169  endtask
170 
171  task axi_write_data;
172  input [11:0] id;
173  input [31:0] data;
174  input [ 3:0] wstrb;
175  input last;
176  begin
177  IRQ_EN = 0;
178  wait (CLK);
179  while (!MAIN_GO) begin
180  wait (!CLK);
181  wait (CLK);
182  end
183  axi_write_data_inner (id, data, wstrb, last);
184  IRQ_EN = 1;
185  if (IRQS) begin
186  @(posedge CLK);
187  @(negedge CLK);
188  end
189  end
190  endtask
191 
192 // Tasks called from ISR
193 
194  task read_contol_register_irq;
195  input [29:0] reg_addr;
196  output [31:0] rslt;
197  begin
198  read_and_wait_w_irq(CONTROL_RBACK_ADDR+reg_addr, rslt);
199  end
200  endtask
201 
202  task read_status_irq;
203  input [STATUS_DEPTH-1:0] address;
204  output [31:0] rslt;
205  begin
206  read_and_wait_w_irq(STATUS_ADDR + address , rslt);
207  end
208  endtask
209 
210  task read_and_wait_w_irq;
211  input [29:0] address;
212  output [31:0] rslt;
213  begin
214  read_and_wait_irq ({address,2'b0},rslt);
215  end
216  endtask
217 
218  task read_and_wait_irq;
219  input [31:0] address;
220  output reg [31:0] rslt;
221  begin
222  axi_read_addr_irq(
223  GLOBAL_READ_ID, // id
224  address & 32'hfffffffc, // addr
225  4'h0, // len - single
226  1 // burst type - increment
227  );
228  GLOBAL_READ_ID <= GLOBAL_READ_ID+1;
229  wait (!CLK && rvalid && rready);
230  wait (CLK);
231  rslt <= rdata;
232  wait (!CLK); // registered_rdata should be valid on exit
233  end
234  endtask
235 
236  task axi_read_addr_irq; // called ferom the main loop, not from interrupts
237  input [11:0] id;
238  input [31:0] addr;
239  input [ 3:0] len;
240  input [ 1:0] burst;
241  begin
242 // IRQ_EN = 0;
243 // wait (CLK);
244 // while (!MAIN_GO) begin
245 // wait (!CLK);
246 // wait (CLK);
247 // end
248  axi_read_addr_inner (id, addr, len, burst);
249 // IRQ_EN = 1;
250  end
251  endtask
252 
253  task write_contol_register_irq;
254  input [29:0] reg_addr;
255 // input integer reg_addr;
256  input [31:0] data;
257  begin
258  axi_write_single_w_irq(CONTROL_ADDR+reg_addr, data);
259  end
260  endtask
261 
262  task axi_write_single_w_irq; // address in dwords
263  input [29:0] address;
264  input [31:0] data;
265  begin
266 `ifdef DEBUG_WR_SINGLE
267  $display("axi_write_single_w %h:%h @ %t",address,data,$time);
268 `endif
269  axi_write_single_irq ({address,2'b0},data);
270  end
271  endtask
272 
273  task axi_write_single_irq; // address in bytes, not words
274  input [31:0] address;
275  input [31:0] data;
276  begin
277  axi_write_addr_data_irq(
278  GLOBAL_WRITE_ID, // id
279  address & 32'hfffffffc, // addr
280  data,
281  4'h0, // len - single
282  1, // burst type - increment
283  1'b1, // data_en
284  4'hf, // wstrb
285  1'b1 // last
286  );
287  GLOBAL_WRITE_ID <= GLOBAL_WRITE_ID+1;
288  #0.1; // without this delay axi_write_addr_data() used old value of GLOBAL_WRITE_ID
289  end
290  endtask
291 
292  task axi_write_addr_data_irq;
293  input [11:0] id;
294  input [31:0] addr;
295  input [31:0] data;
296  input [ 3:0] len;
297  input [ 1:0] burst;
298  input data_en; // if 0 - do not send data, only address
299  input [ 3:0] wstrb;
300  input last;
301  begin
302 // IRQ_EN = 0;
303 // wait (CLK);
304 // while (!MAIN_GO) begin
305 // wait (!CLK);
306 // wait (CLK);
307 // end
308  axi_write_addr_data_inner (id, addr, data, len, burst, data_en, wstrb, last);
309 // IRQ_EN = 1;
310  end
311  endtask
312 
313 
314 // Tasks common for main ind ISR
315 
316  task axi_write_addr_data_inner;
317  input [11:0] id;
318  input [31:0] addr;
319  input [31:0] data;
320  input [ 3:0] len;
321  input [ 1:0] burst;
322  input data_en; // if 0 - do not send data, only address
323  input [ 3:0] wstrb;
324  input last;
325  reg data_sent;
326 // wire data_sent_d;
327 // assign #(.1) data_sent_d= data_sent;
328  begin
329  wait (!CLK && AW_READY);
330  AWID_IN_r <= id;
331  AWADDR_IN_r <= addr;
332  AWLEN_IN_r <= len;
333  AWSIZE_IN_r <= 2'b10;
334  AWBURST_IN_r <= burst;
335  AW_SET_CMD_r <= 1'b1;
336  if (data_en && W_READY) begin
337  WID_IN_r <= id;
338  WDATA_IN_r <= data;
339  WSTRB_IN_r <= wstrb;
340  WLAST_IN_r <= last;
341  W_SET_CMD_r <= 1'b1;
342  data_sent <= 1'b1;
343  end else begin
344  data_sent <= 1'b0;
345  end
346  DEBUG1 <=1'b1;
347  wait (CLK);
348  DEBUG1 <=1'b0;
349  AWID_IN_r <= 'hz;
350  AWADDR_IN_r <= 'hz;
351  AWLEN_IN_r <= 'hz;
352  AWSIZE_IN_r <= 'hz;
353  AWBURST_IN_r <= 'hz;
354  AW_SET_CMD_r <= 1'b0;
355  DEBUG2 <=1'b1;
356  if (data_sent) begin
357  WID_IN_r <= 'hz;
358  WDATA_IN_r <= 'hz;
359  WSTRB_IN_r <= 'hz;
360  WLAST_IN_r <= 'hz;
361  W_SET_CMD_r <= 1'b0;
362  end
363 // Now sent data if it was not sent simultaneously with the address
364  if (data_en && !data_sent) begin
365  DEBUG3 <=1'b1;
366  wait (!CLK && W_READY);
367  DEBUG3 <=1'b0;
368  WID_IN_r <= id;
369  WDATA_IN_r <= data;
370  WSTRB_IN_r <= wstrb;
371  WLAST_IN_r <= last;
372  W_SET_CMD_r <= 1'b1;
373  wait (CLK);
374  DEBUG3 <=1'bx;
375  WID_IN_r <= 'hz;
376  WDATA_IN_r <= 'hz;
377  WSTRB_IN_r <= 'hz;
378  WLAST_IN_r <= 'hz;
379  W_SET_CMD_r <= 1'b0;
380  end
381  DEBUG2 <=1'b0;
382  #0.1;
383  data_sent <= 1'b0;
384  #0.1;
385  end
386  endtask
387 
388  task axi_write_data_inner;
389  input [11:0] id;
390  input [31:0] data;
391  input [ 3:0] wstrb;
392  input last;
393  begin
394  wait (!CLK && W_READY);
395  WID_IN_r <= id;
396  WDATA_IN_r <= data;
397  WSTRB_IN_r <= wstrb;
398  WLAST_IN_r <= last;
399  W_SET_CMD_r <= 1'b1;
400  wait (CLK);
401  WID_IN_r <= 12'hz;
402  WDATA_IN_r <= 'hz;
403  WSTRB_IN_r <= 4'hz;
404  WLAST_IN_r <= 1'bz;
405  W_SET_CMD_r <= 1'b0;
406  #0.1;
407  end
408  endtask
409 
410 
411  task axi_read_addr_inner; // regardless of main loop/interrupts
412  input [11:0] id;
413  input [31:0] addr;
414  input [ 3:0] len;
415  input [ 1:0] burst;
416  begin
417  wait (!CLK && AR_READY);
418  ARID_IN_r <= id;
419  ARADDR_IN_r <= addr;
420  ARLEN_IN_r <= len;
421  ARSIZE_IN_r <= 2'b10;
422  ARBURST_IN_r <= burst;
423  AR_SET_CMD_r <= 1'b1;
424  wait (CLK);
425  ARID_IN_r <= 12'hz;
426  ARADDR_IN_r <= 'hz;
427  ARLEN_IN_r <= 4'hz;
428  ARSIZE_IN_r <= 2'hz;
429  ARBURST_IN_r <= 2'hz;
430  AR_SET_CMD_r <= 1'b0;
431  LAST_ARID <= id;
432  NUM_WORDS_EXPECTED <= NUM_WORDS_EXPECTED+len+1;
433  end
434  endtask
435