simul_clk_div_mult.v

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`timescale 1ns/1ps

module  simul_clk_div_mult#(
        parameter MULTIPLIER = 3,
        parameter DIVISOR =    5,
        parameter SKIP_FIRST = 5
    ) (
        input      clk_in,
        input      en,
        output     clk_out
);
    wire clk_int;
    generate
        if (DIVISOR > 1) 
            sim_clk_div #(
                .DIVISOR   (DIVISOR)
            ) sim_clk_div_i (
                .clk_in   (clk_in), // input
                .en       (en), // input
                .clk_out  (clk_int) // output
            );
        else
            assign clk_int = clk_in;
    endgenerate
    generate
        if (MULTIPLIER > 1) 
            simul_clk_mult #(
                .MULTIPLIER (MULTIPLIER),
                .SKIP_FIRST (SKIP_FIRST)
            ) simul_clk_mult_i (
                .clk_in  (clk_int), // input
                .en      (en), // input
                .clk_out (clk_out) // output
            );
        else
            assign clk_out = clk_int;
    endgenerate
endmodule