2 localparam PCI_Header__ID__DID__ADDR = 'h60;
3 localparam PCI_Header__ID__DID__MASK = 'hffff0000;
4 localparam PCI_Header__ID__DID__DFLT = 'h10000;
6 localparam PCI_Header__ID__VID__ADDR = 'h60;
7 localparam PCI_Header__ID__VID__MASK = 'hffff;
8 localparam PCI_Header__ID__VID__DFLT = 'hfffe;
9 // RW: HBA Interrupt Disable
10 localparam PCI_Header__CMD__ID__ADDR = 'h61;
11 localparam PCI_Header__CMD__ID__MASK = 'h400;
12 localparam PCI_Header__CMD__ID__DFLT = 'h0;
13 // RO: Fast Back-to-Back Enable
14 localparam PCI_Header__CMD__FBE__ADDR = 'h61;
15 localparam PCI_Header__CMD__FBE__MASK = 'h200;
16 localparam PCI_Header__CMD__FBE__DFLT = 'h0;
18 localparam PCI_Header__CMD__SEE__ADDR = 'h61;
19 localparam PCI_Header__CMD__SEE__MASK = 'h100;
20 localparam PCI_Header__CMD__SEE__DFLT = 'h0;
22 localparam PCI_Header__CMD__WCC__ADDR = 'h61;
23 localparam PCI_Header__CMD__WCC__MASK = 'h80;
24 localparam PCI_Header__CMD__WCC__DFLT = 'h0;
25 // RO: Parity Error Response Enable
26 localparam PCI_Header__CMD__PEE__ADDR = 'h61;
27 localparam PCI_Header__CMD__PEE__MASK = 'h40;
28 localparam PCI_Header__CMD__PEE__DFLT = 'h0;
30 localparam PCI_Header__CMD__VGA__ADDR = 'h61;
31 localparam PCI_Header__CMD__VGA__MASK = 'h20;
32 localparam PCI_Header__CMD__VGA__DFLT = 'h0;
34 localparam PCI_Header__CMD__MWIE__ADDR = 'h61;
35 localparam PCI_Header__CMD__MWIE__MASK = 'h10;
36 localparam PCI_Header__CMD__MWIE__DFLT = 'h0;
38 localparam PCI_Header__CMD__SCE__ADDR = 'h61;
39 localparam PCI_Header__CMD__SCE__MASK = 'h8;
40 localparam PCI_Header__CMD__SCE__DFLT = 'h0;
41 // RW: Bus Master Enable (0 - stops any DMA)
42 localparam PCI_Header__CMD__BME__ADDR = 'h61;
43 localparam PCI_Header__CMD__BME__MASK = 'h4;
44 localparam PCI_Header__CMD__BME__DFLT = 'h0;
45 // RW: Memory Space enable (here - always?)
46 localparam PCI_Header__CMD__MSE__ADDR = 'h61;
47 localparam PCI_Header__CMD__MSE__MASK = 'h2;
48 localparam PCI_Header__CMD__MSE__DFLT = 'h0;
49 // RO: Enable IO space access (only for legacy IDE)
50 localparam PCI_Header__CMD__IOSE__ADDR = 'h61;
51 localparam PCI_Header__CMD__IOSE__MASK = 'h1;
52 localparam PCI_Header__CMD__IOSE__DFLT = 'h0;
53 // RWC: Detected Parity Error
54 localparam PCI_Header__STS__DPE__ADDR = 'h61;
55 localparam PCI_Header__STS__DPE__MASK = 'h80000000;
56 localparam PCI_Header__STS__DPE__DFLT = 'h0;
57 // RWC: Signaled System Error (HBA SERR)
58 localparam PCI_Header__STS__SSE__ADDR = 'h61;
59 localparam PCI_Header__STS__SSE__MASK = 'h40000000;
60 localparam PCI_Header__STS__SSE__DFLT = 'h0;
61 // RWC: Received Master Abort
62 localparam PCI_Header__STS__RMA__ADDR = 'h61;
63 localparam PCI_Header__STS__RMA__MASK = 'h20000000;
64 localparam PCI_Header__STS__RMA__DFLT = 'h0;
65 // RWC: Received Target Abort
66 localparam PCI_Header__STS__RTA__ADDR = 'h61;
67 localparam PCI_Header__STS__RTA__MASK = 'h10000000;
68 localparam PCI_Header__STS__RTA__DFLT = 'h0;
69 // RWC: Signaled Target Abort
70 localparam PCI_Header__STS__STA__ADDR = 'h61;
71 localparam PCI_Header__STS__STA__MASK = 'h8000000;
72 localparam PCI_Header__STS__STA__DFLT = 'h0;
73 // RO: PCI DEVSEL Timing
74 localparam PCI_Header__STS__DEVT__ADDR = 'h61;
75 localparam PCI_Header__STS__DEVT__MASK = 'h6000000;
76 localparam PCI_Header__STS__DEVT__DFLT = 'h0;
77 // RWC: Master Data Parity Error Detected
78 localparam PCI_Header__STS__DPD__ADDR = 'h61;
79 localparam PCI_Header__STS__DPD__MASK = 'h1000000;
80 localparam PCI_Header__STS__DPD__DFLT = 'h0;
81 // RO: Fast Back-To-Back Capable
82 localparam PCI_Header__STS__FBC__ADDR = 'h61;
83 localparam PCI_Header__STS__FBC__MASK = 'h800000;
84 localparam PCI_Header__STS__FBC__DFLT = 'h0;
86 localparam PCI_Header__STS__C66__ADDR = 'h61;
87 localparam PCI_Header__STS__C66__MASK = 'h200000;
88 localparam PCI_Header__STS__C66__DFLT = 'h0;
89 // RO: Capabilities List (PCI power management mandatory)
90 localparam PCI_Header__STS__CL__ADDR = 'h61;
91 localparam PCI_Header__STS__CL__MASK = 'h100000;
92 localparam PCI_Header__STS__CL__DFLT = 'h100000;
93 // RO: Interrupt Status (1 - asserted)
94 localparam PCI_Header__STS__IS__ADDR = 'h61;
95 localparam PCI_Header__STS__IS__MASK = 'h80000;
96 localparam PCI_Header__STS__IS__DFLT = 'h0;
97 // RO: HBA Revision ID
98 localparam PCI_Header__RID__RID__ADDR = 'h62;
99 localparam PCI_Header__RID__RID__MASK = 'hff;
100 localparam PCI_Header__RID__RID__DFLT = 'h2;
101 // RO: Base Class Code: 1 - Mass Storage Device
102 localparam PCI_Header__CC__BCC__ADDR = 'h62;
103 localparam PCI_Header__CC__BCC__MASK = 'hff000000;
104 localparam PCI_Header__CC__BCC__DFLT = 'h1000000;
105 // RO: Sub Class Code: 0x06 - SATA Device
106 localparam PCI_Header__CC__SCC__ADDR = 'h62;
107 localparam PCI_Header__CC__SCC__MASK = 'hff0000;
108 localparam PCI_Header__CC__SCC__DFLT = 'h60000;
109 // RO: Programming Interface: 1 - AHCI HBA major rev 1
110 localparam PCI_Header__CC__PI__ADDR = 'h62;
111 localparam PCI_Header__CC__PI__MASK = 'hff0000;
112 localparam PCI_Header__CC__PI__DFLT = 'h10000;
113 // RW: Cache Line Size
114 localparam PCI_Header__CLS__CLS__ADDR = 'h63;
115 localparam PCI_Header__CLS__CLS__MASK = 'hff;
116 localparam PCI_Header__CLS__CLS__DFLT = 'h0;
117 // RW: Master Latency Timer
118 localparam PCI_Header__MLT__MLT__ADDR = 'h63;
119 localparam PCI_Header__MLT__MLT__MASK = 'hff00;
120 localparam PCI_Header__MLT__MLT__DFLT = 'h0;
121 // RO: Multi-Function Device
122 localparam PCI_Header__HTYPE__MFDT__ADDR = 'h63;
123 localparam PCI_Header__HTYPE__MFDT__MASK = 'h8000;
124 localparam PCI_Header__HTYPE__MFDT__DFLT = 'h0;
125 // RO: Header Layout 0 - HBA uses a target device layout
126 localparam PCI_Header__HTYPE__HL__ADDR = 'h63;
127 localparam PCI_Header__HTYPE__HL__MASK = 'h7f00;
128 localparam PCI_Header__HTYPE__HL__DFLT = 'h0;
129 // RO: AHCI Base Address high bits, normally RW, but here RO to get to MAXIGP1 space
130 localparam PCI_Header__ABAR__BA__ADDR = 'h69;
131 localparam PCI_Header__ABAR__BA__MASK = 'hfffffff0;
132 localparam PCI_Header__ABAR__BA__DFLT = 'h80000000;
133 // RO: Prefetchable (this is not)
134 localparam PCI_Header__ABAR__PF__ADDR = 'h69;
135 localparam PCI_Header__ABAR__PF__MASK = 'h8;
136 localparam PCI_Header__ABAR__PF__DFLT = 'h0;
137 // RO: Type (0 - any 32-bit address, here it is hard-mapped
138 localparam PCI_Header__ABAR__TP__ADDR = 'h69;
139 localparam PCI_Header__ABAR__TP__MASK = 'h6;
140 localparam PCI_Header__ABAR__TP__DFLT = 'h0;
141 // RO: Resource Type Indicator: 0 - memory address
142 localparam PCI_Header__ABAR__RTE__ADDR = 'h69;
143 localparam PCI_Header__ABAR__RTE__MASK = 'h1;
144 localparam PCI_Header__ABAR__RTE__DFLT = 'h0;
146 localparam PCI_Header__SS__SSID__ADDR = 'h6b;
147 localparam PCI_Header__SS__SSID__MASK = 'hffff0000;
148 localparam PCI_Header__SS__SSID__DFLT = 'h10000;
149 // RO: SubSystem Vendor ID
150 localparam PCI_Header__SS__SSVID__ADDR = 'h6b;
151 localparam PCI_Header__SS__SSVID__MASK = 'hffff;
152 localparam PCI_Header__SS__SSVID__DFLT = 'hfffe;
153 // RO: ROM Base Address
154 localparam PCI_Header__EROM__RBA__ADDR = 'h6c;
155 localparam PCI_Header__EROM__RBA__MASK = 'hffffffff;
156 localparam PCI_Header__EROM__RBA__DFLT = 'h0;
157 // RO: Capabilities pointer
158 localparam PCI_Header__CAP__CAP__ADDR = 'h6d;
159 localparam PCI_Header__CAP__CAP__MASK = 'hff;
160 localparam PCI_Header__CAP__CAP__DFLT = 'h40;
162 localparam PCI_Header__INTR__IPIN__ADDR = 'h6f;
163 localparam PCI_Header__INTR__IPIN__MASK = 'hff00;
164 localparam PCI_Header__INTR__IPIN__DFLT = 'h100;
165 // RW: Interrupt Line
166 localparam PCI_Header__INTR__ILINE__ADDR = 'h6f;
167 localparam PCI_Header__INTR__ILINE__MASK = 'hff;
168 localparam PCI_Header__INTR__ILINE__DFLT = 'h0;
170 localparam PCI_Header__MGNT__MGNT__ADDR = 'h6f;
171 localparam PCI_Header__MGNT__MGNT__MASK = 'hff0000;
172 localparam PCI_Header__MGNT__MGNT__DFLT = 'h0;
173 // RO: Maximal Latency
174 localparam PCI_Header__MLAT__MLAT__ADDR = 'h6f;
175 localparam PCI_Header__MLAT__MLAT__MASK = 'hff000000;
176 localparam PCI_Header__MLAT__MLAT__DFLT = 'h0;
177 // RO: Next Capability pointer
178 localparam PMCAP__PID__NEXT__ADDR = 'h70;
179 localparam PMCAP__PID__NEXT__MASK = 'hff00;
180 localparam PMCAP__PID__NEXT__DFLT = 'h0;
181 // RO: This is PCI Power Management Capability
182 localparam PMCAP__PID__CID__ADDR = 'h70;
183 localparam PMCAP__PID__CID__MASK = 'hff;
184 localparam PMCAP__PID__CID__DFLT = 'h1;
185 // RO: PME_SUPPORT bits:'b01000
186 localparam PMCAP__PC__PSUP__ADDR = 'h70;
187 localparam PMCAP__PC__PSUP__MASK = 'hf8000000;
188 localparam PMCAP__PC__PSUP__DFLT = 'h40000000;
189 // RO: D2 Support - no
190 localparam PMCAP__PC__D2S__ADDR = 'h70;
191 localparam PMCAP__PC__D2S__MASK = 'h4000000;
192 localparam PMCAP__PC__D2S__DFLT = 'h0;
193 // RO: D1 Support - no
194 localparam PMCAP__PC__D1S__ADDR = 'h70;
195 localparam PMCAP__PC__D1S__MASK = 'h2000000;
196 localparam PMCAP__PC__D1S__DFLT = 'h0;
197 // RO: Maximal D3cold current
198 localparam PMCAP__PC__AUXC__ADDR = 'h70;
199 localparam PMCAP__PC__AUXC__MASK = 'h1c00000;
200 localparam PMCAP__PC__AUXC__DFLT = 'h0;
201 // RO: Device-specific initialization required
202 localparam PMCAP__PC__DSI__ADDR = 'h70;
203 localparam PMCAP__PC__DSI__MASK = 'h200000;
204 localparam PMCAP__PC__DSI__DFLT = 'h0;
205 // RO: PCI clock required to generate PME
206 localparam PMCAP__PC__PMEC__ADDR = 'h70;
207 localparam PMCAP__PC__PMEC__MASK = 'h80000;
208 localparam PMCAP__PC__PMEC__DFLT = 'h0;
209 // RO: Revision of Power Management Specification support version
210 localparam PMCAP__PC__VS__ADDR = 'h70;
211 localparam PMCAP__PC__VS__MASK = 'h70000;
212 localparam PMCAP__PC__VS__DFLT = 'h0;
213 // RWC: PME Status, set by hardware when HBA generates PME
214 localparam PMCAP__PMCS__PMES__ADDR = 'h71;
215 localparam PMCAP__PMCS__PMES__MASK = 'h8000;
216 localparam PMCAP__PMCS__PMES__DFLT = 'h0;
218 localparam PMCAP__PMCS__PMEE__ADDR = 'h71;
219 localparam PMCAP__PMCS__PMEE__MASK = 'h100;
220 localparam PMCAP__PMCS__PMEE__DFLT = 'h0;
222 localparam PMCAP__PMCS__PS__ADDR = 'h71;
223 localparam PMCAP__PMCS__PS__MASK = 'h3;
224 localparam PMCAP__PMCS__PS__DFLT = 'h0;
225 // RO: Supports 64-bit Addressing - no
226 localparam GHC__CAP__S64A__ADDR = 'h0;
227 localparam GHC__CAP__S64A__MASK = 'h80000000;
228 localparam GHC__CAP__S64A__DFLT = 'h0;
229 // RO: Supports Native Command Queuing - no
230 localparam GHC__CAP__SNCQ__ADDR = 'h0;
231 localparam GHC__CAP__SNCQ__MASK = 'h40000000;
232 localparam GHC__CAP__SNCQ__DFLT = 'h0;
233 // RO: Supports SNotification Register - no
234 localparam GHC__CAP__SSNTF__ADDR = 'h0;
235 localparam GHC__CAP__SSNTF__MASK = 'h20000000;
236 localparam GHC__CAP__SSNTF__DFLT = 'h0;
237 // RO: Supports Mechanical Presence Switch - no
238 localparam GHC__CAP__SMPS__ADDR = 'h0;
239 localparam GHC__CAP__SMPS__MASK = 'h10000000;
240 localparam GHC__CAP__SMPS__DFLT = 'h0;
241 // RO: Supports Staggered Spin-up - no
242 localparam GHC__CAP__SSS__ADDR = 'h0;
243 localparam GHC__CAP__SSS__MASK = 'h8000000;
244 localparam GHC__CAP__SSS__DFLT = 'h0;
245 // RO: Supports Aggressive Link Power Management - no
246 localparam GHC__CAP__SALP__ADDR = 'h0;
247 localparam GHC__CAP__SALP__MASK = 'h4000000;
248 localparam GHC__CAP__SALP__DFLT = 'h0;
249 // RO: Supports Activity LED - no
250 localparam GHC__CAP__SAL__ADDR = 'h0;
251 localparam GHC__CAP__SAL__MASK = 'h2000000;
252 localparam GHC__CAP__SAL__DFLT = 'h0;
253 // RO: Supports Command List Override - no (not capable of clearing BSY and DRQ bits, needs soft reset
254 localparam GHC__CAP__SCLO__ADDR = 'h0;
255 localparam GHC__CAP__SCLO__MASK = 'h1000000;
256 localparam GHC__CAP__SCLO__DFLT = 'h0;
257 // RO: Interface Maximal speed: 2 - Gen2, 3 - Gen3
258 localparam GHC__CAP__ISS__ADDR = 'h0;
259 localparam GHC__CAP__ISS__MASK = 'hf00000;
260 localparam GHC__CAP__ISS__DFLT = 'h200000;
261 // RO: AHCI only (0 - legacy too)
262 localparam GHC__CAP__SAM__ADDR = 'h0;
263 localparam GHC__CAP__SAM__MASK = 'h40000;
264 localparam GHC__CAP__SAM__DFLT = 'h40000;
265 // RO: Supports Port Multiplier - no
266 localparam GHC__CAP__SPM__ADDR = 'h0;
267 localparam GHC__CAP__SPM__MASK = 'h20000;
268 localparam GHC__CAP__SPM__DFLT = 'h0;
269 // RO: Supports FIS-based switching of the Port Multiplier - no
270 localparam GHC__CAP__FBSS__ADDR = 'h0;
271 localparam GHC__CAP__FBSS__MASK = 'h10000;
272 localparam GHC__CAP__FBSS__DFLT = 'h0;
273 // RO: PIO Multiple DRQ block - no
274 localparam GHC__CAP__PMD__ADDR = 'h0;
275 localparam GHC__CAP__PMD__MASK = 'h8000;
276 localparam GHC__CAP__PMD__DFLT = 'h0;
277 // RO: Slumber State Capable - no
278 localparam GHC__CAP__SSC__ADDR = 'h0;
279 localparam GHC__CAP__SSC__MASK = 'h4000;
280 localparam GHC__CAP__SSC__DFLT = 'h0;
281 // RO: Partial State Capable - no
282 localparam GHC__CAP__PSC__ADDR = 'h0;
283 localparam GHC__CAP__PSC__MASK = 'h2000;
284 localparam GHC__CAP__PSC__DFLT = 'h0;
285 // RO: Number of Command Slots, 0-based (0 means 1?)
286 localparam GHC__CAP__NSC__ADDR = 'h0;
287 localparam GHC__CAP__NSC__MASK = 'h1f00;
288 localparam GHC__CAP__NSC__DFLT = 'h0;
289 // RO: Command Completion Coalescing - no
290 localparam GHC__CAP__CCCS__ADDR = 'h0;
291 localparam GHC__CAP__CCCS__MASK = 'h80;
292 localparam GHC__CAP__CCCS__DFLT = 'h0;
293 // RO: Enclosure Management - no
294 localparam GHC__CAP__EMS__ADDR = 'h0;
295 localparam GHC__CAP__EMS__MASK = 'h40;
296 localparam GHC__CAP__EMS__DFLT = 'h0;
297 // RO: External SATA connector - yes
298 localparam GHC__CAP__SXS__ADDR = 'h0;
299 localparam GHC__CAP__SXS__MASK = 'h20;
300 localparam GHC__CAP__SXS__DFLT = 'h20;
301 // RO: Number of Ports, 0-based (0 means 1?)
302 localparam GHC__CAP__NP__ADDR = 'h0;
303 localparam GHC__CAP__NP__MASK = 'h1f;
304 localparam GHC__CAP__NP__DFLT = 'h0;
305 // RO: AHCI enable (0 - legacy)
306 localparam GHC__GHC__AE__ADDR = 'h1;
307 localparam GHC__GHC__AE__MASK = 'h80000000;
308 localparam GHC__GHC__AE__DFLT = 'h80000000;
309 // RO: MSI Revert to Single Message
310 localparam GHC__GHC__MRSM__ADDR = 'h1;
311 localparam GHC__GHC__MRSM__MASK = 'h4;
312 localparam GHC__GHC__MRSM__DFLT = 'h0;
313 // RW: Interrupt Enable (all ports)
314 localparam GHC__GHC__IE__ADDR = 'h1;
315 localparam GHC__GHC__IE__MASK = 'h2;
316 localparam GHC__GHC__IE__DFLT = 'h0;
317 // RW1: HBA reset (COMINIT, ...). Set by software, cleared by hardware, section 10.4.3
318 localparam GHC__GHC__HR__ADDR = 'h1;
319 localparam GHC__GHC__HR__MASK = 'h1;
320 localparam GHC__GHC__HR__DFLT = 'h0;
321 // RWC: Interrupt Pending Status (per port)
322 localparam GHC__IS__IPS__ADDR = 'h2;
323 localparam GHC__IS__IPS__MASK = 'hffffffff;
324 localparam GHC__IS__IPS__DFLT = 'h0;
325 // RO: Ports Implemented
326 localparam GHC__PI__PI__ADDR = 'h3;
327 localparam GHC__PI__PI__MASK = 'hffffffff;
328 localparam GHC__PI__PI__DFLT = 'h1;
329 // RO: AHCI Major Version 1.
330 localparam GHC__VS__MJR__ADDR = 'h4;
331 localparam GHC__VS__MJR__MASK = 'hffff0000;
332 localparam GHC__VS__MJR__DFLT = 'h10000;
333 // RO: AHCI Minor Version 3.1
334 localparam GHC__VS__MNR__ADDR = 'h4;
335 localparam GHC__VS__MNR__MASK = 'hffff;
336 localparam GHC__VS__MNR__DFLT = 'h301;
337 // RO: DevSleep Entrance from Slumber Only
338 localparam GHC__CAP2__DESO__ADDR = 'h9;
339 localparam GHC__CAP2__DESO__MASK = 'h20;
340 localparam GHC__CAP2__DESO__DFLT = 'h0;
341 // RO: Supports Aggressive Device Sleep Management
342 localparam GHC__CAP2__SADM__ADDR = 'h9;
343 localparam GHC__CAP2__SADM__MASK = 'h10;
344 localparam GHC__CAP2__SADM__DFLT = 'h0;
345 // RO: Supports Device Sleep
346 localparam GHC__CAP2__SDS__ADDR = 'h9;
347 localparam GHC__CAP2__SDS__MASK = 'h8;
348 localparam GHC__CAP2__SDS__DFLT = 'h0;
349 // RO: Automatic Partial to Slumber Transitions
350 localparam GHC__CAP2__APST__ADDR = 'h9;
351 localparam GHC__CAP2__APST__MASK = 'h4;
352 localparam GHC__CAP2__APST__DFLT = 'h0;
353 // RO: NVMHCI Present (section 10.15)
354 localparam GHC__CAP2__NVMP__ADDR = 'h9;
355 localparam GHC__CAP2__NVMP__MASK = 'h2;
356 localparam GHC__CAP2__NVMP__DFLT = 'h0;
357 // RO: BIOS/OS Handoff - not supported
358 localparam GHC__CAP2__BOH__ADDR = 'h9;
359 localparam GHC__CAP2__BOH__MASK = 'h1;
360 localparam GHC__CAP2__BOH__DFLT = 'h0;
361 // RW: Command List Base Address (1KB aligned)
362 localparam HBA_PORT__PxCLB__CLB__ADDR = 'h40;
363 localparam HBA_PORT__PxCLB__CLB__MASK = 'hfffffc00;
364 localparam HBA_PORT__PxCLB__CLB__DFLT = 'h80000800;
365 // RW: Command List Base Address (1KB aligned)
366 localparam HBA_PORT__PxFB__CLB__ADDR = 'h42;
367 localparam HBA_PORT__PxFB__CLB__MASK = 'hffffff00;
368 localparam HBA_PORT__PxFB__CLB__DFLT = 'h80000c00;
369 // RWC: Cold Port Detect Status
370 localparam HBA_PORT__PxIS__CPDS__ADDR = 'h44;
371 localparam HBA_PORT__PxIS__CPDS__MASK = 'h80000000;
372 localparam HBA_PORT__PxIS__CPDS__DFLT = 'h0;
373 // RWC: Task File Error Status
374 localparam HBA_PORT__PxIS__TFES__ADDR = 'h44;
375 localparam HBA_PORT__PxIS__TFES__MASK = 'h40000000;
376 localparam HBA_PORT__PxIS__TFES__DFLT = 'h0;
377 // RWC: Host Bus (PCI) Fatal error
378 localparam HBA_PORT__PxIS__HBFS__ADDR = 'h44;
379 localparam HBA_PORT__PxIS__HBFS__MASK = 'h20000000;
380 localparam HBA_PORT__PxIS__HBFS__DFLT = 'h0;
381 // RWC: ECC error R/W system memory
382 localparam HBA_PORT__PxIS__HBDS__ADDR = 'h44;
383 localparam HBA_PORT__PxIS__HBDS__MASK = 'h10000000;
384 localparam HBA_PORT__PxIS__HBDS__DFLT = 'h0;
385 // RWC: Interface Fatal Error Status (sect. 6.1.2)
386 localparam HBA_PORT__PxIS__IFS__ADDR = 'h44;
387 localparam HBA_PORT__PxIS__IFS__MASK = 'h8000000;
388 localparam HBA_PORT__PxIS__IFS__DFLT = 'h0;
389 // RWC: Interface Non-Fatal Error Status (sect. 6.1.2)
390 localparam HBA_PORT__PxIS__INFS__ADDR = 'h44;
391 localparam HBA_PORT__PxIS__INFS__MASK = 'h4000000;
392 localparam HBA_PORT__PxIS__INFS__DFLT = 'h0;
393 // RWC: Overflow Status
394 localparam HBA_PORT__PxIS__OFS__ADDR = 'h44;
395 localparam HBA_PORT__PxIS__OFS__MASK = 'h1000000;
396 localparam HBA_PORT__PxIS__OFS__DFLT = 'h0;
397 // RWC: Incorrect Port Multiplier Status
398 localparam HBA_PORT__PxIS__IPMS__ADDR = 'h44;
399 localparam HBA_PORT__PxIS__IPMS__MASK = 'h800000;
400 localparam HBA_PORT__PxIS__IPMS__DFLT = 'h0;
401 // RO: PhyRdy changed Status
402 localparam HBA_PORT__PxIS__PRCS__ADDR = 'h44;
403 localparam HBA_PORT__PxIS__PRCS__MASK = 'h400000;
404 localparam HBA_PORT__PxIS__PRCS__DFLT = 'h0;
405 // RWC: Device Mechanical Presence Status
406 localparam HBA_PORT__PxIS__DMPS__ADDR = 'h44;
407 localparam HBA_PORT__PxIS__DMPS__MASK = 'h80;
408 localparam HBA_PORT__PxIS__DMPS__DFLT = 'h0;
409 // RO: Port Connect Change Status
410 localparam HBA_PORT__PxIS__PCS__ADDR = 'h44;
411 localparam HBA_PORT__PxIS__PCS__MASK = 'h40;
412 localparam HBA_PORT__PxIS__PCS__DFLT = 'h0;
413 // RWC: Descriptor Processed
414 localparam HBA_PORT__PxIS__DPS__ADDR = 'h44;
415 localparam HBA_PORT__PxIS__DPS__MASK = 'h20;
416 localparam HBA_PORT__PxIS__DPS__DFLT = 'h0;
418 localparam HBA_PORT__PxIS__UFS__ADDR = 'h44;
419 localparam HBA_PORT__PxIS__UFS__MASK = 'h10;
420 localparam HBA_PORT__PxIS__UFS__DFLT = 'h0;
421 // RWC: Set Device Bits Interrupt - Set Device bits FIS with 'I' bit set
422 localparam HBA_PORT__PxIS__SDBS__ADDR = 'h44;
423 localparam HBA_PORT__PxIS__SDBS__MASK = 'h8;
424 localparam HBA_PORT__PxIS__SDBS__DFLT = 'h0;
425 // RWC: DMA Setup FIS Interrupt - DMA Setup FIS received with 'I' bit set
426 localparam HBA_PORT__PxIS__DSS__ADDR = 'h44;
427 localparam HBA_PORT__PxIS__DSS__MASK = 'h4;
428 localparam HBA_PORT__PxIS__DSS__DFLT = 'h0;
429 // RWC: PIO Setup FIS Interrupt - PIO Setup FIS received with 'I' bit set
430 localparam HBA_PORT__PxIS__PSS__ADDR = 'h44;
431 localparam HBA_PORT__PxIS__PSS__MASK = 'h2;
432 localparam HBA_PORT__PxIS__PSS__DFLT = 'h0;
433 // RWC: D2H Register FIS Interrupt - D2H Register FIS received with 'I' bit set
434 localparam HBA_PORT__PxIS__DHRS__ADDR = 'h44;
435 localparam HBA_PORT__PxIS__DHRS__MASK = 'h1;
436 localparam HBA_PORT__PxIS__DHRS__DFLT = 'h0;
437 // RW: Cold Port Detect Enable
438 localparam HBA_PORT__PxIE__CPDE__ADDR = 'h45;
439 localparam HBA_PORT__PxIE__CPDE__MASK = 'h80000000;
440 localparam HBA_PORT__PxIE__CPDE__DFLT = 'h0;
441 // RW: Task File Error Enable
442 localparam HBA_PORT__PxIE__TFEE__ADDR = 'h45;
443 localparam HBA_PORT__PxIE__TFEE__MASK = 'h40000000;
444 localparam HBA_PORT__PxIE__TFEE__DFLT = 'h0;
445 // RW: Host Bus (PCI) Fatal Error Enable
446 localparam HBA_PORT__PxIE__HBFE__ADDR = 'h45;
447 localparam HBA_PORT__PxIE__HBFE__MASK = 'h20000000;
448 localparam HBA_PORT__PxIE__HBFE__DFLT = 'h0;
449 // RW: ECC Error R/W System Memory Enable
450 localparam HBA_PORT__PxIE__HBDE__ADDR = 'h45;
451 localparam HBA_PORT__PxIE__HBDE__MASK = 'h10000000;
452 localparam HBA_PORT__PxIE__HBDE__DFLT = 'h0;
453 // RW: Interface Fatal Error Enable (sect. 6.1.2)
454 localparam HBA_PORT__PxIE__IFE__ADDR = 'h45;
455 localparam HBA_PORT__PxIE__IFE__MASK = 'h8000000;
456 localparam HBA_PORT__PxIE__IFE__DFLT = 'h0;
457 // RW: Interface Non-Fatal Error Enable (sect. 6.1.2)
458 localparam HBA_PORT__PxIE__INFE__ADDR = 'h45;
459 localparam HBA_PORT__PxIE__INFE__MASK = 'h4000000;
460 localparam HBA_PORT__PxIE__INFE__DFLT = 'h0;
461 // RW: Overflow Enable
462 localparam HBA_PORT__PxIE__OFE__ADDR = 'h45;
463 localparam HBA_PORT__PxIE__OFE__MASK = 'h1000000;
464 localparam HBA_PORT__PxIE__OFE__DFLT = 'h0;
465 // RW: Incorrect Port Multiplier Enable
466 localparam HBA_PORT__PxIE__IPME__ADDR = 'h45;
467 localparam HBA_PORT__PxIE__IPME__MASK = 'h800000;
468 localparam HBA_PORT__PxIE__IPME__DFLT = 'h0;
469 // RW: PhyRdy changed Enable
470 localparam HBA_PORT__PxIE__PRCE__ADDR = 'h45;
471 localparam HBA_PORT__PxIE__PRCE__MASK = 'h400000;
472 localparam HBA_PORT__PxIE__PRCE__DFLT = 'h0;
473 // RO: Device Mechanical Presence Interrupt Enable
474 localparam HBA_PORT__PxIE__DMPE__ADDR = 'h45;
475 localparam HBA_PORT__PxIE__DMPE__MASK = 'h80;
476 localparam HBA_PORT__PxIE__DMPE__DFLT = 'h0;
477 // RW: Port Connect Change Interrupt Enable
478 localparam HBA_PORT__PxIE__PCE__ADDR = 'h45;
479 localparam HBA_PORT__PxIE__PCE__MASK = 'h40;
480 localparam HBA_PORT__PxIE__PCE__DFLT = 'h0;
481 // RW: Descriptor Processed Interrupt Enable
482 localparam HBA_PORT__PxIE__DPE__ADDR = 'h45;
483 localparam HBA_PORT__PxIE__DPE__MASK = 'h20;
484 localparam HBA_PORT__PxIE__DPE__DFLT = 'h0;
486 localparam HBA_PORT__PxIE__UFE__ADDR = 'h45;
487 localparam HBA_PORT__PxIE__UFE__MASK = 'h10;
488 localparam HBA_PORT__PxIE__UFE__DFLT = 'h0;
489 // RW: Device Bits Interrupt Enable
490 localparam HBA_PORT__PxIE__SDBE__ADDR = 'h45;
491 localparam HBA_PORT__PxIE__SDBE__MASK = 'h8;
492 localparam HBA_PORT__PxIE__SDBE__DFLT = 'h0;
493 // RW: DMA Setup FIS Interrupt Enable
494 localparam HBA_PORT__PxIE__DSE__ADDR = 'h45;
495 localparam HBA_PORT__PxIE__DSE__MASK = 'h4;
496 localparam HBA_PORT__PxIE__DSE__DFLT = 'h0;
497 // RW: PIO Setup FIS Interrupt Enable
498 localparam HBA_PORT__PxIE__PSE__ADDR = 'h45;
499 localparam HBA_PORT__PxIE__PSE__MASK = 'h2;
500 localparam HBA_PORT__PxIE__PSE__DFLT = 'h0;
501 // RW: D2H Register FIS Interrupt Enable
502 localparam HBA_PORT__PxIE__DHRE__ADDR = 'h45;
503 localparam HBA_PORT__PxIE__DHRE__MASK = 'h1;
504 localparam HBA_PORT__PxIE__DHRE__DFLT = 'h0;
505 // RW: Interface Communication Control
506 localparam HBA_PORT__PxCMD__ICC__ADDR = 'h46;
507 localparam HBA_PORT__PxCMD__ICC__MASK = 'hf0000000;
508 localparam HBA_PORT__PxCMD__ICC__DFLT = 'h0;
509 // RO: Aggressive Slumber/Partial - not implemented
510 localparam HBA_PORT__PxCMD__ASP__ADDR = 'h46;
511 localparam HBA_PORT__PxCMD__ASP__MASK = 'h8000000;
512 localparam HBA_PORT__PxCMD__ASP__DFLT = 'h0;
513 // RO: Aggressive Link Power Management Enable - not implemented
514 localparam HBA_PORT__PxCMD__ALPE__ADDR = 'h46;
515 localparam HBA_PORT__PxCMD__ALPE__MASK = 'h4000000;
516 localparam HBA_PORT__PxCMD__ALPE__DFLT = 'h0;
517 // RW: Drive LED on ATAPI enable
518 localparam HBA_PORT__PxCMD__DLAE__ADDR = 'h46;
519 localparam HBA_PORT__PxCMD__DLAE__MASK = 'h2000000;
520 localparam HBA_PORT__PxCMD__DLAE__DFLT = 'h0;
521 // RW: Device is ATAPI (for activity LED)
522 localparam HBA_PORT__PxCMD__ATAPI__ADDR = 'h46;
523 localparam HBA_PORT__PxCMD__ATAPI__MASK = 'h1000000;
524 localparam HBA_PORT__PxCMD__ATAPI__DFLT = 'h0;
525 // RW: Automatic Partial to Slumber Transitions Enabled
526 localparam HBA_PORT__PxCMD__APSTE__ADDR = 'h46;
527 localparam HBA_PORT__PxCMD__APSTE__MASK = 'h800000;
528 localparam HBA_PORT__PxCMD__APSTE__DFLT = 'h0;
529 // RO: FIS-Based Switching Capable Port - not implemented
530 localparam HBA_PORT__PxCMD__FBSCP__ADDR = 'h46;
531 localparam HBA_PORT__PxCMD__FBSCP__MASK = 'h400000;
532 localparam HBA_PORT__PxCMD__FBSCP__DFLT = 'h0;
533 // RO: External SATA port
534 localparam HBA_PORT__PxCMD__ESP__ADDR = 'h46;
535 localparam HBA_PORT__PxCMD__ESP__MASK = 'h200000;
536 localparam HBA_PORT__PxCMD__ESP__DFLT = 'h200000;
537 // RO: Cold Presence Detection
538 localparam HBA_PORT__PxCMD__CPD__ADDR = 'h46;
539 localparam HBA_PORT__PxCMD__CPD__MASK = 'h100000;
540 localparam HBA_PORT__PxCMD__CPD__DFLT = 'h0;
541 // RO: Mechanical Presence Switch Attached to Port
542 localparam HBA_PORT__PxCMD__MPSP__ADDR = 'h46;
543 localparam HBA_PORT__PxCMD__MPSP__MASK = 'h80000;
544 localparam HBA_PORT__PxCMD__MPSP__DFLT = 'h0;
545 // RO: Hot Plug Capable Port
546 localparam HBA_PORT__PxCMD__HPCP__ADDR = 'h46;
547 localparam HBA_PORT__PxCMD__HPCP__MASK = 'h40000;
548 localparam HBA_PORT__PxCMD__HPCP__DFLT = 'h40000;
549 // RW: Port Multiplier Attached - not implemented (software should write this bit)
550 localparam HBA_PORT__PxCMD__PMA__ADDR = 'h46;
551 localparam HBA_PORT__PxCMD__PMA__MASK = 'h20000;
552 localparam HBA_PORT__PxCMD__PMA__DFLT = 'h0;
553 // RO: Cold Presence State
554 localparam HBA_PORT__PxCMD__CPS__ADDR = 'h46;
555 localparam HBA_PORT__PxCMD__CPS__MASK = 'h10000;
556 localparam HBA_PORT__PxCMD__CPS__DFLT = 'h0;
557 // RO: Command List Running (section 5.3.2)
558 localparam HBA_PORT__PxCMD__CR__ADDR = 'h46;
559 localparam HBA_PORT__PxCMD__CR__MASK = 'h8000;
560 localparam HBA_PORT__PxCMD__CR__DFLT = 'h0;
561 // RO: FIS Receive Running (section 10.3.2)
562 localparam HBA_PORT__PxCMD__FR__ADDR = 'h46;
563 localparam HBA_PORT__PxCMD__FR__MASK = 'h4000;
564 localparam HBA_PORT__PxCMD__FR__DFLT = 'h0;
565 // RO: Mechanical Presence Switch State
566 localparam HBA_PORT__PxCMD__MPSS__ADDR = 'h46;
567 localparam HBA_PORT__PxCMD__MPSS__MASK = 'h2000;
568 localparam HBA_PORT__PxCMD__MPSS__DFLT = 'h0;
569 // RO: Current Command Slot (when PxCMD.ST 1-> ) should be reset to 0, when 0->1 - highest priority is 0
570 localparam HBA_PORT__PxCMD__CCS__ADDR = 'h46;
571 localparam HBA_PORT__PxCMD__CCS__MASK = 'h1f00;
572 localparam HBA_PORT__PxCMD__CCS__DFLT = 'h0;
573 // RW: FIS Receive Enable (enable after FIS memory is set)
574 localparam HBA_PORT__PxCMD__FRE__ADDR = 'h46;
575 localparam HBA_PORT__PxCMD__FRE__MASK = 'h10;
576 localparam HBA_PORT__PxCMD__FRE__DFLT = 'h0;
577 // RW1: Command List Override
578 localparam HBA_PORT__PxCMD__CLO__ADDR = 'h46;
579 localparam HBA_PORT__PxCMD__CLO__MASK = 'h8;
580 localparam HBA_PORT__PxCMD__CLO__DFLT = 'h0;
581 // RO: Power On Device (RW with Cold Presence Detection)
582 localparam HBA_PORT__PxCMD__POD__ADDR = 'h46;
583 localparam HBA_PORT__PxCMD__POD__MASK = 'h4;
584 localparam HBA_PORT__PxCMD__POD__DFLT = 'h4;
585 // RO: Spin-Up Device (RW with Staggered Spin-Up Support)
586 localparam HBA_PORT__PxCMD__SUD__ADDR = 'h46;
587 localparam HBA_PORT__PxCMD__SUD__MASK = 'h2;
588 localparam HBA_PORT__PxCMD__SUD__DFLT = 'h2;
589 // RW: Start (HBA may process commands). See section 10.3.1
590 localparam HBA_PORT__PxCMD__ST__ADDR = 'h46;
591 localparam HBA_PORT__PxCMD__ST__MASK = 'h1;
592 localparam HBA_PORT__PxCMD__ST__DFLT = 'h0;
593 // RO: Latest Copy of Task File Error Register
594 localparam HBA_PORT__PxTFD__ERR__ADDR = 'h48;
595 localparam HBA_PORT__PxTFD__ERR__MASK = 'hff00;
596 localparam HBA_PORT__PxTFD__ERR__DFLT = 'h0;
597 // RO: Latest Copy of Task File Status Register: BSY
598 localparam HBA_PORT__PxTFD__STS__BSY__ADDR = 'h48;
599 localparam HBA_PORT__PxTFD__STS__BSY__MASK = 'h80;
600 localparam HBA_PORT__PxTFD__STS__BSY__DFLT = 'h0;
601 // RO: Latest Copy of Task File Status Register: command-specific bits 4..6
602 localparam HBA_PORT__PxTFD__STS__64__ADDR = 'h48;
603 localparam HBA_PORT__PxTFD__STS__64__MASK = 'h70;
604 localparam HBA_PORT__PxTFD__STS__64__DFLT = 'h0;
605 // RO: Latest Copy of Task File Status Register: DRQ
606 localparam HBA_PORT__PxTFD__STS__DRQ__ADDR = 'h48;
607 localparam HBA_PORT__PxTFD__STS__DRQ__MASK = 'h8;
608 localparam HBA_PORT__PxTFD__STS__DRQ__DFLT = 'h0;
609 // RO: Latest Copy of Task File Status Register: command-specific bits 1..2
610 localparam HBA_PORT__PxTFD__STS__12__ADDR = 'h48;
611 localparam HBA_PORT__PxTFD__STS__12__MASK = 'h6;
612 localparam HBA_PORT__PxTFD__STS__12__DFLT = 'h0;
613 // RO: Latest Copy of Task File Status Register: ERR
614 localparam HBA_PORT__PxTFD__STS__ERR__ADDR = 'h48;
615 localparam HBA_PORT__PxTFD__STS__ERR__MASK = 'h1;
616 localparam HBA_PORT__PxTFD__STS__ERR__DFLT = 'h0;
617 // RO: Data in the first D2H Register FIS
618 localparam HBA_PORT__PxSIG__SIG__ADDR = 'h49;
619 localparam HBA_PORT__PxSIG__SIG__MASK = 'hffffffff;
620 localparam HBA_PORT__PxSIG__SIG__DFLT = 'hffffffff;
621 // RO: Interface Power Management
622 localparam HBA_PORT__PxSSTS__IPM__ADDR = 'h4a;
623 localparam HBA_PORT__PxSSTS__IPM__MASK = 'hf00;
624 localparam HBA_PORT__PxSSTS__IPM__DFLT = 'h0;
625 // RO: Interface Speed
626 localparam HBA_PORT__PxSSTS__SPD__ADDR = 'h4a;
627 localparam HBA_PORT__PxSSTS__SPD__MASK = 'hf0;
628 localparam HBA_PORT__PxSSTS__SPD__DFLT = 'h0;
629 // RO: Device Detection (should be detected if COMINIT is received)
630 localparam HBA_PORT__PxSSTS__DET__ADDR = 'h4a;
631 localparam HBA_PORT__PxSSTS__DET__MASK = 'hf;
632 localparam HBA_PORT__PxSSTS__DET__DFLT = 'h0;
633 // RO: Port Multiplier Port - not used by AHCI
634 localparam HBA_PORT__PxSCTL__PMP__ADDR = 'h4b;
635 localparam HBA_PORT__PxSCTL__PMP__MASK = 'hf0000;
636 localparam HBA_PORT__PxSCTL__PMP__DFLT = 'h0;
637 // RO: Select Power Management - not used by AHCI
638 localparam HBA_PORT__PxSCTL__SPM__ADDR = 'h4b;
639 localparam HBA_PORT__PxSCTL__SPM__MASK = 'hf000;
640 localparam HBA_PORT__PxSCTL__SPM__DFLT = 'h0;
641 // RW: Interface Power Management Transitions Allowed
642 localparam HBA_PORT__PxSCTL__IPM__ADDR = 'h4b;
643 localparam HBA_PORT__PxSCTL__IPM__MASK = 'hf00;
644 localparam HBA_PORT__PxSCTL__IPM__DFLT = 'h0;
645 // RW: Interface Highest Speed
646 localparam HBA_PORT__PxSCTL__SPD__ADDR = 'h4b;
647 localparam HBA_PORT__PxSCTL__SPD__MASK = 'hf0;
648 localparam HBA_PORT__PxSCTL__SPD__DFLT = 'h0;
649 // RW: Device Detection Initialization
650 localparam HBA_PORT__PxSCTL__DET__ADDR = 'h4b;
651 localparam HBA_PORT__PxSCTL__DET__MASK = 'hf;
652 localparam HBA_PORT__PxSCTL__DET__DFLT = 'h0;
653 // RWC: Exchanged (set on COMINIT), reflected in PxIS.PCS
654 localparam HBA_PORT__PxSERR__DIAG__X__ADDR = 'h4c;
655 localparam HBA_PORT__PxSERR__DIAG__X__MASK = 'h4000000;
656 localparam HBA_PORT__PxSERR__DIAG__X__DFLT = 'h0;
658 localparam HBA_PORT__PxSERR__DIAG__F__ADDR = 'h4c;
659 localparam HBA_PORT__PxSERR__DIAG__F__MASK = 'h2000000;
660 localparam HBA_PORT__PxSERR__DIAG__F__DFLT = 'h0;
661 // RWC: Transport state transition error
662 localparam HBA_PORT__PxSERR__DIAG__T__ADDR = 'h4c;
663 localparam HBA_PORT__PxSERR__DIAG__T__MASK = 'h1000000;
664 localparam HBA_PORT__PxSERR__DIAG__T__DFLT = 'h0;
665 // RWC: Link sequence error
666 localparam HBA_PORT__PxSERR__DIAG__S__ADDR = 'h4c;
667 localparam HBA_PORT__PxSERR__DIAG__S__MASK = 'h800000;
668 localparam HBA_PORT__PxSERR__DIAG__S__DFLT = 'h0;
669 // RWC: Handshake Error (i.e. Device got CRC error)
670 localparam HBA_PORT__PxSERR__DIAG__H__ADDR = 'h4c;
671 localparam HBA_PORT__PxSERR__DIAG__H__MASK = 'h400000;
672 localparam HBA_PORT__PxSERR__DIAG__H__DFLT = 'h0;
673 // RWC: CRC error in Link layer
674 localparam HBA_PORT__PxSERR__DIAG__C__ADDR = 'h4c;
675 localparam HBA_PORT__PxSERR__DIAG__C__MASK = 'h200000;
676 localparam HBA_PORT__PxSERR__DIAG__C__DFLT = 'h0;
677 // RWC: Disparity Error - not used by AHCI
678 localparam HBA_PORT__PxSERR__DIAG__D__ADDR = 'h4c;
679 localparam HBA_PORT__PxSERR__DIAG__D__MASK = 'h100000;
680 localparam HBA_PORT__PxSERR__DIAG__D__DFLT = 'h0;
681 // RWC: 10B to 8B decode error
682 localparam HBA_PORT__PxSERR__DIAG__B__ADDR = 'h4c;
683 localparam HBA_PORT__PxSERR__DIAG__B__MASK = 'h80000;
684 localparam HBA_PORT__PxSERR__DIAG__B__DFLT = 'h0;
685 // RWC: COMMWAKE signal was detected
686 localparam HBA_PORT__PxSERR__DIAG__W__ADDR = 'h4c;
687 localparam HBA_PORT__PxSERR__DIAG__W__MASK = 'h40000;
688 localparam HBA_PORT__PxSERR__DIAG__W__DFLT = 'h0;
689 // RWC: PHY Internal Error
690 localparam HBA_PORT__PxSERR__DIAG__I__ADDR = 'h4c;
691 localparam HBA_PORT__PxSERR__DIAG__I__MASK = 'h20000;
692 localparam HBA_PORT__PxSERR__DIAG__I__DFLT = 'h0;
693 // RWC: PhyRdy changed. Reflected in PxIS.PRCS bit.
694 localparam HBA_PORT__PxSERR__DIAG__N__ADDR = 'h4c;
695 localparam HBA_PORT__PxSERR__DIAG__N__MASK = 'h10000;
696 localparam HBA_PORT__PxSERR__DIAG__N__DFLT = 'h0;
697 // RWC: Internal Error
698 localparam HBA_PORT__PxSERR__ERR__E__ADDR = 'h4c;
699 localparam HBA_PORT__PxSERR__ERR__E__MASK = 'h800;
700 localparam HBA_PORT__PxSERR__ERR__E__DFLT = 'h0;
701 // RWC: Protocol Error - a violation of SATA protocol detected
702 localparam HBA_PORT__PxSERR__ERR__P__ADDR = 'h4c;
703 localparam HBA_PORT__PxSERR__ERR__P__MASK = 'h400;
704 localparam HBA_PORT__PxSERR__ERR__P__DFLT = 'h0;
705 // RWC: Persistent Communication or Data Integrity Error
706 localparam HBA_PORT__PxSERR__ERR__C__ADDR = 'h4c;
707 localparam HBA_PORT__PxSERR__ERR__C__MASK = 'h200;
708 localparam HBA_PORT__PxSERR__ERR__C__DFLT = 'h0;
709 // RWC: Transient Data Integrity Error (error not recovered by the interface)
710 localparam HBA_PORT__PxSERR__ERR__T__ADDR = 'h4c;
711 localparam HBA_PORT__PxSERR__ERR__T__MASK = 'h100;
712 localparam HBA_PORT__PxSERR__ERR__T__DFLT = 'h0;
713 // RWC: Communication between the device and host was lost but re-established
714 localparam HBA_PORT__PxSERR__ERR__M__ADDR = 'h4c;
715 localparam HBA_PORT__PxSERR__ERR__M__MASK = 'h2;
716 localparam HBA_PORT__PxSERR__ERR__M__DFLT = 'h0;
717 // RWC: Recovered Data integrity Error
718 localparam HBA_PORT__PxSERR__ERR__I__ADDR = 'h4c;
719 localparam HBA_PORT__PxSERR__ERR__I__MASK = 'h1;
720 localparam HBA_PORT__PxSERR__ERR__I__DFLT = 'h0;
721 // RW1: Device Status: bit per Port, for TAG in native queued command
722 localparam HBA_PORT__PxSACT__DS__ADDR = 'h4d;
723 localparam HBA_PORT__PxSACT__DS__MASK = 'hffffffff;
724 localparam HBA_PORT__PxSACT__DS__DFLT = 'h0;
725 // RW1: Command Issued: bit per Port, only set when PxCMD.ST==1, also cleared by PxCMD.ST: 1->0 by soft
726 localparam HBA_PORT__PxCI__CI__ADDR = 'h4e;
727 localparam HBA_PORT__PxCI__CI__MASK = 'hffffffff;
728 localparam HBA_PORT__PxCI__CI__DFLT = 'h0;
729 // RWC: PM Notify (bit per PM port)
730 localparam HBA_PORT__PxSNTF__PMN__ADDR = 'h4f;
731 localparam HBA_PORT__PxSNTF__PMN__MASK = 'hffff;
732 localparam HBA_PORT__PxSNTF__PMN__DFLT = 'h0;
733 // RO: Device with Error
734 localparam HBA_PORT__PxFBS__DWE__ADDR = 'h50;
735 localparam HBA_PORT__PxFBS__DWE__MASK = 'hf0000;
736 localparam HBA_PORT__PxFBS__DWE__DFLT = 'h0;
737 // RO: Active Device Optimization
738 localparam HBA_PORT__PxFBS__ADO__ADDR = 'h50;
739 localparam HBA_PORT__PxFBS__ADO__MASK = 'hf000;
740 localparam HBA_PORT__PxFBS__ADO__DFLT = 'h0;
741 // RW: Device To Issue
742 localparam HBA_PORT__PxFBS__DEV__ADDR = 'h50;
743 localparam HBA_PORT__PxFBS__DEV__MASK = 'hf00;
744 localparam HBA_PORT__PxFBS__DEV__DFLT = 'h0;
745 // RO: Single Device Error
746 localparam HBA_PORT__PxFBS__SDE__ADDR = 'h50;
747 localparam HBA_PORT__PxFBS__SDE__MASK = 'h4;
748 localparam HBA_PORT__PxFBS__SDE__DFLT = 'h0;
749 // RW1: Device Error Clear
750 localparam HBA_PORT__PxFBS__DEC__ADDR = 'h50;
751 localparam HBA_PORT__PxFBS__DEC__MASK = 'h2;
752 localparam HBA_PORT__PxFBS__DEC__DFLT = 'h0;
754 localparam HBA_PORT__PxFBS__EN__ADDR = 'h50;
755 localparam HBA_PORT__PxFBS__EN__MASK = 'h1;
756 localparam HBA_PORT__PxFBS__EN__DFLT = 'h0;
757 // RO: DITO Multiplier
758 localparam HBA_PORT__PxDEVSLP__DM__ADDR = 'h51;
759 localparam HBA_PORT__PxDEVSLP__DM__MASK = 'h1e000000;
760 localparam HBA_PORT__PxDEVSLP__DM__DFLT = 'h0;
761 // RW: Device Sleep Idle Timeout (section 8.5.1.1.1)
762 localparam HBA_PORT__PxDEVSLP__DITO__ADDR = 'h51;
763 localparam HBA_PORT__PxDEVSLP__DITO__MASK = 'h1ff8000;
764 localparam HBA_PORT__PxDEVSLP__DITO__DFLT = 'h0;
765 // RW: Minimum Device Sleep Assertion Time
766 localparam HBA_PORT__PxDEVSLP__MDAT__ADDR = 'h51;
767 localparam HBA_PORT__PxDEVSLP__MDAT__MASK = 'h7c00;
768 localparam HBA_PORT__PxDEVSLP__MDAT__DFLT = 'h0;
769 // RW: Device Sleep Exit Timeout
770 localparam HBA_PORT__PxDEVSLP__DETO__ADDR = 'h51;
771 localparam HBA_PORT__PxDEVSLP__DETO__MASK = 'h3fc;
772 localparam HBA_PORT__PxDEVSLP__DETO__DFLT = 'h0;
773 // RO: Device Sleep Present
774 localparam HBA_PORT__PxDEVSLP__DSP__ADDR = 'h51;
775 localparam HBA_PORT__PxDEVSLP__DSP__MASK = 'h2;
776 localparam HBA_PORT__PxDEVSLP__DSP__DFLT = 'h0;
777 // RO: Aggressive Device Sleep Enable
778 localparam HBA_PORT__PxDEVSLP__ADSE__ADDR = 'h51;
779 localparam HBA_PORT__PxDEVSLP__ADSE__MASK = 'h1;
780 localparam HBA_PORT__PxDEVSLP__ADSE__DFLT = 'h0;
781 // RW: SAXIHP write channel cache mode
782 localparam HBA_PORT__AFI_CACHE__WR_CM__ADDR = 'h5c;
783 localparam HBA_PORT__AFI_CACHE__WR_CM__MASK = 'hf0;
784 localparam HBA_PORT__AFI_CACHE__WR_CM__DFLT = 'h30;
785 // RW: SAXIHP read channel cache mode
786 localparam HBA_PORT__AFI_CACHE__RD_CM__ADDR = 'h5c;
787 localparam HBA_PORT__AFI_CACHE__RD_CM__MASK = 'hf;
788 localparam HBA_PORT__AFI_CACHE__RD_CM__DFLT = 'h3;
789 // RW: Address/not data for programming AHCI state machine
790 localparam HBA_PORT__PGM_AHCI_SM__AnD__ADDR = 'h5d;
791 localparam HBA_PORT__PGM_AHCI_SM__AnD__MASK = 'h1000000;
792 localparam HBA_PORT__PGM_AHCI_SM__AnD__DFLT = 'h0;
793 // RW: Program address/data for programming AHCI state machine
794 localparam HBA_PORT__PGM_AHCI_SM__PGM_AD__ADDR = 'h5d;
795 localparam HBA_PORT__PGM_AHCI_SM__PGM_AD__MASK = 'h3ffff;
796 localparam HBA_PORT__PGM_AHCI_SM__PGM_AD__DFLT = 'h0;
797 // RW: 3-bit tag to add to the recorded timestamp
798 localparam HBA_PORT__PunchTime__TAG__ADDR = 'h5e;
799 localparam HBA_PORT__PunchTime__TAG__MASK = 'h7;
800 localparam HBA_PORT__PunchTime__TAG__DFLT = 'h0;
1.8.12