47 input ext_we,
// external write enable 51 input [
1:
0]
rpage_in,
// will register to wclk, input OK with mclk 52 input rpage_set,
// set internal read page to rpage_in 53 input page_next,
// advance to next page (and reset lower bits to 0) 54 output [
1:
0]
page,
// current internal page 55 input rd,
// read buffer to memory, increment read address (regester enable will be delayed) 63 always @ (
posedge rclk)
begin 86 .
web (
8'hff),
// input[3:0]
[1 << LOG2WIDTH_WR-1:0] 11872data_in
[14-LOG2WIDTH_WR:0] 11869waddr
[1 << LOG2WIDTH_RD-1:0] 11867data_out
[14-LOG2WIDTH_RD:0] 11864raddr
ram_var_w_var_r_i ram_var_w_var_r
[1 << LOG2WIDTH_WR-1:0] 5202ext_data_in
integer 5198LOG2WIDTH_WR5
[14-LOG2WIDTH_WR:0] 5200ext_waddr