memctrl Directory Reference

Directories
directory	phy

Files
file	cmd_encod_4mux.v [code]
	4-to-1 mux to cmbine memory sequences sources
file	cmd_encod_linear_mux.v [code]
	Multiplex parameters from multiple channels sharing the same linear command encoders (cmd_encod_linear_rd and cmd_encod_linear_wr) Latency 1 clcok cycle.
file	cmd_encod_linear_rd.v [code]
	Command sequencer generator for reading a sequential up to 1KB page single page access, bank and row will not be changed.
file	cmd_encod_linear_rw.v [code]
	Combining 2 modules:cmd_encod_linear_rd and cmd_encod_linear_wr.
file	cmd_encod_linear_wr.v [code]
	Command sequencer generator for writing a sequential up to 1KB page single page access, bank and row will not be changed.
file	cmd_encod_tiled_32_rd.v [code]
	Command sequencer generator for reading a tiled area up to 1 kB. Memory is mapped so 8 consecuitive rows have same RA, CA and alternating BA (0 to 7). Data will be read in columns 32 bytes wide, then proceding to the next column (if >1). This is a modification of module: cmd_encod_tiled_32_rd, just reading 32 bytes per row instead of the 16 - that eases timing Start burst should be even (LSB is ignored)
file	cmd_encod_tiled_32_rw.v [code]
	Combines cmd_encod_tiled_32_rd and cmd_encod_tiled_32_wr modules.
file	cmd_encod_tiled_32_wr.v [code]
	Command sequencer generator for writing a tiled area up to 1 kB. Memory is mapped so 8 consecuitive rows have same RA, CA and alternating BA (0 to 7). Data will be read in columns 16 bytes wide, then proceding to the next column (if >1). This is a modification of module: cmd_encod_tiled_32_wr, just writing 32 bytes per row instead of the 16 - that eases timing Start burst should be even (LSB is ignored)
file	cmd_encod_tiled_mux.v [code]
	Multiplex parameters from multiple channels sharing the same tiled command encoders (cmd_encod_tiled_rd and cmd_encod_tiled_wr) Latency 1 clcok cycle.
file	cmd_encod_tiled_rd.v [code]
	Command sequencer generator for reading a tiled area up to 1 kB.
file	cmd_encod_tiled_rw.v [code]
	Combines cmd_encod_tiled_rd and cmd_encod_tiled_wr modules.
file	cmd_encod_tiled_wr.v [code]
	Command sequencer generator for writing a tiled area up to 1 kB.
file	ddr_refresh.v [code]
	DDR3 memory refresh request module.
file	mcntrl393.v [code]
	Top level memory controller for 393 camera, includes channel buffers.
file	mcntrl393_test01.v [code]
	Temporary module to interface mcntrl393 control signals.
file	mcntrl_1kx32r.v [code]
	Paged buffer for ddr3 controller read channel with address autoincrement. 32 bit external data.
file	mcntrl_1kx32w.v [code]
	Paged buffer for ddr3 controller write channel with address autoincrement. 32 bit external data. Extends rd to regen.
file	mcntrl_buf_rd.v [code]
	Paged buffer for ddr3 controller read channel with address autoincrement. Variable width external data.
file	mcntrl_buf_wr.v [code]
	Paged buffer for ddr3 controller write channel with address autoincrement. 32 bit external data. Extends rd to regen.
file	mcntrl_linear_rw.v [code]
	Organize paged R/W from DDR3 memory in scan-line order with window support.
file	mcntrl_ps_pio.v [code]
	Read/write channels to DDR3 memory with software-programmable command sequence.
file	mcntrl_tiled_rw.v [code]
	Organize paged R/W from DDR3 memory in tiled order with window support Tiles spreading over two different frames is not yet supported (needed for line-scan mode in JPEG (JP4 - OK)
file	memctrl16.v [code]
	16-channel memory controller
file	scheduler16.v [code]
	16-channel programmable DDR memory access scheduler