2 * @file x393_mcontr_encode_cmd.vh
4 * @author Andrey Filippov
6 * @brief Functions used to encode memory controller sequences
8 * @copyright Copyright (c) 2015 Elphel, Inc.
12 * x393_mcontr_encode_cmd.vh is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation, either version 3 of the License, or
15 * (at your option) any later version.
17 * x393_mcontr_encode_cmd.vh is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program. If not, see <http://www.gnu.org/licenses/> .
25 * Additional permission under GNU GPL version 3 section 7:
26 * If you modify this Program, or any covered work, by linking or combining it
27 * with independent modules provided by the FPGA vendor only (this permission
28 * does not extend to any 3-rd party modules, "soft cores" or macros) under
29 * different license terms solely for the purpose of generating binary "bitstream"
30 * files and/or simulating the code, the copyright holders of this Program give
31 * you the right to distribute the covered work without those independent modules
32 * as long as the source code for them is available from the FPGA vendor free of
33 * charge, and there is no dependence on any encrypted modules for simulating of
34 * the combined code. This permission applies to you if the distributed code
35 * contains all the components and scripts required to completely simulate it
36 * with at least one of the Free Software programs.
39 function [31:0] func_encode_cmd;
40 input [14:0] addr; // 15-bit row/column address
41 input [2:0] bank; // bank (here OK to be any)
42 input [2:0] rcw; // RAS/CAS/WE, positive logic
43 input odt_en; // enable ODT
44 input cke; // disable CKE
45 input sel; // first/second half-cycle, other will be nop (cke+odt applicable to both)
46 input dq_en; // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
47 input dqs_en; // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
48 input dqs_toggle; // enable toggle DQS according to the pattern
49 input dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
50 input buf_wr; // connect to external buffer (but only if not paused)
51 input buf_rd; // connect to external buffer (but only if not paused)
52 input nop; // add NOP after the current command, keep other data
53 input buf_rst; // connect to external buffer (but only if not paused)
56 addr[14:0], // 15-bit row/column address
58 rcw[2:0], // RAS/CAS/WE
60 cke, // may be optimized (removed from here)?
61 sel, // first/second half-cycle, other will be nop (cke+odt applicable to both)
62 dq_en, // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
63 dqs_en, // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
64 dqs_toggle, // enable toggle DQS according to the pattern
65 dci, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
66 buf_wr, // phy_buf_wr, // connect to external buffer (but only if not paused)
67 buf_rd, // phy_buf_rd, // connect to external buffer (but only if not paused)
68 nop, // add NOP after the current command, keep other data
69 buf_rst // Reserved for future use
74 function [31:0] func_encode_skip;
75 input [CMD_PAUSE_BITS-1:0] skip; // number of extra cycles to skip (and keep all the other outputs)
76 input done; // end of sequence
77 input [2:0] bank; // bank (here OK to be any)
78 input odt_en; // enable ODT
79 input cke; // disable CKE
80 input sel; // first/second half-cycle, other will be nop (cke+odt applicable to both)
81 input dq_en; // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
82 input dqs_en; // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
83 input dqs_toggle; // enable toggle DQS according to the pattern
84 input dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
85 input buf_wr; // connect to external buffer (but only if not paused)
86 input buf_rd; // connect to external buffer (but only if not paused)
87 input buf_rst; // connect to external buffer (but only if not paused)
89 func_encode_skip= func_encode_cmd (
90 {{14-CMD_DONE_BIT{1'b0}}, done, skip[CMD_PAUSE_BITS-1:0]}, // 15-bit row/column address
91 bank[2:0], // bank (here OK to be any)
92 3'b0, // RAS/CAS/WE, positive logic
95 sel, // first/second half-cycle, other will be nop (cke+odt applicable to both)
96 dq_en, // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
97 dqs_en, // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
98 dqs_toggle, // enable toggle DQS according to the pattern
99 dci, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
100 buf_wr, // connect to external buffer (but only if not paused)
101 buf_rd, // connect to external buffer (but only if not paused)
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