x393  1.0
FPGAcodeforElphelNC393camera
tasks_tests_memory.vh
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1 /*!
2  * @file tasks_tests_memory.vh
3  * @date 2015-08-01
4  * @author Andrey Filippov
5  *
6  * @brief Top-level tasks for testing memory subsystem functionality
7  *
8  * @copyright Copyright (c) 2015 Elphel, Inc .
9  *
10  * <b>License:</b>
11  *
12  * tasks_tests_memory.vh is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License as published by
14  * the Free Software Foundation, either version 3 of the License, or
15  * (at your option) any later version.
16  *
17  * tasks_tests_memory.vh is distributed in the hope that it will be useful,
18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20  * GNU General Public License for more details.
21  *
22  * You should have received a copy of the GNU General Public License
23  * along with this program. If not, see <http://www.gnu.org/licenses/> .
24  *
25  * Additional permission under GNU GPL version 3 section 7:
26  * If you modify this Program, or any covered work, by linking or combining it
27  * with independent modules provided by the FPGA vendor only (this permission
28  * does not extend to any 3-rd party modules, "soft cores" or macros) under
29  * different license terms solely for the purpose of generating binary "bitstream"
30  * files and/or simulating the code, the copyright holders of this Program give
31  * you the right to distribute the covered work without those independent modules
32  * as long as the source code for them is available from the FPGA vendor free of
33  * charge, and there is no dependence on any encrypted modules for simulating of
34  * the combined code. This permission applies to you if the distributed code
35  * contains all the components and scripts required to completely simulate it
36  * with at least one of the Free Software programs.
37  */
38 
39 task test_write_levelling; // SuppressThisWarning VEditor - may be unused
40  begin
41 // Set special values for DQS idelay for write leveling
42  wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // not no interrupt running cycle - delays are changed immediately
43  axi_set_dqs_idelay_wlv;
44 // Set write buffer (from DDR3) WE signal delay for write leveling mode
45  axi_set_wbuf_delay(WBUF_DLY_WLV);
46  axi_set_dqs_odelay('h80); // 'h80 - inverted, 'h60 - not - 'h80 will cause warnings during simulation
47  schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
48  WRITELEV_OFFSET, // input [9:0] seq_addr; // sequence start address
49  0, // input [1:0] page; // buffer page number
50  0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
51  0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
52  `PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
53 
54  wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
55  read_block_buf_chn (0, 0, 32, 1 ); // chn=0, page=0, number of 32-bit words=32, wait_done
56 // @ (negedge rstb);
57  axi_set_dqs_odelay(DLY_DQS_ODELAY);
58  schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
59  WRITELEV_OFFSET, // input [9:0] seq_addr; // sequence start address
60  1, // input [1:0] page; // buffer page number
61  0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
62  0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
63  `PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
64  wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
65  read_block_buf_chn (0, 1, 32, 1 ); // chn=0, page=1, number of 32-bit words=32, wait_done
66 // task wait_read_queue_empty; - alternative way to check fo empty read queue
67 
68 // @ (negedge rstb);
69  axi_set_dqs_idelay_nominal;
70  axi_set_dqs_odelay_nominal;
71 // axi_set_dqs_odelay('h78);
72  axi_set_wbuf_delay(WBUF_DLY_DFLT); //DFLT_WBUF_DELAY
73  end
74 endtask
75 
76 task test_read_pattern; // SuppressThisWarning VEditor - may be unused
77  begin
78  schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
79  READ_PATTERN_OFFSET, // input [9:0] seq_addr; // sequence start address
80  2, // input [1:0] page; // buffer page number
81  0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
82  0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
83  `PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
84  wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
85  read_block_buf_chn (0, 2, 32, 1 ); // chn=0, page=2, number of 32-bit words=32, wait_done
86  end
87 endtask
88 
89 task test_write_block; // SuppressThisWarning VEditor - may be unused
90  begin
91 // write_block_buf_chn; // fill block memory - already set in set_up task
92  schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
93  WRITE_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
94  0, // input [1:0] page; // buffer page number
95  0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
96  1, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
97  `PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
98 // tempoary - for debugging:
99 // wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
100  end
101 endtask
102 
103 task test_read_block; // SuppressThisWarning VEditor - may be unused
104  begin
105  schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
106  READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
107  3, // input [1:0] page; // buffer page number
108  0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
109  0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
110  `PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
111  schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
112  READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
113  2, // input [1:0] page; // buffer page number
114  0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
115  0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
116  `PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
117  schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
118  READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
119  1, // input [1:0] page; // buffer page number
120  0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
121  0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
122  `PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
123  wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
124  read_block_buf_chn (0, 3, 256, 1 ); // chn=0, page=3, number of 32-bit words=256, wait_done
125  end
126 endtask
127 
128 
129 // above - move to include
130 
131 task test_afi_rw; // SuppressThisWarning VEditor - may be unused
132  input write_ddr3;
133  input [1:0] extra_pages;
134  input [21:0] frame_start_addr;
135  input [15:0] window_full_width; // 13 bit - in 8*16=128 bit bursts
136  input [15:0] window_width; // 13 bit - in 8*16=128 bit bursts
137  input [15:0] window_height; // 16 bit (only 14 are used here)
138  input [15:0] window_left;
139  input [15:0] window_top;
140  input [28:0] start64; // relative start address of the transfer (set to 0 when writing lo_addr64)
141  input [28:0] lo_addr64; // low address of the system memory range, in 64-bit words
142  input [28:0] size64; // size of the system memory range in 64-bit words
143  input continue; // 0 start from start64, 1 - continue from where it was
144  input disable_need;
145  input [4:0] cache_mode; // 'h3 - normal, 'h13 - debug
146  input rpt;
147 
148 
149 // -----------------------------------------
150  integer mode;
151 `ifdef MEMBRIDGE_DEBUG_READ
152  integer ii;
153 `endif
154  reg repetitive;
155  reg single;
156  reg reset_frame;
157  reg disable_need;
158  reg skip_too_late;
159  begin
160  skip_too_late = 1'b0;
161  disable_need = 1'b0;
162  repetitive = rpt; //1'b1;
163  single = !rpt; // 1'b0;
164  reset_frame = 1'b0;
165  $display("====== test_afi_rw: write=%d, extra_pages=%d, frame_start= %x, window_full_width=%d, window_width=%d, window_height=%d, window_left=%d, window_top=%d,@%t",
166  write_ddr3, extra_pages, frame_start_addr, window_full_width, window_width, window_height, window_left, window_top, $time);
167  $display("len64=%x, width64=%x, start64=%x, lo_addr64=%x, size64=%x,@%t",
168  ((window_width[12:0]==0)? 15'h4000 : {1'b0,window_width[12:0],1'b0})*window_height[13:0],
169  (window_width[12:0]==0)? 29'h4000 : {15'b0,window_width[12:0],1'b0},
170  start64, lo_addr64, size64, $time);
171  mode= func_encode_mode_scanline(
172  skip_too_late,
173  disable_need,
174  repetitive,
175  single,
176  reset_frame,
177  extra_pages,
178  write_ddr3, // write_mem,
179  1, // enable
180  0); // chn_reset
181  write_contol_register(MCNTRL_SCANLINE_CHN1_ADDR + MCNTRL_SCANLINE_STARTADDR, {10'b0,frame_start_addr}); // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
182  write_contol_register(MCNTRL_SCANLINE_CHN1_ADDR + MCNTRL_SCANLINE_FRAME_FULL_WIDTH, {16'h0, window_full_width});
183  write_contol_register(MCNTRL_SCANLINE_CHN1_ADDR + MCNTRL_SCANLINE_WINDOW_WH, {window_height,window_width}); //WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
184  write_contol_register(MCNTRL_SCANLINE_CHN1_ADDR + MCNTRL_SCANLINE_WINDOW_X0Y0, {window_top,window_left}); //WINDOW_X0+ (WINDOW_Y0<<16));
185  write_contol_register(MCNTRL_SCANLINE_CHN1_ADDR + MCNTRL_SCANLINE_WINDOW_STARTXY, 0);
186  write_contol_register(MCNTRL_SCANLINE_CHN1_ADDR + MCNTRL_SCANLINE_MODE, mode);
187  configure_channel_priority(1,0); // lowest priority channel 3
188  enable_memcntrl_en_dis(1,1);
189 // write_contol_register(test_mode_address, TEST01_START_FRAME);
190  afi_setup(0);
191  membridge_setup(
192  ((window_width[12:0]==0)? 15'h4000 : {1'b0,window_width[12:0],1'b0})*window_height[13:0], //len64,
193  (window_width[12:0]==0)? 29'h4000 : {15'b0,window_width[12:0],1'b0}, // width64,
194  start64,
195  lo_addr64,
196  size64,
197  cache_mode);
198  membridge_start (continue);
199 `ifdef MEMBRIDGE_DEBUG_READ
200  // debugging
201  for (ii=0; ii < 10; ii=ii +1) begin
202  #200; //#50;
203  write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_CTRL, {27'b0,continue,4'b1101}); // enable both address and data
204  end
205  #500;
206  write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_CTRL, {26'b0,continue,5'b10001}); // disable debug (enable remaining xfers)
207 `endif
208 // just wait done
209  wait_status_condition ( // may also be read directly from the same bit of mctrl_linear_rw (address=5) status
210  MEMBRIDGE_STATUS_REG, // MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
211  MEMBRIDGE_ADDR + MEMBRIDGE_STATUS_CNTRL, // MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL,
212  DEFAULT_STATUS_MODE,
213  2 << STATUS_2LSB_SHFT, // bit 24 - busy, bit 25 - frame done
214  2 << STATUS_2LSB_SHFT, // mask for the 4-bit page number
215  0, // equal to
216  1); // do synchronize sequence number
217  end
218 endtask
219 
220 task test_scanline_write; // SuppressThisWarning VEditor - may be unused
221  input [3:0] channel;
222  input [1:0] extra_pages;
223  input wait_done;
224  input [15:0] window_width; // 13 bit - in 8*16=128 bit bursts
225  input [15:0] window_height; // 16 bit
226  input [15:0] window_left;
227  input [15:0] window_top;
228 
229 
230  reg [29:0] start_addr;
231  integer mode;
232  reg [STATUS_DEPTH-1:0] status_address;
233  reg [29:0] status_control_address;
234  reg [29:0] test_mode_address;
235 
236  integer ii;
237  integer xfer_size;
238  integer pages_per_row;
239  integer startx,starty; // temporary - because of the vdt bug with integer ports
240  reg repetitive;
241  reg single;
242  reg reset_frame;
243  reg disable_need;
244  reg skip_too_late;
245  begin
246  disable_need = 1'b0;
247  repetitive = 1'b1;
248  single = 1'b0;
249  reset_frame = 1'b0;
250  skip_too_late = 1'b0;
251  pages_per_row= (window_width>>NUM_XFER_BITS)+((window_width[NUM_XFER_BITS-1:0]==0)?0:1);
252  $display("====== test_scanline_write: channel=%d, extra_pages=%d, wait_done=%d @%t",
253  channel, extra_pages, wait_done, $time);
254  case (channel)
255 // 1: begin
256 // start_addr= MCNTRL_SCANLINE_CHN1_ADDR;
257 // status_address= MCNTRL_TEST01_STATUS_REG_CHN1_ADDR;
258 // status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN1_STATUS_CNTRL;
259 // test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN1_MODE;
260 // end
261  3: begin
262  start_addr= MCNTRL_SCANLINE_CHN3_ADDR;
263  status_address= MCNTRL_TEST01_STATUS_REG_CHN3_ADDR;
264  status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL;
265  test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE;
266  end
267  default: begin
268  $display("**** ERROR: Invalid channel, only 3 is valid");
269  start_addr= MCNTRL_SCANLINE_CHN3_ADDR;
270  status_address= MCNTRL_TEST01_STATUS_REG_CHN1_ADDR;
271  status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN1_STATUS_CNTRL;
272  test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN1_MODE;
273  end
274  endcase
275  mode= func_encode_mode_scanline(
276  skip_too_late,
277  disable_need,
278  repetitive,
279  single,
280  reset_frame,
281  extra_pages,
282  1, // write_mem,
283  1, // enable
284  0); // chn_reset
285 
286  write_contol_register(start_addr + MCNTRL_SCANLINE_STARTADDR, FRAME_START_ADDRESS); // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
287  write_contol_register(start_addr + MCNTRL_SCANLINE_FRAME_FULL_WIDTH, FRAME_FULL_WIDTH);
288  write_contol_register(start_addr + MCNTRL_SCANLINE_WINDOW_WH, {window_height,window_width}); //WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
289  write_contol_register(start_addr + MCNTRL_SCANLINE_WINDOW_X0Y0, {window_top,window_left}); //WINDOW_X0+ (WINDOW_Y0<<16));
290  write_contol_register(start_addr + MCNTRL_SCANLINE_WINDOW_STARTXY, SCANLINE_STARTX+(SCANLINE_STARTY<<16));
291  write_contol_register(start_addr + MCNTRL_SCANLINE_MODE, mode);
292  configure_channel_priority(channel,0); // lowest priority channel 3
293 // enable_memcntrl_channels(16'h000b); // channels 0,1,3 are enabled
294  enable_memcntrl_en_dis(channel,1);
295  write_contol_register(test_mode_address, TEST01_START_FRAME);
296  for (ii=0;ii<TEST_INITIAL_BURST;ii=ii+1) begin
297 // VDT bugs: 1:does not propagate undefined width through ?:, 2: - does not allow to connect it to task integer input, 3: shows integer input width as 1
298  xfer_size= ((pages_per_row>1)?
299  (
300  (
301  ((ii % pages_per_row) < (pages_per_row-1))?
302  (1<<NUM_XFER_BITS):
303  (window_width % (1<<NUM_XFER_BITS))
304  )
305  ):
306  ({16'b0,window_width}));
307  $display("########### test_scanline_write block %d: channel=%d, @%t", ii, channel, $time);
308  startx=window_left + ((ii % pages_per_row)<<NUM_XFER_BITS);
309  starty=window_top + (ii / pages_per_row);
310  write_block_scanline_chn(
311  channel,
312  (ii & 3),
313  xfer_size,
314  startx, //window_left + ((ii % pages_per_row)<<NUM_XFER_BITS), // SCANLINE_CUR_X,
315  starty); // window_top + (ii / pages_per_row)); // SCANLINE_CUR_Y);\
316 
317  end
318  for (ii=0;ii< (window_height * pages_per_row) ;ii = ii+1) begin // here assuming 1 page per line
319  if (ii >= TEST_INITIAL_BURST) begin // wait page ready and fill page after first 4 are filled
320  wait_status_condition (
321  status_address, //MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
322  status_control_address, // MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL,
323  DEFAULT_STATUS_MODE,
324  (ii-TEST_INITIAL_BURST)<<16, // 4-bit page number
325  'hf << 16, // mask for the 4-bit page number
326  1, // not equal to
327  (ii == TEST_INITIAL_BURST)); // synchronize sequence number - only first time, next just wait fro auto update
328  xfer_size= ((pages_per_row>1)?
329  (
330  (
331  ((ii % pages_per_row) < (pages_per_row-1))?
332 
333  (1<<NUM_XFER_BITS):
334  (window_width % (1<<NUM_XFER_BITS))
335  )
336  ):
337  ({16'b0,window_width}));
338  $display("########### test_scanline_write block %d: channel=%d, @%t", ii, channel, $time);
339  startx=window_left + ((ii % pages_per_row)<<NUM_XFER_BITS);
340  starty=window_top + (ii / pages_per_row);
341 
342  write_block_scanline_chn(
343  channel,
344  (ii & 3),
345  xfer_size,
346  startx, // window_left + ((ii % pages_per_row)<<NUM_XFER_BITS), // SCANLINE_CUR_X,
347  starty); // window_top + (ii / pages_per_row)); // SCANLINE_CUR_Y);
348  end
349  write_contol_register(test_mode_address, TEST01_NEXT_PAGE);
350  end
351  if (wait_done) begin
352  wait_status_condition ( // may also be read directly from the same bit of mctrl_linear_rw (address=5) status
353  status_address, // MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
354  status_control_address, // MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL,
355  DEFAULT_STATUS_MODE,
356  2 << STATUS_2LSB_SHFT, // bit 24 - busy, bit 25 - frame done
357  2 << STATUS_2LSB_SHFT, // mask for the 4-bit page number
358  0, // equal to
359  0); // no need to synchronize sequence number
360 // enable_memcntrl_en_dis(channel,0); // disable channel
361  end
362  end
363 endtask
364 
365 task test_scanline_read; // SuppressThisWarning VEditor - may be unused
366  input [3:0] channel;
367  input [1:0] extra_pages;
368  input show_data;
369  input [15:0] window_width;
370  input [15:0] window_height;
371  input [15:0] window_left;
372  input [15:0] window_top;
373 
374  reg [29:0] start_addr;
375  integer mode;
376  reg [STATUS_DEPTH-1:0] status_address;
377  reg [29:0] status_control_address;
378  reg [29:0] test_mode_address;
379  integer ii;
380  integer xfer_size;
381  integer pages_per_row;
382 
383  reg repetitive;
384  reg single;
385  reg reset_frame;
386  reg disable_need;
387  reg skip_too_late;
388  begin
389  skip_too_late = 1'b0;
390  disable_need = 1'b0;
391  repetitive = 1'b1;
392  single = 1'b0;
393  reset_frame = 1'b0;
394  pages_per_row= (window_width>>NUM_XFER_BITS)+((window_width[NUM_XFER_BITS-1:0]==0)?0:1);
395  $display("====== test_scanline_read: channel=%d, extra_pages=%d, show_data=%d @%t",
396  channel, extra_pages, show_data, $time);
397  case (channel)
398 // 1: begin
399 // start_addr= MCNTRL_SCANLINE_CHN1_ADDR;
400 // status_address= MCNTRL_TEST01_STATUS_REG_CHN1_ADDR;
401 // status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN1_STATUS_CNTRL;
402 // test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN1_MODE;
403 // end
404  3: begin
405  start_addr= MCNTRL_SCANLINE_CHN3_ADDR;
406  status_address= MCNTRL_TEST01_STATUS_REG_CHN3_ADDR;
407  status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL;
408  test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE;
409  end
410  default: begin
411  $display("**** ERROR: Invalid channel, only 3 is valid");
412  start_addr= MCNTRL_SCANLINE_CHN3_ADDR;
413  status_address= MCNTRL_TEST01_STATUS_REG_CHN1_ADDR;
414  status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN1_STATUS_CNTRL;
415  test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN1_MODE;
416  end
417  endcase
418  mode= func_encode_mode_scanline(
419  skip_too_late,
420  disable_need,
421  repetitive,
422  single,
423  reset_frame,
424  extra_pages,
425  0, // write_mem,
426  1, // enable
427  0); // chn_reset
428 
429  // program to the
430  write_contol_register(start_addr + MCNTRL_SCANLINE_STARTADDR, FRAME_START_ADDRESS); // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
431  write_contol_register(start_addr + MCNTRL_SCANLINE_FRAME_FULL_WIDTH, FRAME_FULL_WIDTH);
432  write_contol_register(start_addr + MCNTRL_SCANLINE_WINDOW_WH, {window_height,window_width}); //WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
433  write_contol_register(start_addr + MCNTRL_SCANLINE_WINDOW_X0Y0, {window_top,window_left}); //WINDOW_X0+ (WINDOW_Y0<<16));
434  write_contol_register(start_addr + MCNTRL_SCANLINE_WINDOW_STARTXY, SCANLINE_STARTX+(SCANLINE_STARTY<<16));
435  write_contol_register(start_addr + MCNTRL_SCANLINE_MODE, mode);// set mode register: {extra_pages[1:0],enable,!reset}
436  configure_channel_priority(channel,0); // lowest priority channel 3
437  enable_memcntrl_en_dis(channel,1);
438  write_contol_register(test_mode_address, TEST01_START_FRAME);
439  for (ii=0;ii<(window_height * pages_per_row);ii = ii+1) begin
440  xfer_size= ((pages_per_row>1)?
441  (
442  (
443  ((ii % pages_per_row) < (pages_per_row-1))?
444  (1<<NUM_XFER_BITS):
445  (window_width % (1<<NUM_XFER_BITS))
446  )
447  ):
448  ({16'b0,window_width}));
449  wait_status_condition (
450  status_address, //MCNTRL_TEST01_STATUS_REG_CHN2_ADDR,
451  status_control_address, // MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_STATUS_CNTRL,
452  DEFAULT_STATUS_MODE,
453  (ii) << 16, // -TEST_INITIAL_BURST)<<16, // 4-bit page number
454  'hf << 16, // mask for the 4-bit page number
455  1, // not equal to
456  (ii == 0)); // synchronize sequence number - only first time, next just wait fro auto update
457 // read block (if needed), for now just sikip
458  if (show_data) begin
459  $display("########### test_scanline_read block %d: channel=%d, @%t", ii, channel, $time);
460  read_block_buf_chn (
461  channel,
462  (ii & 3),
463  xfer_size <<2,
464  1 ); // chn=0, page=3, number of 32-bit words=256, wait_done
465  end
466  write_contol_register(test_mode_address, TEST01_NEXT_PAGE);
467  end
468  end
469 endtask
470 
471 task test_tiled_write; // SuppressThisWarning VEditor - may be unused
472  input [3:0] channel;
473  input byte32;
474  input keep_open;
475  input [1:0] extra_pages;
476  input wait_done;
477  input [15:0] window_width;
478  input [15:0] window_height;
479  input [15:0] window_left;
480  input [15:0] window_top;
481  input [ 7:0] tile_width;
482  input [ 7:0] tile_height;
483  input [ 7:0] tile_vstep;
484 
485 
486 
487  reg [29:0] start_addr;
488  integer mode;
489  reg [STATUS_DEPTH-1:0] status_address;
490  reg [29:0] status_control_address;
491  reg [29:0] test_mode_address;
492  integer ii;
493  integer tiles_per_row;
494  integer tile_rows_per_window;
495  integer tile_size;
496  integer startx,starty; // temporary - because of the vdt bug with integer ports
497  reg repetitive;
498  reg single;
499  reg reset_frame;
500  reg disable_need;
501  reg skip_too_late;
502  begin
503  disable_need = 1'b0;
504  repetitive = 1'b1;
505  single = 1'b0;
506  reset_frame = 1'b0;
507  skip_too_late = 1'b0;
508  tiles_per_row= (window_width/tile_width)+ ((window_width % tile_width==0)?0:1);
509  tile_rows_per_window= ((window_height-1)/tile_vstep) + 1;
510  tile_size= tile_width*tile_height;
511  $display("====== test_tiled_write: channel=%d, byte32=%d, keep_open=%d, extra_pages=%d, wait_done=%d @%t",
512  channel, byte32, keep_open, extra_pages, wait_done, $time);
513  case (channel)
514  2: begin
515  start_addr= MCNTRL_TILED_CHN2_ADDR;
516  status_address= MCNTRL_TEST01_STATUS_REG_CHN2_ADDR;
517  status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_STATUS_CNTRL;
518  test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_MODE;
519  end
520  4: begin
521  start_addr= MCNTRL_TILED_CHN4_ADDR;
522  status_address= MCNTRL_TEST01_STATUS_REG_CHN4_ADDR;
523  status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN4_STATUS_CNTRL;
524  test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN4_MODE;
525  end
526  default: begin
527  $display("**** ERROR: Invalid channel, only 2 and 4 are valid");
528  start_addr= MCNTRL_TILED_CHN2_ADDR;
529  status_address= MCNTRL_TEST01_STATUS_REG_CHN2_ADDR;
530  status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_STATUS_CNTRL;
531  test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_MODE;
532  end
533  endcase
534  mode= func_encode_mode_tiled(
535  skip_too_late,
536  disable_need,
537  repetitive,
538  single,
539  reset_frame,
540  byte32,
541  keep_open,
542  extra_pages,
543  1, // write_mem,
544  1, // enable
545  0); // chn_reset
546  write_contol_register(start_addr + MCNTRL_TILED_STARTADDR, FRAME_START_ADDRESS); // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
547  write_contol_register(start_addr + MCNTRL_TILED_FRAME_FULL_WIDTH, FRAME_FULL_WIDTH);
548  write_contol_register(start_addr + MCNTRL_TILED_WINDOW_WH, {window_height,window_width}); //WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
549  write_contol_register(start_addr + MCNTRL_TILED_WINDOW_X0Y0, {window_top,window_left}); //WINDOW_X0+ (WINDOW_Y0<<16));
550 
551  write_contol_register(start_addr + MCNTRL_TILED_WINDOW_STARTXY, TILED_STARTX+(TILED_STARTY<<16));
552  write_contol_register(start_addr + MCNTRL_TILED_TILE_WHS, {8'b0,tile_vstep,tile_height,tile_width});//tile_width+(tile_height<<8)+(tile_vstep<<16));
553  write_contol_register(start_addr + MCNTRL_TILED_MODE, mode);// set mode register: {extra_pages[1:0],enable,!reset}
554  configure_channel_priority(channel,0); // lowest priority channel 3
555  enable_memcntrl_en_dis(channel,1);
556  write_contol_register(test_mode_address, TEST01_START_FRAME);
557 
558  for (ii=0;ii<TEST_INITIAL_BURST;ii=ii+1) begin
559  $display("########### test_tiled_write block %d: channel=%d, @%t", ii, channel, $time);
560  startx = window_left + ((ii % tiles_per_row) * tile_width);
561  starty = window_top + (ii / tile_rows_per_window); // SCANLINE_CUR_Y);\
562  write_block_scanline_chn( // TODO: Make a different tile buffer data, matching the order
563  channel, // channel
564  (ii & 3),
565  tile_size,
566  startx, //window_left + ((ii % tiles_per_row) * tile_width),
567  starty); //window_top + (ii / tile_rows_per_window)); // SCANLINE_CUR_Y);\
568  end
569 
570  for (ii=0;ii<(tiles_per_row * tile_rows_per_window);ii = ii+1) begin
571  if (ii >= TEST_INITIAL_BURST) begin // wait page ready and fill page after first 4 are filled
572  wait_status_condition (
573  status_address, // MCNTRL_TEST01_STATUS_REG_CHN5_ADDR,
574  status_control_address, // MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN5_STATUS_CNTRL,
575  DEFAULT_STATUS_MODE,
576  (ii-TEST_INITIAL_BURST)<<16, // 4-bit page number
577  'hf << 16, // mask for the 4-bit page number
578  1, // not equal to
579  (ii == TEST_INITIAL_BURST)); // synchronize sequence number - only first time, next just wait fro auto update
580  $display("########### test_tiled_write block %d: channel=%d, @%t", ii, channel, $time);
581  startx = window_left + ((ii % tiles_per_row) * tile_width);
582  starty = window_top + (ii / tile_rows_per_window);
583  write_block_scanline_chn( // TODO: Make a different tile buffer data, matching the order
584  channel, // channel
585  (ii & 3),
586  tile_size,
587  startx, // window_left + ((ii % tiles_per_row) * tile_width),
588  starty); // window_top + (ii / tile_rows_per_window)); // SCANLINE_CUR_Y);\
589  end
590  write_contol_register(test_mode_address, TEST01_NEXT_PAGE);
591  end
592  if (wait_done) begin
593  wait_status_condition ( // may also be read directly from the same bit of mctrl_linear_rw (address=5) status
594  status_address, // MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
595  status_control_address, // MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL,
596  DEFAULT_STATUS_MODE,
597  2 << STATUS_2LSB_SHFT, // bit 24 - busy, bit 25 - frame done
598  2 << STATUS_2LSB_SHFT, // mask for the 4-bit page number
599  0, // equal to
600  0); // no need to synchronize sequence number
601 // enable_memcntrl_en_dis(channel,0); // disable channel
602  end
603  end
604 endtask
605 
606 task test_tiled_read; // SuppressThisWarning VEditor - may be unused
607  input [3:0] channel;
608  input byte32;
609  input keep_open;
610  input [1:0] extra_pages;
611  input show_data;
612  input [15:0] window_width;
613  input [15:0] window_height;
614  input [15:0] window_left;
615  input [15:0] window_top;
616  input [ 7:0] tile_width;
617  input [ 7:0] tile_height;
618  input [ 7:0] tile_vstep;
619 
620  reg [29:0] start_addr;
621  integer mode;
622  reg [STATUS_DEPTH-1:0] status_address;
623  reg [29:0] status_control_address;
624  reg [29:0] test_mode_address;
625 
626  integer ii;
627  integer tiles_per_row;
628  integer tile_rows_per_window;
629  integer tile_size;
630 
631  reg repetitive;
632  reg single;
633  reg reset_frame;
634  reg disable_need;
635  reg skip_too_late;
636  begin
637  skip_too_late = 1'b0;
638  disable_need = 1'b0;
639  repetitive = 1'b1;
640  single = 1'b0;
641  reset_frame = 1'b0;
642 
643  tiles_per_row= (window_width/tile_width)+ ((window_width % tile_width==0)?0:1);
644  tile_rows_per_window= ((window_height-1)/tile_vstep) + 1;
645  tile_size= tile_width*tile_height;
646  $display("====== test_tiled_read: channel=%d, byte32=%d, keep_open=%d, extra_pages=%d, show_data=%d @%t",
647  channel, byte32, keep_open, extra_pages, show_data, $time);
648  case (channel)
649  2: begin
650  start_addr= MCNTRL_TILED_CHN2_ADDR;
651  status_address= MCNTRL_TEST01_STATUS_REG_CHN2_ADDR;
652  status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_STATUS_CNTRL;
653  test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_MODE;
654  end
655  4: begin
656  start_addr= MCNTRL_TILED_CHN4_ADDR;
657  status_address= MCNTRL_TEST01_STATUS_REG_CHN4_ADDR;
658  status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN4_STATUS_CNTRL;
659  test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN4_MODE;
660  end
661  default: begin
662  $display("**** ERROR: Invalid channel, only 2 and 4 are valid");
663  start_addr= MCNTRL_TILED_CHN2_ADDR;
664  status_address= MCNTRL_TEST01_STATUS_REG_CHN2_ADDR;
665  status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_STATUS_CNTRL;
666  test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_MODE;
667  end
668  endcase
669  mode= func_encode_mode_tiled(
670  skip_too_late,
671  disable_need,
672  repetitive,
673  single,
674  reset_frame,
675  byte32,
676  keep_open,
677  extra_pages,
678  0, // write_mem,
679  1, // enable
680  0); // chn_reset
681  write_contol_register(start_addr + MCNTRL_TILED_STARTADDR, FRAME_START_ADDRESS); // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
682  write_contol_register(start_addr + MCNTRL_TILED_FRAME_FULL_WIDTH, FRAME_FULL_WIDTH);
683  write_contol_register(start_addr + MCNTRL_TILED_WINDOW_WH, {window_height,window_width}); //WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
684  write_contol_register(start_addr + MCNTRL_TILED_WINDOW_X0Y0, {window_top,window_left}); //WINDOW_X0+ (WINDOW_Y0<<16));
685 
686  write_contol_register(start_addr + MCNTRL_TILED_WINDOW_STARTXY, TILED_STARTX+(TILED_STARTY<<16));
687  write_contol_register(start_addr + MCNTRL_TILED_TILE_WHS, {8'b0,tile_vstep,tile_height,tile_width});//(tile_height<<8)+(tile_vstep<<16));
688  write_contol_register(start_addr + MCNTRL_TILED_MODE, mode);// set mode register: {extra_pages[1:0],enable,!reset}
689  configure_channel_priority(channel,0); // lowest priority channel 3
690  enable_memcntrl_en_dis(channel,1);
691  write_contol_register(test_mode_address, TEST01_START_FRAME);
692  for (ii=0;ii<(tiles_per_row * tile_rows_per_window);ii = ii+1) begin
693  wait_status_condition (
694  status_address, // MCNTRL_TEST01_STATUS_REG_CHN4_ADDR,
695  status_control_address, // MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN4_STATUS_CNTRL,
696  DEFAULT_STATUS_MODE,
697  ii << 16, // -TEST_INITIAL_BURST)<<16, // 4-bit page number
698  'hf << 16, // mask for the 4-bit page number
699  1, // not equal to
700  (ii == 0)); // synchronize sequence number - only first time, next just wait fro auto update
701  if (show_data) begin
702  $display("########### test_tiled_read block %d: channel=%d, @%t", ii, channel, $time);
703  read_block_buf_chn (
704  channel,
705  (ii & 3),
706  tile_size <<2,
707  1 ); // chn=0, page=3, number of 32-bit words=256, wait_done
708  end
709  write_contol_register(test_mode_address, TEST01_NEXT_PAGE);
710  end
711 // enable_memcntrl_en_dis(channel,0); // disable channel
712  end
713 endtask
714 
715 
716 
717