2 * @file x393_parameters.vh
4 * @author Andrey Filippov
6 * @brief Parameters for the x393 (simulation and implementation)
8 * @copyright Copyright (c) 2015 Elphel, Inc.
12 * x393_parameters.vh is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation, either version 3 of the License, or
15 * (at your option) any later version.
17 * x393_parameters.vh is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program. If not, see <http://www.gnu.org/licenses/> .
25 * Additional permission under GNU GPL version 3 section 7:
26 * If you modify this Program, or any covered work, by linking or combining it
27 * with independent modules provided by the FPGA vendor only (this permission
28 * does not extend to any 3-rd party modules, "soft cores" or macros) under
29 * different license terms solely for the purpose of generating binary "bitstream"
30 * files and/or simulating the code, the copyright holders of this Program give
31 * you the right to distribute the covered work without those independent modules
32 * as long as the source code for them is available from the FPGA vendor free of
33 * charge, and there is no dependence on any encrypted modules for simulating of
34 * the combined code. This permission applies to you if the distributed code
35 * contains all the components and scripts required to completely simulate it
36 * with at least one of the Free Software programs.
38 parameter MCONTR_WR_MASK = 'h3c00, // AXI write address mask for the 1Kx32 buffers command sequence memory
39 parameter MCONTR_RD_MASK = 'h3c00, // AXI read address mask to generate busy
41 parameter CONTROL_ADDR = 'h0000, // AXI write address of control write registers
42 parameter CONTROL_ADDR_MASK = 'h3800, // AXI write mask of control registers
43 parameter CONTROL_RBACK_ADDR = 'h0000, // AXI read address of control registers readback
44 parameter CONTROL_RBACK_ADDR_MASK = 'h3800, // AXI mask of control registers readback addresses
45 parameter CONTROL_RBACK_DEPTH= 11, // 10 - 1xbram, 11 - 2xbram
48 parameter STATUS_ADDR = 'h0800, // AXI read address of status read registers
49 parameter STATUS_ADDR_MASK = 'h3c00, // AXI write address of status registers
51 parameter MCONTR_CMD_WR_ADDR = 'h0c00, // AXI write to command sequence memory
53 parameter MCONTR_BUF0_RD_ADDR = 'h1000, // AXI read address from buffer 0 (PS sequence, memory read) (was 'h400)
54 parameter MCONTR_BUF0_WR_ADDR = 'h1000, // AXI write address to buffer 0 (PS sequence, memory write) (was 'h400)
55 // MCONTR_BUF[2-4]_* - temporary, will be removed in the futire
56 parameter MCONTR_BUF2_RD_ADDR = 'h1400, // AXI read address from buffer 2 (PL sequence, tiles, memory read)
57 parameter MCONTR_BUF2_WR_ADDR = 'h1400, // AXI write address to buffer 2 (PL sequence, tiles, memory write)
58 parameter MCONTR_BUF3_RD_ADDR = 'h1800, // AXI read address from buffer 3 (PL sequence, scanline, memory read)
59 parameter MCONTR_BUF3_WR_ADDR = 'h1800, // AXI write address to buffer 3 (PL sequence, scanline, memory write)
60 parameter MCONTR_BUF4_RD_ADDR = 'h1c00, // AXI read address from buffer 4 (PL sequence, tiles, memory read)
61 parameter MCONTR_BUF4_WR_ADDR = 'h1c00, // AXI write address to buffer 4 (PL sequence, tiles, memory write)
64 parameter AXI_WR_ADDR_BITS = 14,
65 parameter AXI_RD_ADDR_BITS = 14,
66 parameter STATUS_DEPTH= 8, // 256 cells, maybe just 16..64 are enough?
68 //command interface parameters
69 parameter DLY_LD = 'h080, // address to generate delay load
70 parameter DLY_LD_MASK = 'h780, // address mask to generate delay load
71 //0x1000..103f - 0- bit data (set/reset)
72 parameter MCONTR_PHY_0BIT_ADDR = 'h020, // address to set sequnecer channel and run (4 LSB-s - channel)
73 parameter MCONTR_PHY_0BIT_ADDR_MASK = 'h7f0, // address mask to generate sequencer channel/run
74 // 0x1020 - DLY_SET // 0 bits -set pre-programmed delays
75 // 0x1024..1025 - CMDA_EN // 0 bits - enable/disable command/address outputs
76 // 0x1026..1027 - SDRST_ACT // 0 bits - enable/disable active-low reset signal to DDR3 memory
77 // 0x1028..1029 - CKE_EN // 0 bits - enable/disable CKE signal to memory
78 // 0x102a..102b - DCI_RST // 0 bits - enable/disable CKE signal to memory
79 // 0x102c..102d - DLY_RST // 0 bits - enable/disable CKE signal to memory
80 parameter MCONTR_PHY_0BIT_DLY_SET = 'h0, // set pre-programmed delays
81 parameter MCONTR_PHY_0BIT_CMDA_EN = 'h4, // enable/disable command/address outputs
82 parameter MCONTR_PHY_0BIT_SDRST_ACT = 'h6, // enable/disable active-low reset signal to DDR3 memory
83 parameter MCONTR_PHY_0BIT_CKE_EN = 'h8, // enable/disable CKE signal to memory
84 parameter MCONTR_PHY_0BIT_DCI_RST = 'ha, // enable/disable CKE signal to memory
85 parameter MCONTR_PHY_0BIT_DLY_RST = 'hc, // enable/disable CKE signal to memory
86 //0x1030..1037 - 0-bit memory cotroller (set/reset)
87 parameter MCONTR_TOP_0BIT_ADDR = 'h030, // address to turn on/off memory controller features
88 parameter MCONTR_TOP_0BIT_ADDR_MASK = 'h7f8, // address mask to generate sequencer channel/run
89 // 0x1030..1031 - MCONTR_EN // 0 bits, disable/enable memory controller
90 // 0x1032..1033 - REFRESH_EN // 0 bits, disable/enable memory refresh
91 // 0x1034..1037 - reserved
92 parameter MCONTR_TOP_0BIT_MCONTR_EN = 'h0, // disable/enable memory controller
93 parameter MCONTR_TOP_0BIT_REFRESH_EN = 'h2, // disable/enable command/address outputs
94 //0x1040..107f - 16-bit data
95 // 0x1040..104f - RUN_CHN // address to set sequncer channel and run (4 LSB-s - channel) - bits?
96 // parameter RUN_CHN_REL = 'h040, // address to set sequnecer channel and run (4 LSB-s - channel)
97 // parameter RUN_CHN_REL_MASK = 'h7f0, // address mask to generate sequencer channel/run
98 // 0x1050..1057: MCONTR_PHY16
99 parameter MCONTR_PHY_16BIT_ADDR = 'h050, // address to set sequnecer channel and run (4 LSB-s - channel)
100 parameter MCONTR_PHY_16BIT_ADDR_MASK = 'h7f8, // address mask to generate sequencer channel/run
101 // 0x1050 - PATTERNS // 16 bits
102 // 0x1051 - PATTERNS_TRI // 16-bit address to set DQM and DQS tristate on/off patterns {dqs_off,dqs_on, dq_off,dq_on} - 4 bits each
103 // 0x1052 - WBUF_DELAY // 4 bits - extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
104 // 0x1053 - EXTRA_REL // 1 bit - set extra parameters (currently just inv_clk_div)
105 // 0x1054 - STATUS_CNTRL // 8 bits - write to status control
106 parameter MCONTR_PHY_16BIT_PATTERNS = 'h0, // set DQM and DQS patterns (16'h0055)
107 parameter MCONTR_PHY_16BIT_PATTERNS_TRI = 'h1, // 16-bit address to set DQM and DQS tristate on/off patterns {dqs_off,dqs_on, dq_off,dq_on} - 4 bits each
108 parameter MCONTR_PHY_16BIT_WBUF_DELAY = 'h2, // 4? bits - extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
109 parameter MCONTR_PHY_16BIT_EXTRA = 'h3, // ? bits - set extra parameters (currently just inv_clk_div)
110 parameter MCONTR_PHY_STATUS_CNTRL = 'h4, // write to status control (8-bit)
112 //0x1060..106f: arbiter priority data
113 parameter MCONTR_ARBIT_ADDR = 'h060, // Address to set channel priorities
114 parameter MCONTR_ARBIT_ADDR_MASK = 'h7f0, // Address mask to set channel priorities
115 //0x1070..1077 - 16-bit top memory controller:
116 parameter MCONTR_TOP_16BIT_ADDR = 'h070, // address to set mcontr top control registers
117 parameter MCONTR_TOP_16BIT_ADDR_MASK = 'h7f8, // address mask to set mcontr top control registers
118 // 0x1070 - MCONTR_CHN_EN // 16 bits per-channel enable (want/need requests)
119 // 0x1071 - REFRESH_PERIOD // 8-bit refresh period
120 // 0x1072 - REFRESH_ADDRESS // 10 bits
121 // 0x1073 - STATUS_CNTRL // 8 bits - write to status control (and debug?)
122 parameter MCONTR_TOP_16BIT_CHN_EN = 'h0, // 16 bits per-channel enable (want/need requests)
123 parameter MCONTR_TOP_16BIT_REFRESH_PERIOD = 'h1, // 8-bit refresh period
124 parameter MCONTR_TOP_16BIT_REFRESH_ADDRESS= 'h2, // 10 bits refresh address in the sequencer (PL) memory
125 parameter MCONTR_TOP_16BIT_STATUS_CNTRL= 'h3, // 8 bits - write to status control (and debug?)
127 // Status read address
128 parameter MCONTR_PHY_STATUS_REG_ADDR= 'h0, // 8 or less bits: status register address to use for memory controller phy
129 parameter MCONTR_TOP_STATUS_REG_ADDR= 'h1, // 8 or less bits: status register address to use for memory controller
132 parameter CHNBUF_READ_LATENCY = 2, //1, // external channel buffer extra read latency ( 0 - data available next cycle after re (but prev. data))
134 parameter DFLT_DQS_PATTERN= 8'haa, // TODO: make work for the simulator too 8'h55,
135 parameter DFLT_DQM_PATTERN= 8'h00, // 8'h00
136 parameter DFLT_DQ_TRI_ON_PATTERN= 4'h7, // DQ tri-state control word, first when enabling output
137 parameter DFLT_DQ_TRI_OFF_PATTERN= 4'he, // DQ tri-state control word, first after disabling output
138 parameter DFLT_DQS_TRI_ON_PATTERN= 4'h3, // DQS tri-state control word, first when enabling output
139 parameter DFLT_DQS_TRI_OFF_PATTERN=4'hc, // DQS tri-state control word, first after disabling output
140 parameter DFLT_WBUF_DELAY= 4'h9, // TODO: Find the reason - simulation needs 8, target - 9
141 parameter DFLT_INV_CLK_DIV= 1'b0,
143 parameter DFLT_CHN_EN= 16'h0, // channel mask to be enabled at reset
144 parameter DFLT_REFRESH_ADDR= 10'h0, // refresh sequence address in command memory
145 parameter DFLT_REFRESH_PERIOD= 8'h0, // default 8-bit refresh period (scale?)
146 parameter ADDRESS_NUMBER= 15,
147 parameter COLADDR_NUMBER= 10,
148 parameter PHASE_WIDTH = 8,
149 parameter SLEW_DQ = "SLOW",
150 parameter SLEW_DQS = "SLOW",
151 parameter SLEW_CMDA = "SLOW",
152 parameter SLEW_CLK = "SLOW",
153 parameter IBUF_LOW_PWR = "TRUE",
155 parameter real REFCLK_FREQUENCY = 200.0, // 300.0,
156 parameter HIGH_PERFORMANCE_MODE = "FALSE",
157 parameter CLKIN_PERIOD = 20, // 10, //ns >1.25, 600<Fvco<1200 // Hardware 150MHz , change to | 6.667
159 parameter CLKFBOUT_MULT = `MCLK_VCO_MULT ,
161 parameter CLKFBOUT_MULT = 16, // 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 16
164 parameter real REFCLK_FREQUENCY = 300.0,
165 parameter HIGH_PERFORMANCE_MODE = "FALSE",
166 parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200
167 parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
169 parameter DIVCLK_DIVIDE= 1,
170 parameter CLKFBOUT_USE_FINE_PS= 0, //1, // 0 - old, 1 - new
171 parameter CLKFBOUT_PHASE = 0.000,
172 parameter SDCLK_PHASE = 0.000,
173 parameter CLK_PHASE = 0.000, //11.25, /// 0.000,
174 parameter CLK_DIV_PHASE = 0.000,
175 parameter MCLK_PHASE = 90.000, //78.75, // 90.000,
176 parameter REF_JITTER1 = 0.010,
177 parameter SS_EN = "FALSE",
178 parameter SS_MODE = "CENTER_HIGH",
179 parameter SS_MOD_PERIOD = 10000,
180 parameter CMD_PAUSE_BITS= 10,
181 parameter CMD_DONE_BIT= 10,
183 parameter NUM_CYCLES_LOW_BIT= 'h6, // decode addresses [NUM_CYCLES_LOW_BIT+:4] into command a/d length
184 // TODO: put actual data
185 parameter NUM_CYCLES_00 = 2, // 2-cycle 000.003f
186 parameter NUM_CYCLES_01 = 4, // 4-cycle 040.007f
187 parameter NUM_CYCLES_02 = 3, // 3-cycle 080.00bf
188 parameter NUM_CYCLES_03 = 3, // 3-cycle 0c0.00ff
189 parameter NUM_CYCLES_04 = 6, // 6-cycle 100.013f
190 parameter NUM_CYCLES_05 = 6, // 6-cycle 140.017f
191 parameter NUM_CYCLES_06 = 4, // 4-cycle 180.01bf
192 parameter NUM_CYCLES_07 = 4, // 4-cycle 1c0.01ff
193 parameter NUM_CYCLES_08 = 6, // 6-cycle 200.023f
194 parameter NUM_CYCLES_09 = 6, //
195 parameter NUM_CYCLES_10 = 6, //
196 parameter NUM_CYCLES_11 = 6, //
197 parameter NUM_CYCLES_12 = 6, //
198 parameter NUM_CYCLES_13 = 5, // 5-cycle - not yet used
199 parameter NUM_CYCLES_14 = 6, // 6-cycle - not yet used
200 parameter NUM_CYCLES_15 = 9, // single-cycle
201 parameter NUM_CYCLES_16 = 6, //
202 parameter NUM_CYCLES_17 = 6, //
203 parameter NUM_CYCLES_18 = 6, //
204 parameter NUM_CYCLES_19 = 6, //
205 parameter NUM_CYCLES_20 = 6, //
206 parameter NUM_CYCLES_21 = 6, //
207 parameter NUM_CYCLES_22 = 6, //
208 parameter NUM_CYCLES_23 = 6, //
209 parameter NUM_CYCLES_24 = 6, //
210 parameter NUM_CYCLES_25 = 6, //
211 parameter NUM_CYCLES_26 = 6, //
212 parameter NUM_CYCLES_27 = 6, //
213 parameter NUM_CYCLES_28 = 6, //
214 parameter NUM_CYCLES_29 = 6, //
215 parameter NUM_CYCLES_30 = 6, //
216 parameter NUM_CYCLES_31 = 6, //
218 // parameter CMD0_ADDR = 'h0800, // AXI write to command sequence memory
219 // parameter CMD0_ADDR_MASK = 'h1800, // AXI read address mask for the command sequence memory
220 parameter MCNTRL_PS_ADDR= 'h100,
221 parameter MCNTRL_PS_MASK= 'h7e0, // both channels 0 and 1
222 parameter MCNTRL_PS_STATUS_REG_ADDR= 'h2,
223 parameter MCNTRL_PS_EN_RST= 'h0,
224 parameter MCNTRL_PS_CMD= 'h1,
225 parameter MCNTRL_PS_STATUS_CNTRL= 'h2,
227 parameter NUM_XFER_BITS= 6, // number of bits to specify transfer length
228 parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
229 parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height
230 parameter LAST_FRAME_BITS= 16, // number of bits in frame counter (before rolls over)
231 parameter MCNTRL_SCANLINE_CHN1_ADDR= 'h120,
232 parameter MCNTRL_SCANLINE_CHN3_ADDR= 'h130,
233 parameter MCNTRL_SCANLINE_MASK= 'h7f0, // both channels 0 and 1
234 parameter MCNTRL_SCANLINE_MODE= 'h0, // set mode register: {extra_pages[1:0],enable,!reset}
235 parameter MCNTRL_SCANLINE_STATUS_CNTRL= 'h1, // control status reporting
236 parameter MCNTRL_SCANLINE_STARTADDR= 'h2, // 22-bit frame start address (3 CA LSBs==0. BA==0)
237 parameter MCNTRL_SCANLINE_FRAME_SIZE= 'h3, // 22-bit frame start address increment (3 CA LSBs==0. BA==0)
238 parameter MCNTRL_SCANLINE_FRAME_LAST= 'h4, // 16-bit last frame number in the buffer
239 parameter MCNTRL_SCANLINE_FRAME_FULL_WIDTH= 'h5, // Padded line length (8-row increment), in 8-bursts (16 bytes)
240 parameter MCNTRL_SCANLINE_WINDOW_WH= 'h6, // low word - 13-bit window width (0->'h4000), high word - 16-bit frame height (0->'h10000)
241 parameter MCNTRL_SCANLINE_WINDOW_X0Y0= 'h7, // low word - 13-bit window left, high word - 16-bit window top
242 parameter MCNTRL_SCANLINE_WINDOW_STARTXY= 'h8, // low word - 13-bit start X (relative to window), high word - 16-bit start y
243 // Start XY can be used when read command to start from the middle
244 // TODO: Add number of blocks to R/W? (blocks can be different) - total length?
245 // Read back current address (for debugging)?
246 parameter MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR= 'h4,
247 parameter MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR= 'h6,
248 parameter MCNTRL_SCANLINE_PENDING_CNTR_BITS= 2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase
249 // if memory controller will allow programming several sequences in advance to
250 // spread long-programming (tiled) over fast-programming (linear) requests.
251 // But that should not be too big to maintain 2-level priorities
253 parameter MCNTRL_SCANLINE_FRAME_PAGE_RESET =1'b0, // reset internal page number to zero at the frame start (false - only when hard/soft reset)
254 parameter MAX_TILE_WIDTH= 6, // number of bits to specify maximal tile (width-1) (6 -> 64)
255 parameter MAX_TILE_HEIGHT= 6, // number of bits to specify maximal tile (height-1) (6 -> 64)
256 parameter MCNTRL_TILED_CHN2_ADDR= 'h140,
257 parameter MCNTRL_TILED_CHN4_ADDR= 'h150,
258 parameter MCNTRL_TILED_MASK= 'h7f0, // both channels 0 and 1
259 parameter MCNTRL_TILED_MODE= 'h0, // set mode register: {extra_pages[1:0],write_mode,enable,!reset}
260 parameter MCNTRL_TILED_STATUS_CNTRL= 'h1, // control status reporting
261 parameter MCNTRL_TILED_STARTADDR= 'h2, // 22-bit frame start address (3 CA LSBs==0. BA==0)
262 parameter MCNTRL_TILED_FRAME_SIZE= 'h3, // 22-bit frame start address increment (3 CA LSBs==0. BA==0)
263 parameter MCNTRL_TILED_FRAME_LAST= 'h4, // 16-bit last frame number in the buffer
264 parameter MCNTRL_TILED_FRAME_FULL_WIDTH='h5, // Padded line length (8-row increment), in 8-bursts (16 bytes)
265 parameter MCNTRL_TILED_WINDOW_WH= 'h6, // low word - 13-bit window width (0->'h4000), high word - 16-bit frame height (0->'h10000)
266 parameter MCNTRL_TILED_WINDOW_X0Y0= 'h7, // low word - 13-bit window left, high word - 16-bit window top
267 parameter MCNTRL_TILED_WINDOW_STARTXY= 'h8, // low word - 13-bit start X (relative to window), high word - 16-bit start y
268 // Start XY can be used when read command to start from the middle
269 // TODO: Add number of blocks to R/W? (blocks can be different) - total length?
270 // Read back current address (for debugging)?
271 parameter MCNTRL_TILED_TILE_WHS= 'h9, // low byte - 6-bit tile width in 8-bursts, second byte - tile height (0 - > 64),
272 // 3-rd byte - vertical step (to control tile vertical overlap)
273 parameter MCNTRL_TILED_STATUS_REG_CHN2_ADDR= 'h5,
274 parameter MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h7,
275 parameter MCNTRL_TILED_PENDING_CNTR_BITS=2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase
276 // if memory controller will allow programming several sequences in advance to
277 // spread long-programming (tiled) over fast-programming (linear) requests.
278 // But that should not be too big to maintain 2-level priorities
279 parameter MCNTRL_TILED_FRAME_PAGE_RESET =1'b0, // reset internal page number to zero at the frame start (false - only when hard/soft reset)
280 parameter BUFFER_DEPTH32= 10, // Block RAM buffer depth on a 32-bit port
282 // bits in mode control word
283 parameter MCONTR_LINTILE_NRESET = 0, // reset if 0
284 parameter MCONTR_LINTILE_EN = 1, // enable requests
285 parameter MCONTR_LINTILE_WRITE = 2, // write to memory mode
286 parameter MCONTR_LINTILE_EXTRAPG = 3, // extra pages (over 1) needed by the client simultaneously
287 parameter MCONTR_LINTILE_EXTRAPG_BITS = 2, // number of bits to use for extra pages
288 parameter MCONTR_LINTILE_KEEP_OPEN = 5, // keep banks open (will be used only if number of rows <= 8)
289 parameter MCONTR_LINTILE_BYTE32 = 6, // use 32-byte wide columns in each tile (false - 16-byte)
290 parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
291 parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
292 parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
293 parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request
294 parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers
296 // Channel test module parameters
297 parameter MCNTRL_TEST01_ADDR= 'h0f0,
298 parameter MCNTRL_TEST01_MASK= 'h7f0,
299 parameter MCNTRL_TEST01_CHN1_MODE= 'h2, // set mode register for channel 5
300 parameter MCNTRL_TEST01_CHN1_STATUS_CNTRL= 'h3, // control status reporting for channel 5
301 parameter MCNTRL_TEST01_CHN2_MODE= 'h4, // set mode register for channel 2
302 parameter MCNTRL_TEST01_CHN2_STATUS_CNTRL= 'h5, // control status reporting for channel 2
303 parameter MCNTRL_TEST01_CHN3_MODE= 'h6, // set mode register for channel 3
304 parameter MCNTRL_TEST01_CHN3_STATUS_CNTRL= 'h7, // control status reporting for channel 3
305 parameter MCNTRL_TEST01_CHN4_MODE= 'h8, // set mode register for channel 4
306 parameter MCNTRL_TEST01_CHN4_STATUS_CNTRL= 'h9, // control status reporting for channel 4
307 parameter MCNTRL_TEST01_STATUS_REG_CHN1_ADDR= 'h3c, // status/readback register for channel 2
308 parameter MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3d, // status/readback register for channel 3
309 parameter MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3e, // status/readback register for channel 4
310 parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3f, // status/readback register for channel 4
312 parameter MCONTR_SENS_BASE = 'h680, // .. 'h6bf
313 parameter MCONTR_SENS_INC = 'h10,
314 parameter MCONTR_CMPRS_BASE = 'h6c0, // .. 'h6ff
315 parameter MCONTR_CMPRS_INC = 'h10,
316 parameter MCONTR_SENS_STATUS_BASE = 'h28, // .. 'h2b
317 parameter MCONTR_SENS_STATUS_INC = 'h1,
318 parameter MCONTR_CMPRS_STATUS_BASE = 'h2c, // .. 'h2f
319 parameter MCONTR_CMPRS_STATUS_INC = 'h1,
321 // membridge module parameters
322 parameter MEMBRIDGE_ADDR= 'h200,
323 parameter MEMBRIDGE_MASK= 'h7f0,
324 parameter MEMBRIDGE_CTRL= 'h0, // bit 0 - enable, bits[2:1]: 01 - start, 11 - start and reset address
325 parameter MEMBRIDGE_STATUS_CNTRL= 'h1,
326 parameter MEMBRIDGE_LO_ADDR64= 'h2, // low address of the system memory, in 64-bit words (<<3 to get byte address)
327 parameter MEMBRIDGE_SIZE64= 'h3, // size of the system memory range (access will roll over to lo_addr
328 parameter MEMBRIDGE_START64= 'h4, // start address relative to lo_addr
329 parameter MEMBRIDGE_LEN64= 'h5, // full length of transfer in 64-bit words
330 parameter MEMBRIDGE_WIDTH64= 'h6, // frame width in 64-bit words (partial last page in each line)
331 parameter MEMBRIDGE_MODE= 'h7, // AXI cache mode (default == 3). +0x10 - debug cache (replace data with counters)
332 parameter MEMBRIDGE_STATUS_REG= 'h3b,
334 parameter RSEL= 1'b1, // late/early READ commands (to adjust timing by 1 SDCLK period)
335 parameter WSEL= 1'b0, // late/early WRITE commands (to adjust timing by 1 SDCLK period)
337 parameter SENSOR_GROUP_ADDR = 'h400, // sensor registers base address
338 parameter SENSOR_BASE_INC = 'h040, // increment for sesor channel
340 parameter HIST_SAXI_ADDR_REL = 'h100, // histograms control addresses (16 locations) relative to SENSOR_GROUP_ADDR
341 parameter HIST_SAXI_MODE_ADDR_REL = 'h110, // histograms mode address (1 locations) relative to SENSOR_GROUP_ADDR
344 parameter SENSI2C_STATUS_REG_BASE = 'h20, // 4 locations" x20, x22, x24, x26
345 parameter SENSI2C_STATUS_REG_INC = 2, // increment to the next sensor
346 parameter SENSI2C_STATUS_REG_REL = 0, // 4 locations" 'h20, 'h22, 'h24, 'h26
347 parameter SENSIO_STATUS_REG_REL = 1, // 4 locations" 'h21, 'h23, 'h25, 'h27
348 parameter SENSOR_NUM_HISTOGRAM= 1, //was 3 trying just one histogram (see utilization) 3, // number of histogram channels
349 parameter HISTOGRAM_RAM_MODE = "BUF32", // "NOBUF", // valid: "NOBUF" (32-bits, no buffering), "BUF18", "BUF32"
350 parameter SENS_NUM_SUBCHN = 3, // number of subchannels for his sensor ports (1..4)
351 parameter SENS_GAMMA_BUFFER = 0, // 1 - use "shadow" table for clean switching, 0 - single table per channel
353 // parameters defining address map
354 parameter SENSOR_CTRL_RADDR = 0, // relative to SENSOR_GROUP_ADDR
355 parameter SENSOR_CTRL_ADDR_MASK = 'h7ff, //
356 // bits of the SENSOR mode register
357 parameter SENSOR_MODE_WIDTH = 10,
358 parameter SENSOR_HIST_EN_BITS = 0, // 0..3 1 - enable histogram modules, disable after processing the started frame
359 parameter SENSOR_HIST_NRST_BITS = 4, // 0 - immediately reset all histogram modules
360 parameter SENSOR_CHN_EN_BIT = 8, // 1 - this enable channel
361 parameter SENSOR_16BIT_BIT = 9, // 0 - 8 bpp mode, 1 - 16 bpp (bypass gamma). Gamma-processed data is still used for histograms
363 parameter SENSI2C_CTRL_RADDR = 2, // 302..'h303
364 parameter SENSI2C_CTRL_MASK = 'h7fe,
365 // sensor_i2c_io relative control register addresses
366 parameter SENSI2C_CTRL = 'h0,
367 // Control register bits
368 parameter SENSI2C_CMD_TABLE = 29, // [29]: 1 - write to translation table (ignore any other fields), 0 - write other fields
369 parameter SENSI2C_CMD_TAND = 28, // [28]: 1 - write table address (8 bits), 0 - write table data (28 bits)
371 parameter SENSI2C_CMD_RESET = 14, // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
372 parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
373 parameter SENSI2C_CMD_RUN_PBITS = 1,
375 parameter SENSI2C_CMD_SOFT_SDA = 6, // [7:6] - SDA software control: 0 - nop, 1 - low, 2 - active high, 3 - float
376 parameter SENSI2C_CMD_SOFT_SCL = 4, // [5:4] - SCL software control: 0 - nop, 1 - low, 2 - active high, 3 - float
378 parameter SENSI2C_CMD_FIFO_RD = 3, // advance I2C read data FIFO by 1
379 parameter SENSI2C_CMD_ACIVE = 2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA
380 parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1
381 parameter SENSI2C_CMD_ACIVE_SDA = 0, // drive SDA=1 during the second half of SCL=1
382 //i2c page table bit fields
383 parameter SENSI2C_TBL_RAH = 0, // high byte of the register address
384 parameter SENSI2C_TBL_RAH_BITS = 8,
385 parameter SENSI2C_TBL_RNWREG = 8, // read register (when 0 - write register
386 parameter SENSI2C_TBL_SA = 9, // Slave address in write mode
387 parameter SENSI2C_TBL_SA_BITS = 7,
388 parameter SENSI2C_TBL_NBWR = 16, // number of bytes to write (1..10)
389 parameter SENSI2C_TBL_NBWR_BITS = 4,
390 parameter SENSI2C_TBL_NBRD = 16, // number of bytes to read (1 - 8) "0" means "8"
391 parameter SENSI2C_TBL_NBRD_BITS = 3,
392 parameter SENSI2C_TBL_NABRD = 19, // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
393 parameter SENSI2C_TBL_DLY = 20, // bit delay (number of mclk periods in 1/4 of SCL period)
394 parameter SENSI2C_TBL_DLY_BITS= 8,
397 parameter SENSI2C_STATUS = 'h1,
399 parameter SENS_SYNC_RADDR = 'h4,
400 parameter SENS_SYNC_MASK = 'h7fc,
401 // 2 locations reserved for control/status (if they will be needed)
402 parameter SENS_SYNC_MULT = 'h2, // relative register address to write number of frames to combine in one (minus 1, '0' - each farme)
403 parameter SENS_SYNC_LATE = 'h3, // number of lines to delay late frame sync
407 parameter SENS_GAMMA_RADDR = 'h38, // 'h38..'h3b was 4,
408 parameter SENS_GAMMA_ADDR_MASK = 'h7fc,
409 // sens_gamma registers
410 parameter SENS_GAMMA_CTRL = 'h0,
411 parameter SENS_GAMMA_ADDR_DATA = 'h1, // bit 20 ==1 - table address, bit 20==0 - table data (18 bits)
412 parameter SENS_GAMMA_HEIGHT01 = 'h2, // bits [15:0] - height minus 1 of image 0, [31:16] - height-1 of image1
413 parameter SENS_GAMMA_HEIGHT2 = 'h3, // bits [15:0] - height minus 1 of image 2 ( no need for image 3)
414 // bits of the SENS_GAMMA_CTRL mode register
415 parameter SENS_GAMMA_MODE_WIDTH = 5, // does not include trig
416 parameter SENS_GAMMA_MODE_BAYER = 0,
417 parameter SENS_GAMMA_MODE_PAGE = 2,
418 parameter SENS_GAMMA_MODE_EN = 3,
419 parameter SENS_GAMMA_MODE_REPET = 4,
420 parameter SENS_GAMMA_MODE_TRIG = 5,
422 // Vignetting correction / pixel value scaling - controlled via single data word (same as in 252), some of bits [23:16]
423 // are used to select register, bits 25:24 - select sub-frame
424 parameter SENS_LENS_RADDR = 'h3c,
425 parameter SENS_LENS_ADDR_MASK = 'h7fc,
426 parameter SENS_LENS_COEFF = 'h3, // set vignetting/scale coefficients (
427 parameter SENS_LENS_AX = 'h00, // 00000...
428 parameter SENS_LENS_AX_MASK = 'hf8,
429 parameter SENS_LENS_AY = 'h08, // 00001...
430 parameter SENS_LENS_AY_MASK = 'hf8,
431 parameter SENS_LENS_C = 'h10, // 00010...
432 parameter SENS_LENS_C_MASK = 'hf8,
433 parameter SENS_LENS_BX = 'h20, // 001.....
434 parameter SENS_LENS_BX_MASK = 'he0,
435 parameter SENS_LENS_BY = 'h40, // 010.....
436 parameter SENS_LENS_BY_MASK = 'he0,
437 parameter SENS_LENS_SCALES = 'h60, // 01100...
438 parameter SENS_LENS_SCALES_MASK = 'hf8,
439 parameter SENS_LENS_FAT0_IN = 'h68, // 01101000
440 parameter SENS_LENS_FAT0_IN_MASK = 'hff,
441 parameter SENS_LENS_FAT0_OUT = 'h69, // 01101001
442 parameter SENS_LENS_FAT0_OUT_MASK = 'hff,
443 parameter SENS_LENS_POST_SCALE = 'h6a, // 01101010
444 parameter SENS_LENS_POST_SCALE_MASK = 'hff,
446 parameter SENSIO_RADDR = 8, //'h408 .. 'h40f
447 parameter SENSIO_ADDR_MASK = 'h7f8,
448 // sens_parallel12 registers
449 parameter SENSIO_CTRL = 'h0,
450 // SENSIO_CTRL register bits
451 parameter SENS_CTRL_MRST = 0, // 1: 0
452 parameter SENS_CTRL_ARST = 2, // 3: 2
453 parameter SENS_CTRL_ARO = 4, // 5: 4
454 parameter SENS_CTRL_RST_MMCM = 6, // 7: 6
456 parameter SENS_CTRL_IGNORE_EMBED =8, // 9: 8
458 parameter SENS_CTRL_EXT_CLK = 8, // 9: 8
460 parameter SENS_CTRL_LD_DLY = 10, // 10
462 parameter SENS_CTRL_GP0= 12, // 13:12
463 parameter SENS_CTRL_GP1= 14, // 15:14
465 parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
466 parameter SENS_CTRL_QUADRANTS_WIDTH = 6,
467 parameter SENS_CTRL_QUADRANTS_EN = 20, // 17:12, enable - 20 (2 bits reserved)
469 parameter SENSIO_STATUS = 'h1,
470 parameter SENSIO_JTAG = 'h2,
471 // SENSIO_JTAG register bits
472 parameter SENS_JTAG_PGMEN = 8,
473 parameter SENS_JTAG_PROG = 6,
474 parameter SENS_JTAG_TCK = 4,
475 parameter SENS_JTAG_TMS = 2,
476 parameter SENS_JTAG_TDI = 0,
478 parameter SENSIO_WIDTH = 'h3, // 1.. 2^16, 0 - use HACT
480 parameter SENSIO_DELAYS = 'h4, // 'h4..'h7
481 // 4 of 8-bit delays per register
482 // sensor_i2c_io command/data write registers s (relative to SENSOR_GROUP_ADDR)
483 parameter SENSI2C_ABS_RADDR = 'h10, // 'h410..'h41f
484 parameter SENSI2C_REL_RADDR = 'h20, // 'h420..'h42f
485 parameter SENSI2C_ADDR_MASK = 'h7f0, // both for SENSI2C_ABS_ADDR and SENSI2C_REL_ADDR
487 // sens_hist registers (relative to SENSOR_GROUP_ADDR)
488 parameter HISTOGRAM_RADDR0 = 'h30, //
489 parameter HISTOGRAM_RADDR1 = 'h32, //
490 parameter HISTOGRAM_RADDR2 = 'h34, //
491 parameter HISTOGRAM_RADDR3 = 'h36, //
492 parameter HISTOGRAM_ADDR_MASK = 'h7fe, // for each channel
493 // sens_hist registers
494 parameter HISTOGRAM_LEFT_TOP = 'h0,
495 parameter HISTOGRAM_WIDTH_HEIGHT = 'h1, // 1.. 2^16, 0 - use HACT
497 //sensor_i2c_io other parameters
498 parameter integer SENSI2C_DRIVE= 12,
499 parameter SENSI2C_IBUF_LOW_PWR= "TRUE",
500 parameter SENSI2C_SLEW = "SLOW",
503 //sensor_fifo parameters
504 parameter SENSOR_DATA_WIDTH = 12,
505 parameter SENSOR_FIFO_2DEPTH = 4,
506 parameter [3:0] SENSOR_FIFO_DELAY = 5, // 7,
509 // other parameters for histogram_saxi module
510 parameter HIST_SAXI_ADDR_MASK = 'h7f0,
511 parameter HIST_SAXI_MODE_WIDTH = 8,
512 parameter HIST_SAXI_EN = 0,
513 parameter HIST_SAXI_NRESET = 1,
514 parameter HIST_CONFIRM_WRITE = 2, // wait write confirmation for each block
516 parameter HIST_SAXI_AWCACHE = 4, // ..7 Write 4'h3 there, cache mode (4 bits, default 4'h3)
518 parameter HIST_SAXI_MODE_ADDR_MASK = 'h7ff,
519 parameter NUM_FRAME_BITS = 4, // number of bits use for frame number
522 parameter SENS_SYNC_FBITS = 16, // number of bits in a frame counter for linescan mode
523 parameter SENS_SYNC_LBITS = 16, // number of bits in a line counter for sof_late output (limited by eof)
524 parameter SENS_SYNC_LATE_DFLT = 15, // number of lines to delay late frame sync
525 parameter SENS_SYNC_MINBITS = 8, // number of bits to enforce minimal frame period
526 parameter SENS_SYNC_MINPER = 130, // minimal frame period (in pclk/mclk?)
529 // sens_parallel12 other parameters
531 // parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?
532 parameter integer IDELAY_VALUE = 0,
533 parameter integer PXD_DRIVE = 12,
534 parameter PXD_IBUF_LOW_PWR = "TRUE",
535 parameter PXD_SLEW = "SLOW",
537 parameter real SENS_REFCLK_FREQUENCY = 300.0, // same as REFCLK_FREQUENCY
539 parameter real SENS_REFCLK_FREQUENCY = 200.0,
541 parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
544 parameter PXD_CAPACITANCE = "DONT_CARE",
545 parameter PXD_CLK_DIV = 10, // 220MHz -> 22MHz
546 parameter PXD_CLK_DIV_BITS = 4,
549 parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
550 // parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
551 parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
553 // parameters for the sensor-synchronous clock PLL
554 `define TWEAKING_IOSTANDARD
556 parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
557 parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
558 parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
559 parameter IPCLK_PHASE = 0.000,
560 parameter IPCLK2X_PHASE = 0.000,
561 `ifdef TWEAKING_IOSTANDARD
562 parameter PXD_IOSTANDARD = "LVCMOS25", // with 1.8 actually applied voltage
563 parameter SENSI2C_IOSTANDARD = "LVCMOS25", // with 1.8 actually applied voltage
564 // parameter PXD_IOSTANDARD = "LVCMOS18", // with 1.8 actually applied voltage
565 // parameter SENSI2C_IOSTANDARD = "LVCMOS18", // with 1.8 actually applied voltage
567 parameter PXD_IOSTANDARD = "LVCMOS18",
568 parameter SENSI2C_IOSTANDARD = "LVCMOS18",
572 parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
573 parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
574 parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
575 parameter IPCLK_PHASE = 0.000,
576 parameter IPCLK2X_PHASE = 0.000,
577 parameter PXD_IOSTANDARD = "LVCMOS25",
578 parameter SENSI2C_IOSTANDARD = "LVCMOS25",
582 `ifdef TWEAKING_IOSTANDARD
583 parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
584 parameter HISPI_DIFF_TERM = "TRUE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
585 // parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
586 // parameter HISPI_IOSTANDARD = "PPDS_25", // "LVDS_25", "MINI_LVDS_25", "PPDS_25", "RSDS_25"
587 parameter HISPI_IOSTANDARD = "LVDS_25", // "LVDS_25", "MINI_LVDS_25", "PPDS_25", "RSDS_25"
589 parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
590 parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
591 parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
595 // parameter BUF_IPCLK = "BUFMR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
596 // parameter BUF_IPCLK2X = "BUFMR", //G", // "BUFR",
598 parameter BUF_IPCLK_SENS0 = "BUFR", // "BUFR2", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
599 parameter BUF_IPCLK2X_SENS0 = "BUFIO", /// "BUFR", //G", // "BUFR",
601 parameter BUF_IPCLK_SENS1 = "BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
602 parameter BUF_IPCLK2X_SENS1 = "BUFG", // "BUFR",
604 parameter BUF_IPCLK_SENS2 = "BUFR", // "BUFR2", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
605 parameter BUF_IPCLK2X_SENS2 = "BUFIO", ///"BUFR", //G", // "BUFR",
607 parameter BUF_IPCLK_SENS3 = "BUFG", // "BUFR2", ///"BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
608 parameter BUF_IPCLK2X_SENS3 = "BUFG", // "BUFIO", ///"BUFG", // "BUFR",
610 parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
611 parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
612 parameter SENS_REF_JITTER2 = 0.010,
613 parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
614 parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
615 parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
618 parameter HISPI_MSB_FIRST = 0,
619 parameter HISPI_NUMLANES = 4,
621 parameter HISPI_DELAY_CLK0= "TRUE",
622 parameter HISPI_DELAY_CLK1= "TRUE",
623 parameter HISPI_DELAY_CLK2= "TRUE",
624 parameter HISPI_DELAY_CLK3= "TRUE",
625 parameter HISPI_MMCM0 = "TRUE",
626 parameter HISPI_MMCM1 = "FALSE",
627 parameter HISPI_MMCM2 = "TRUE",
628 parameter HISPI_MMCM3 = "FALSE",
629 parameter HISPI_KEEP_IRST = 5, // number of cycles to keep irst on after release of prst (small number - use 1 hot)
630 parameter HISPI_WAIT_ALL_LANES = 4'h8, // number of output pixel cycles to wait after the earliest lane
631 parameter HISPI_FIFO_DEPTH = 4,
632 parameter HISPI_FIFO_START = 7,
633 parameter HISPI_CAPACITANCE = "DONT_CARE",
634 parameter HISPI_DQS_BIAS = "TRUE",
635 parameter HISPI_IBUF_DELAY_VALUE = "0",
636 parameter HISPI_IBUF_LOW_PWR = "TRUE",
637 parameter HISPI_IFD_DELAY_VALUE = "AUTO",
638 // parameter HISPI_IOSTANDARD = "PPDS_25", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
639 // parameter HISPI_IOSTANDARD = "DIFF_HSTL_II_18", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
640 //`endif DIFF_HSTL_II_18
643 parameter CMPRS_NUM_AFI_CHN = 1, // 2, // 1 - multiplex all 4 compressors to a single AXI_HP, 2 - split between to AXI_HP
644 parameter CMPRS_GROUP_ADDR = 'h600, // total of 'h60
645 parameter CMPRS_BASE_INC = 'h10,
646 parameter CMPRS_AFIMUX_RADDR0= 'h40, // relative to CMPRS_NUM_AFI_CHN ( 16 addr)
647 parameter CMPRS_AFIMUX_RADDR1= 'h50, // relative to CMPRS_NUM_AFI_CHN ( 16 addr)
648 parameter CMPRS_AFIMUX_MASK= 'h7f0,
650 parameter CMPRS_STATUS_REG_BASE= 'h10,
651 parameter CMPRS_HIFREQ_REG_BASE= 'h14,
652 parameter CMPRS_AFIMUX_REG_ADDR0= 'h18, // Uses 4 locations
653 parameter CMPRS_AFIMUX_REG_ADDR1= 'h1c, // Uses 4 locations
655 parameter CMPRS_STATUS_REG_INC= 1,
656 parameter CMPRS_HIFREQ_REG_INC= 1,
657 parameter CMPRS_MASK= 'h7f8,
658 parameter CMPRS_CONTROL_REG= 0,
659 parameter CMPRS_STATUS_CNTRL= 1,
660 parameter CMPRS_FORMAT= 2,
661 parameter CMPRS_COLOR_SATURATION= 3,
662 parameter CMPRS_CORING_MODE= 4,
663 parameter CMPRS_INTERRUPTS= 5,
664 parameter CMPRS_TABLES= 6, // 6..7
665 parameter TABLE_QUANTIZATION_INDEX = 0,
666 parameter TABLE_CORING_INDEX = 1,
667 parameter TABLE_FOCUS_INDEX = 2,
668 parameter TABLE_HUFFMAN_INDEX = 3,
671 // Bit-fields in compressor control word
672 parameter CMPRS_CBIT_RUN = 2, // bit # to control compressor run modes
673 parameter CMPRS_CBIT_RUN_BITS = 2, // number of bits to control compressor run modes
674 parameter CMPRS_CBIT_QBANK = 6, // bit # to control quantization table page
675 parameter CMPRS_CBIT_QBANK_BITS = 3, // number of bits to control quantization table page
676 parameter CMPRS_CBIT_DCSUB = 8, // bit # to control extracting DC components bypassing DCT
677 parameter CMPRS_CBIT_DCSUB_BITS = 1, // bit # to control extracting DC components bypassing DCT
678 parameter CMPRS_CBIT_CMODE = 13, // bit # to control compressor color modes
679 parameter CMPRS_CBIT_CMODE_BITS = 4, // number of bits to control compressor color modes
680 parameter CMPRS_CBIT_FRAMES = 15, // bit # to control compressor multi/single frame buffer modes
681 parameter CMPRS_CBIT_FRAMES_BITS = 1, // number of bits to control compressor multi/single frame buffer modes
682 parameter CMPRS_CBIT_BAYER = 20, // bit # to control compressor Bayer shift mode
683 parameter CMPRS_CBIT_BAYER_BITS = 2, // number of bits to control compressor Bayer shift mode
684 parameter CMPRS_CBIT_FOCUS = 23, // bit # to control compressor focus display mode
685 parameter CMPRS_CBIT_FOCUS_BITS = 2, // number of bits to control compressor focus display mode
686 // compressor bit-fields decode
687 parameter CMPRS_CBIT_RUN_RST = 2'h0, // reset compressor, stop immediately
688 // parameter CMPRS_CBIT_RUN_DISABLE = 2'h1, // disable compression of the new frames, finish any already started
689 parameter CMPRS_CBIT_RUN_STANDALONE = 2'h2, // enable compressor, compress single frame from memory (async)
690 parameter CMPRS_CBIT_RUN_ENABLE = 2'h3, // enable compressor, enable synchronous compression mode
691 parameter CMPRS_CBIT_CMODE_JPEG18 = 4'h0, // color 4:2:0 3x3 de-bayer core
692 parameter CMPRS_CBIT_CMODE_MONO6 = 4'h1, // mono 4:2:0 (6 blocks)
693 parameter CMPRS_CBIT_CMODE_JP46 = 4'h2, // jp4, 6 blocks, original
694 parameter CMPRS_CBIT_CMODE_JP46DC = 4'h3, // jp4, 6 blocks, dc -improved
695 parameter CMPRS_CBIT_CMODE_JPEG20 = 4'h4, // color 4:2:0 5x5 de-bayer core - not implemented
696 parameter CMPRS_CBIT_CMODE_JP4 = 4'h5, // jp4, 4 blocks
697 parameter CMPRS_CBIT_CMODE_JP4DC = 4'h6, // jp4, 4 blocks, dc-improved
698 parameter CMPRS_CBIT_CMODE_JP4DIFF = 4'h7, // jp4, 4 blocks, differential
699 parameter CMPRS_CBIT_CMODE_JP4DIFFHDR = 4'h8, // jp4, 4 blocks, differential, hdr
700 parameter CMPRS_CBIT_CMODE_JP4DIFFDIV2 = 4'h9, // jp4, 4 blocks, differential, divide by 2
701 parameter CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = 4'ha, // jp4, 4 blocks, differential, hdr,divide by 2
702 parameter CMPRS_CBIT_CMODE_MONO1 = 4'hb, // mono JPEG (not yet implemented)
703 parameter CMPRS_CBIT_CMODE_MONO4 = 4'he, // mono, 4 blocks (but still not actual monochrome JPEG as the blocks are scanned in 2x2 macroblocks)
705 parameter CMPRS_CBIT_FRAMES_SINGLE = 0, //1, // use a single-frame buffer for images
707 parameter CMPRS_COLOR18 = 0, // JPEG 4:2:0 with 18x18 overlapping tiles for de-bayer
708 parameter CMPRS_COLOR20 = 1, // JPEG 4:2:0 with 18x18 overlapping tiles for de-bayer (not implemented)
709 parameter CMPRS_MONO16 = 2, // JPEG 4:2:0 with 16x16 non-overlapping tiles, color components zeroed
710 parameter CMPRS_JP4 = 3, // JP4 mode with 16x16 macroblocks
711 parameter CMPRS_JP4DIFF = 4, // JP4DIFF mode TODO: see if correct
712 parameter CMPRS_MONO8 = 7, // Regular JPEG monochrome with 8x8 macroblocks (not yet implemented)
714 parameter CMPRS_FRMT_MBCM1 = 0, // bit # of number of macroblock columns minus 1 field in format word
715 parameter CMPRS_FRMT_MBCM1_BITS = 13, // number of bits in number of macroblock columns minus 1 field in format word
716 parameter CMPRS_FRMT_MBRM1 = 13, // bit # of number of macroblock rows minus 1 field in format word
717 parameter CMPRS_FRMT_MBRM1_BITS = 13, // number of bits in number of macroblock rows minus 1 field in format word
718 parameter CMPRS_FRMT_LMARG = 26, // bit # of left margin field in format word
719 parameter CMPRS_FRMT_LMARG_BITS = 5, // number of bits in left margin field in format word
720 parameter CMPRS_CSAT_CB = 0, // bit # of number of blue scale field in color saturation word
721 parameter CMPRS_CSAT_CB_BITS = 10, // number of bits in blue scale field in color saturation word
722 parameter CMPRS_CSAT_CR = 12, // bit # of number of red scale field in color saturation word
723 parameter CMPRS_CSAT_CR_BITS = 10, // number of bits in red scale field in color saturation word
724 parameter CMPRS_CORING_BITS = 3, // number of bits in coring mode
726 parameter CMPRS_TIMEOUT_BITS= 12,
727 parameter CMPRS_TIMEOUT= 1000, // mclk cycles
729 parameter CMPRS_AFIMUX_EN= 'h0, // enables (gl;obal and per-channel)
730 parameter CMPRS_AFIMUX_RST= 'h1, // per-channel resets
731 parameter CMPRS_AFIMUX_MODE= 'h2, // per-channel select - which register to return as status
732 parameter CMPRS_AFIMUX_STATUS_CNTRL= 'h4, // .. 'h7
733 parameter CMPRS_AFIMUX_SA_LEN= 'h8, // .. 'hf
735 parameter CMPRS_AFIMUX_WIDTH = 26, // maximal for status: currently only works with 26)
736 parameter CMPRS_AFIMUX_CYCBITS = 3,
737 parameter AFI_MUX_BUF_LATENCY = 4'd2, // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used
738 // GPIO control : 'h700..'h701, status: 'h30
739 parameter integer GPIO_DRIVE = 12,
740 parameter GPIO_ADDR = 'h700, // .701
741 parameter GPIO_MASK = 'h7fe,
742 parameter GPIO_STATUS_REG_ADDR = 'h30, // address where status can be read out (10 GPIO inputs)
744 parameter GPIO_IBUF_LOW_PWR = "TRUE",
745 parameter GPIO_IOSTANDARD = "LVCMOS15", // power is 1.5V
746 parameter GPIO_SLEW = "SLOW",
748 parameter GPIO_SET_PINS = 0, // Set GPIO output state, give control for some bits to other modules
749 parameter GPIO_SET_STATUS = 1, // set status mode
750 parameter GPIO_N = 10, // number of GPIO bits to control
751 parameter GPIO_PORTEN = 24, // bit number to control port enables (up from this)
752 // Timing (rtc+camsync) parameters
753 parameter RTC_ADDR= 'h704, // 'h707
754 parameter CAMSYNC_ADDR = 'h708, // 'h70f
755 parameter RTC_STATUS_REG_ADDR = 'h31, // (1 loc) address where status can be read out (currently just sequence # and alternating bit)
756 parameter RTC_SEC_USEC_ADDR = 'h32, // ..'h33 address where seconds of the snapshot can be read (microseconds - next address)
757 parameter RTC_MASK = 'h7fc,
758 parameter CAMSYNC_MASK = 'h7f8,
759 parameter CAMSYNC_MODE = 'h0,
760 parameter CAMSYNC_TRIG_SRC = 'h1, // setup trigger source
761 parameter CAMSYNC_TRIG_DST = 'h2, // setup trigger destination line(s)
762 parameter CAMSYNC_TRIG_PERIOD = 'h3, // setup output trigger period
763 parameter CAMSYNC_TRIG_DELAY0 = 'h4, // setup input trigger delay
764 parameter CAMSYNC_TRIG_DELAY1 = 'h5, // setup input trigger delay
765 parameter CAMSYNC_TRIG_DELAY2 = 'h6, // setup input trigger delay
766 parameter CAMSYNC_TRIG_DELAY3 = 'h7, // setup input trigger delay
768 parameter CAMSYNC_EN_BIT = 'h0, // enable module (0 - reset)
769 parameter CAMSYNC_SNDEN_BIT = 'h2, // enable writing ts_snd_en
770 parameter CAMSYNC_EXTERNAL_BIT = 'h4, // enable writing ts_external (0 - local timestamp in the frame header)
771 parameter CAMSYNC_TRIGGERED_BIT = 'h6, // triggered mode ( 0- async)
772 parameter CAMSYNC_MASTER_BIT = 'h9, // select a 2-bit master channel (master delay may be used as a flash delay)
773 parameter CAMSYNC_CHN_EN_BIT = 'he, // per-channel enable timestamp generation
774 parameter CAMSYNC_PRE_MAGIC = 6'b110100,
775 parameter CAMSYNC_POST_MAGIC = 6'b001101,
777 parameter RTC_MHZ= 25, // RTC input clock in MHz (should be interger number)
778 parameter RTC_BITC_PREDIV = 5, // number of bits to generate 2 MHz pulses counting refclk
779 parameter RTC_SET_USEC= 0, // 20-bit number of microseconds
780 parameter RTC_SET_SEC= 1, // 32-bit full number of seconds (und actually update timer)
781 parameter RTC_SET_CORR= 2, // write correction 16-bit signed
782 parameter RTC_SET_STATUS= 3, // generate an output pulse to take a snapshot
783 // Command sequencers parameters
784 parameter CMDFRAMESEQ_ADDR_BASE= 'h780,
785 parameter CMDFRAMESEQ_ADDR_INC= 'h20,
786 parameter CMDFRAMESEQ_MASK= 'h7e0,
787 parameter CMDFRAMESEQ_DEPTH = 64, // 32/64/128
788 parameter CMDFRAMESEQ_ABS = 0,
789 parameter CMDFRAMESEQ_REL = 16,
790 parameter CMDFRAMESEQ_CTRL = 31,
791 parameter CMDFRAMESEQ_RST_BIT = 14,
792 parameter CMDFRAMESEQ_RUN_BIT = 13,
793 parameter CMDFRAMESEQ_IRQ_BIT = 0,
795 parameter CMDSEQMUX_ADDR = 'h702, // only status control
796 parameter CMDSEQMUX_MASK = 'h7ff,
797 parameter CMDSEQMUX_STATUS = 'h38,
799 parameter LOGGER_ADDR = 'h720, //..'h721
800 parameter LOGGER_STATUS = 'h722, // .. 'h722
801 parameter LOGGER_STATUS_REG_ADDR = 'h39, // just 1 location)
802 parameter LOGGER_MASK = 'h7fe,
803 parameter LOGGER_STATUS_MASK = 'h7ff,
805 // parameter LOGGER_PAGE_IMU = 0, // 'h00..'h1f - overlaps with period/duration/halfperiod/config? (was so in x353)
806 parameter LOGGER_PAGE_GPS = 1, // 'h20..'h3f
807 parameter LOGGER_PAGE_MSG = 2, // 'h40..'h5f
808 parameter LOGGER_PAGE_IMU = 3, // 'h60..'h7f - removing overlap with period/duration/halfperiod/config
810 parameter LOGGER_PERIOD = 0,
811 parameter LOGGER_BIT_DURATION = 1,
812 parameter LOGGER_BIT_HALF_PERIOD = 2, //rs232 half bit period
813 parameter LOGGER_CONFIG = 3,
815 parameter LOGGER_CONF_IMU = 2,
816 parameter LOGGER_CONF_IMU_BITS = 2,
817 parameter LOGGER_CONF_GPS = 7,
818 parameter LOGGER_CONF_GPS_BITS = 4,
819 parameter LOGGER_CONF_MSG = 13,
820 parameter LOGGER_CONF_MSG_BITS = 5,
821 parameter LOGGER_CONF_SYN = 18, // 15,
822 parameter LOGGER_CONF_SYN_BITS = 4, // 1,
823 parameter LOGGER_CONF_EN = 20, // 17,
824 parameter LOGGER_CONF_EN_BITS = 1,
825 parameter LOGGER_CONF_DBG = 25, // 22,
826 parameter LOGGER_CONF_DBG_BITS = 4,
828 parameter MULT_SAXI_HALF_BRAM_IN = 1, // 0 - use full 36Kb BRAM for the buffer, 1 - use just half
829 parameter MULT_SAXI_WLOG = 4, // number of bits for the input data ( 3 - 8 bit, 4 - 16-bit, 5 - 32-bit
831 parameter MULT_SAXI_ADDR = 'h730, // ..'h737
832 parameter MULT_SAXI_CNTRL_ADDR = 'h738, // ..'h739
833 parameter MULT_SAXI_STATUS_REG = 'h34, //..'h37 uses 4 consecutive locations
834 parameter MULT_SAXI_HALF_BRAM = 1, // 0 - use full 36Kb BRAM for the buffer, 1 - use just half
835 parameter MULT_SAXI_BSLOG0 = 4, // number of bits to represent burst size (4 - b.s. = 16, 0 - b.s = 1)
836 parameter MULT_SAXI_BSLOG1 = 4,
837 parameter MULT_SAXI_BSLOG2 = 4,
838 parameter MULT_SAXI_BSLOG3 = 4,
839 parameter MULT_SAXI_MASK = 'h7f8, // 4 address/length pairs. In bytes, but lower bits are set to 0?
840 parameter MULT_SAXI_CNTRL_MASK = 'h7fe, // mode and status - 2 locations
841 parameter MULT_SAXI_AWCACHE = 4'h3, //..7 cache mode (4 bits, default 4'h3)
842 parameter MULT_SAXI_ADV_WR = 4, // number of clock cycles before end of write to genearte adv_wr_done
843 parameter MULT_SAXI_ADV_RD = 3, // number of clock cycles before end of write to genearte adv_wr_done
845 // Clock management (input, generation, buffering)
846 parameter CLK_ADDR = 'h728, // ..'h729
847 parameter CLK_MASK = 'h7fe, //
848 parameter CLK_STATUS_REG_ADDR = 'h3a, //
849 parameter CLK_CNTRL = 0,
850 parameter CLK_STATUS = 1,
852 // These are needed for Python:
854 // Debug module (read/write serial ring)
855 parameter DEBUG_ADDR = 'h710, //..'h713 // SuppressThisWarning VEditor
856 parameter DEBUG_MASK = 'h7fc,
857 parameter DEBUG_STATUS_REG_ADDR = 'hfc, // address where status can be read out // SuppressThisWarning VEditor
858 parameter DEBUG_READ_REG_ADDR = 'hfd, // read 32-bit received shifted data// SuppressThisWarning VEditor
859 parameter DEBUG_SHIFT_DATA = 'h0, // shift i/o data by 32 bits// SuppressThisWarning VEditor
860 parameter DEBUG_LOAD = 'h1, // parallel load of the distributed shift registe (both ways)// SuppressThisWarning VEditor
861 parameter DEBUG_SET_STATUS = 'h2, // program status (mode 3?)// SuppressThisWarning VEditor
862 parameter DEBUG_CMD_LATENCY = 2, // >0 extra registers in the debug_sl (distriburted in parallel)// SuppressThisWarning VEditor
864 // setting system clock generated by a single PLL
865 parameter MULTICLK_IN_PERIOD = 20, // 50MHz
866 parameter MULTICLK_DIVCLK = 1, //
867 parameter MULTICLK_MULT = 24, //1200MHz
869 parameter MULTICLK_DIV_DLYREF = 6, // 6 - 200MHz I/O delay reference clock (4 - 300MHz)
871 parameter MULTICLK_DIV_DLYREF = 4, // 4 - 300MHz I/O delay reference clock (6 - 200MHz)
873 parameter MULTICLK_DIV_AXIHP = 8, // 150 MHz for AXI HP
875 parameter MULTICLK_DIV_XCLK = 12, // 100 MHz for compressor
876 parameter MULTICLK_DIV_XCLK2X = 6, // 200 MHz for compressor (when MULTICLK_DIV_XCLK uses 100 MHz)
878 parameter MULTICLK_DIV_XCLK = 5, // 240 MHz for compressor (12 for 100 MHz)
880 parameter MULTICLK_DIV_SYNC = 12, // 100 MHz for inter-camera synchronization and time keeping
881 // Additional parameters for multi-clock PLL (phases and buffer types)
882 parameter MULTICLK_PHASE_FB = 0.0,
883 parameter MULTICLK_PHASE_DLYREF = 0.0,
884 parameter MULTICLK_BUF_DLYREF = "BUFG",
885 parameter MULTICLK_PHASE_AXIHP = 0.0,
886 parameter MULTICLK_BUF_AXIHP = "BUFG",
887 parameter MULTICLK_PHASE_XCLK = 0.0,
888 parameter MULTICLK_BUF_XCLK = "BUFG",
890 parameter MULTICLK_PHASE_XCLK2X = 0.0,
891 parameter MULTICLK_BUF_XCLK2X = "BUFG",
893 parameter MULTICLK_PHASE_SYNC = 0.0,
894 parameter MULTICLK_BUF_SYNC = "BUFG",
896 // parameter CLKIN_PERIOD_AXIHP = 20, //ns >1.25, 600<Fvco<1200
897 // parameter DIVCLK_DIVIDE_AXIHP = 1,
898 // parameter CLKFBOUT_MULT_AXIHP = 18, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
899 // parameter CLKOUT_DIV_AXIHP = 6, // To get 150MHz for the reference clock
900 // parameter BUF_CLK1X_AXIHP = "BUFG", // "BUFG", "BUFH", "BUFR", "NONE"
902 parameter CLKIN_PERIOD_PCLK = 42, // 24MHz (actually needed is 24.4444
903 parameter DIVCLK_DIVIDE_PCLK = 1,
904 parameter CLKFBOUT_MULT_PCLK = 36, // 880 MHz
905 parameter CLKOUT_DIV_PCLK = 4, // 220 MHz
906 parameter CLKOUT_DIV_PCLK2X = 2, // 440 MHz
908 parameter CLKIN_PERIOD_PCLK = 42, // 24MHz
909 parameter DIVCLK_DIVIDE_PCLK = 1,
910 parameter CLKFBOUT_MULT_PCLK = 40, // 960 MHz
911 parameter CLKOUT_DIV_PCLK = 10, // 96MHz
912 parameter CLKOUT_DIV_PCLK2X = 5, // 192 MHz
914 parameter PHASE_CLK2X_PCLK = 0.000,
915 parameter BUF_CLK1X_PCLK = "BUFG",
916 parameter BUF_CLK1X_PCLK2X = "BUFG",
919 parameter MEMCLK_CAPACITANCE = "DONT_CARE",
920 parameter MEMCLK_IBUF_LOW_PWR = "TRUE",
921 parameter MEMCLK_IOSTANDARD = "SSTL15",
923 parameter FFCLK0_CAPACITANCE = "DONT_CARE",
924 parameter FFCLK0_DIFF_TERM = "FALSE",
925 parameter FFCLK0_IBUF_LOW_PWR = "TRUE",
926 parameter FFCLK0_IOSTANDARD = "RSDS_25",
928 parameter FFCLK1_CAPACITANCE = "DONT_CARE",
929 parameter FFCLK1_DIFF_TERM = "FALSE",
930 parameter FFCLK1_IBUF_LOW_PWR = "TRUE",
931 parameter FFCLK1_IOSTANDARD = "RSDS_25"
1.8.12