util_modules Directory Reference

Files
file	axi_hp_clk.v [code]
	Generate global clock for axi_hp.
file	clk_to_clk2x.v [code]
	move data between clk and clk2x (nominally posedge aligned)
file	clocks393.v [code]
	Generating global clocks for x393 (excluding memcntrl and SATA)
file	clocks393m.v [code]
	Generating global clocks for x393 (excluding memcntrl and SATA)
file	cmd_deser.v [code]
	Expand command address/data from a byte-wide.
file	cmd_frame_sequencer.v [code]
	Store/dispatch commands on per-frame basis.
file	cmd_mux.v [code]
	Command multiplexer between AXI and frame-based command sequencer.
file	cmd_readback.v [code]
	Store control register data and readback.
file	cmd_seq_mux.v [code]
	Command multiplexer from 4 channels of frame-based command sequencers.
file	debug_master.v [code]
	Debug master module to send/receive serial debug data.
file	debug_slave.v [code]
	Send/receive debug data over the serial ring.
file	dly01_16.v [code]
	Synchronous delay by 1-16 clock cycles with reset (will map to primitive)
file	dly_16.v [code]
	Synchronous delay by 1-16 clock cycles with reset (will map to primitives)
file	dual_clock_source.v [code]
	generate clk and clk2x with configurable output buffers
file	elastic_cross_clock.v [code]
	Generate a train of pulses through the clock domains boundary.
file	fifo_1cycle.v [code]
	Configurable synchronous FIFO using the same clock for read and write Single clock cycle latency - simple fifo using sync in, async out RAM, no registers on input and output.
file	fifo_2regs.v [code]
	Simple two-register FIFO, no over/under check, behaves correctly only for correct inputs.
file	fifo_cross_clocks.v [code]
	Configurable FIFO with separate read and write clocks.
file	fifo_same_clock.v [code]
	Configurable synchronous FIFO using the same clock for read and write.
file	fifo_same_clock_fill.v [code]
	Configurable synchronous FIFO using the same clock for read and write. Provides fill level - number of words currently in FIFO.
file	fifo_sameclock_control.v [code]
	BRAM-based fifo control, uses BARM output registers.
file	frame_num_sync.v [code]
	Propagating frame number from acquisition to compressor output.
file	gpio393.v [code]
	Control of the 10 GPIO signals of the 10393 board Converted from twelve_ios.v of the x353 project (2005)
file	index_max_16.v [code]
	Find index of the maximal of 16 values (masked), 4 cycle latency.
file	level_cross_clocks.v [code]
	re-sample signal to a different clock to reduce metastability
file	masked_max_reg.v [code]
	Finds maximal of two masked values, registers result.
file	mcont_common_chnbuf_reg.v [code]
	Registering data from channel buffer to memory controller.
file	mcont_from_chnbuf_reg.v [code]
	Registering data from channel buffer to memory controller.
file	mcont_to_chnbuf_reg.v [code]
	Registering data from memory controller to channel buffer.
file	multipulse_cross_clock.v [code]
	Generate a train of pulses through clock domains boundary.
file	pri1hot16.v [code]
	Priority select one of 16 inputs.
file	pulse_cross_clock.v [code]
	Propagate a single pulse through clock domain boundary For same frequencies input pulses can have 1:3 duty cycle EXTRA_DLY=0 and 1:5 for EXTRA_DLY=1.
file	resync_data.v [code]
	Resynchronize data between clock domains. No over/underruns are checker, start with half FIFO full. Async reset sets specifies output values regardless of the clocks.
file	round_robin.v [code]
	Round-robin arbiter.
file	status_generate.v [code]
	generate byte-serial status data
file	status_read.v [code]
	Receives status read data (low bandwidth) from multiple subsystems byte-serial, stores in axi-addressable memory 8-bita ddress is received from the source module, as well as another (optional) byte of sequence number (set in write command) Sequence number (received first afther the address) is stored as a high byte, lower bytes are the actual payload, starting from lower byte (not all 3 are required. Single-bit responsen can be combined in the same byte with the sequence number to use just 2-byte packets? TODO: add interrupt capabilities.
file	status_router16.v [code]
	Routes status data from 16 sources.
file	status_router2.v [code]
	2:1 status data router/mux
file	status_router4.v [code]
	Routes status data from 4 sources.
file	status_router8.v [code]
	Routes status data from 8 sources.
file	sync_resets.v [code]
	Generate synchronous resets for several clocks, leaving room for generous register duplication.
file	table_ad_receive.v [code]
	Receive tabble address/data sent by table_ad_transmit.
file	table_ad_transmit.v [code]
	transmit byte-wide table address/data from 32-bit cmd_desr In 32-bit mode we duty cycle is >= 6, so there will always be gaps in chn_stb[i] active