2 * @file fpga_version.vh
4 * @author Andrey Filippov
6 * @brief Defining run-time readable FPGA code version
8 * @copyright Copyright (c) 2015 Elphel, Inc.
12 * fpga_version.vh is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation, either version 3 of the License, or
15 * (at your option) any later version.
17 * fpga_version.vh is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program. If not, see <http://www.gnu.org/licenses/> .
25 * Additional permission under GNU GPL version 3 section 7:
26 * If you modify this Program, or any covered work, by linking or combining it
27 * with independent modules provided by the FPGA vendor only (this permission
28 * does not extend to any 3-rd party modules, "soft cores" or macros) under
29 * different license terms solely for the purpose of generating binary "bitstream"
30 * files and/or simulating the code, the copyright holders of this Program give
31 * you the right to distribute the covered work without those independent modules
32 * as long as the source code for them is available from the FPGA vendor free of
33 * charge, and there is no dependence on any encrypted modules for simulating of
34 * the combined code. This permission applies to you if the distributed code
35 * contains all the components and scripts required to completely simulate it
36 * with at least one of the Free Software programs.
38 parameter FPGA_VERSION = 32'h03930099; // parallel, with dct_chen, all met, 79.2%
39 // parameter FPGA_VERSION = 32'h03930098; // serial, trying dct_chen - works, removing old completely, constraints met80.?%
40 // parameter FPGA_VERSION = 32'h03930097; // serial, trying dct_chen - works
41 // parameter FPGA_VERSION = 32'h03930096; // serial, next (before changing DCT)
42 // parameter FPGA_VERSION = 32'h03930095; // parallel -0.068/-0.342/5 82.38%
43 // parameter FPGA_VERSION = 32'h03930094; // hispi, disabling debug -0.187/-1.252/16 84.14%
44 // parameter FPGA_VERSION = 32'h03930093; // hispi, masking sensor data to memory buffer, debug still on
45 // parameter FPGA_VERSION = 32'h03930092; // hispi, even more debugging memory pages sens-> memory
46 // parameter FPGA_VERSION = 32'h03930091; // hispi, more debugging memory pages sens-> memory
47 // parameter FPGA_VERSION = 32'h03930090; // hispi, debugging memory pages sens-> memory (not met)
48 // parameter FPGA_VERSION = 32'h0393008f; // parallel, all the same
49 // parameter FPGA_VERSION = 32'h0393008e; // hispi, adding i2c fifo fill, all met,83.73%
50 // parameter FPGA_VERSION = 32'h0393008d; // parallel, adding i2c fifo fill max err 0.128, 82.61%
51 // parameter FPGA_VERSION = 32'h0393008c; // hispi, all met, 83.55%
52 // parameter FPGA_VERSION = 32'h0393008b; // parallel, all met, 82.06% . Reran 0.051ns error, 82.02%
53 // parameter FPGA_VERSION = 32'h0393008a; // HiSPI sensor (14 MPix) no timing errors
54 // parameter FPGA_VERSION = 32'h03930089; // Auto-synchronizing i2c sequencers with the command ones
55 // parameter FPGA_VERSION = 32'h03930088; // Fixing circbuf rollover pointers bug (only one path violated)
56 // parameter FPGA_VERSION = 32'h03930087; // Fixed default 90% quantization table
57 // parameter FPGA_VERSION = 32'h03930087; // Synchronizing i2c sequencer frame number with that of a command sequencer
58 // parameter FPGA_VERSION = 32'h03930086; // Adding byte-wide JTAG read to speed-up 10359 load
59 // parameter FPGA_VERSION = 32'h03930085; // Adding software control for i2c pins when sequencer is stopped, timing matched
60 // parameter FPGA_VERSION = 32'h03930084; // Back to iserdes, inverting xfpgatdo - met
61 // parameter FPGA_VERSION = 32'h03930083; // Debugging JTAG, using plain IOBUF
62 // parameter FPGA_VERSION = 32'h03930082; // trying other path to read xfpgatdo
63 // parameter FPGA_VERSION = 32'h03930081; // re-started parallel - timing met
64 // parameter FPGA_VERSION = 32'h03930080; // serial, failed timing, >84%
65 // parameter FPGA_VERSION = 32'h0393007f; // More constraints files tweaking
66 // parameter FPGA_VERSION = 32'h0393007e; // Trying .tcl constraints instead of xdc - timing met
67 // parameter FPGA_VERSION = 32'h0393007d; // Changing IMU logger LOGGER_PAGE_IMU 0-> 3 to avoid overlap with other registers. Timing met
68 // parameter FPGA_VERSION = 32'h0393007c; // fixed cmdseqmux - reporting interrupt status and mask correctly
69 // parameter FPGA_VERSION = 32'h0393007b; // lvcmos25_lvds_25_diff
70 // parameter FPGA_VERSION = 32'h0393007a; // lvcmos25_ppds_25_nodiff - OK
71 // parameter FPGA_VERSION = 32'h03930079; // diff - failed
72 // parameter FPGA_VERSION = 32'h03930078; // lvcmos18_ppds_25_nodiff
73 // parameter FPGA_VERSION = 32'h03930077; // Restoring IOSTANDARDs - OK
74 // parameter FPGA_VERSION = 32'h03930076; // Trying PPDS_25 with 1.8 actual power - Stuck when applying 1.8 or 2.5V
75 // parameter FPGA_VERSION = 32'h03930075; // Trying IN_TERM = "UNTUNED_50"
76 // parameter FPGA_VERSION = 32'h03930074; // Adding SATA controller 16365 ( 83.28%)
77 // parameter FPGA_VERSION = 32'h03930073; // Adding interrupts support
78 // parameter FPGA_VERSION = 32'h03930072; // Adding hact monitor bit 77.9%, failed timing
79 // parameter FPGA_VERSION = 32'h03930071; // Fixing AXI HP multiplexer xclk -0.083 -1.968 44 / 15163 (77.17%)
80 // parameter FPGA_VERSION = 32'h03930070; // Fixing HiSPi xclk -0.049 -0.291 17, utilization 15139 (77.04%)
81 // parameter FPGA_VERSION = 32'h0393006f; // Fixing JP4 mode - xcl -0.002 -0.004 2, utilization 15144 (77.07 %)
82 // parameter FPGA_VERSION = 32'h0393006f; // Fixing JP4 mode - xclk -0.209/-2.744/23, utilization 15127 (76.98%)
83 // parameter FPGA_VERSION = 32'h0393006e; // Trying lane switch again after bug fix, failing 1 in ddr3_mclk -> ddr3_clk_div by -0.023
84 // parameter FPGA_VERSION = 32'h0393006d; // -1 with lane switch - does not work
85 // parameter FPGA_VERSION = 32'h0393006d; // Reversing pixels/lanes order xclk violated -0.154
86 // parameter FPGA_VERSION = 32'h0393006c; // will try debug for HiSPi. xclk violated by -0.030, slices 15062 (76.65%)
87 // parameter FPGA_VERSION = 32'h0393006b; // Correcting sensor external clock generation - was wrong division. xclk violated by 0.095 ns
88 // parameter FPGA_VERSION = 32'h0393006a; // modified clock generation, trying with HiSPi - 72.77% utilization x40..x60
89 // parameter FPGA_VERSION = 32'h03930069; // modified clock generation, rebuilding for parallel sensors - all met, 71.8% utilization
90 // Worked OK, but different phase for sensor 0 (all quadrants as 1,3 OK)
91 // parameter FPGA_VERSION = 32'h03930068; // trying BUFR/FUFIO on all sensors ipclk/ipclk2x
92 // parameter FPGA_VERSION = 32'h03930067; // removing DUMMY_TO_KEEP, moving IOSTANDARD to HDL code
93 // parameter FPGA_VERSION = 32'h03930066; // trying just one histogram to watch utilization - with 4 was: Slice 15913 (80.98%), now Slice = 14318 (72.87%)
94 // parameter FPGA_VERSION = 32'h03930065; // (same rev) all met, using "old" (non-inverted) phase - OK (full phase range)
95 // parameter FPGA_VERSION = 32'h03930065; // switch phy_top.v (all met) - OK with inverted phase control (reduced phase range)
96 // parameter FPGA_VERSION = 32'h03930064; // switch mcomtr_sequencer.v (xclk not met) - wrong!
97 // parameter FPGA_VERSION = 32'h03930063; // switch mcntrl_linear_rw.v (met) good, worse mem valid phases
98 // parameter FPGA_VERSION = 32'h03930062; // (met)debugging - what was broken (using older versions of some files) - mostly OK (some glitches)
99 // parameter FPGA_VERSION = 32'h03930061; // restored bufr instead of bufio for memory high speed clock
100 // parameter FPGA_VERSION = 32'h03930060; // moving CLK1..3 in memory controller MMCM, keeping CLK0 and FB. Stuck at memory calib
101 // parameter FPGA_VERSION = 32'h0393005f; // restored mclk back to 200KHz, registers added to csconvert18a
102 // parameter FPGA_VERSION = 32'h0393005e; // trying mclk = 225 MHz (was 200MHz) define MCLK_VCO_MULT 18
103 // parameter FPGA_VERSION = 32'h0393005d; // trying mclk = 250 MHz (was 200MHz) define MCLK_VCO_MULT 20
104 // parameter FPGA_VERSION = 32'h0393005c; // 250MHz OK, no timing violations
105 // parameter FPGA_VERSION = 32'h0393005b; // 250MHz Not tested, timing violation in bit_stuffer_escape: xclk -0.808 -142.047 515
106 // parameter FPGA_VERSION = 32'h0393005a; // Trying xclk = 250MHz - timing viloations in xdct393, but particular hardware works
107 // parameter FPGA_VERSION = 32'h03930059; // 'new' (no pclk2x, no xclk2x clocks) sensor/converter w/o debug - OK
108 // parameter FPGA_VERSION = 32'h03930058; // 'new' (no pclk2x, no xclk2x clocks) sensor/converter w/o debug - broken end of frame
109 // parameter FPGA_VERSION = 32'h03930057; // 'new' (no pclk2x, yes xclk2x clocks) sensor/converter w/o debug - OK
110 // parameter FPGA_VERSION = 32'h03930056; // 'new' (no 2x clocks) sensor/converter w/o debug - broken
111 // parameter FPGA_VERSION = 32'h03930055; // 'old' sensor/converter w/o debug, fixed bug with irst - OK
112 // parameter FPGA_VERSION = 32'h03930054; // 'old' sensor/converter with debug
113 // parameter FPGA_VERSION = 32'h03930053; // trying if(reset ) reg <- 'bx
1.8.12