x393  1.0
FPGAcodeforElphelNC393camera
x393_placement.tcl
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1 #################################################################################
2 # Filename: x393_placement.tcl
3 # Date:2016-03-28
4 # Author: Andrey Filippov
5 # Description: Placementg constraints (selected by HISPI parameter in system_devines.vh)
6 #
7 # Copyright (c) 2016 Elphel, Inc.
8 # x393_placement.tcl is free software; you can redistribute it and/or modify
9 # it under the terms of the GNU General Public License as published by
10 # the Free Software Foundation, either version 3 of the License, or
11 # (at your option) any later version.
12 #
13 # x393_placement.tcl is distributed in the hope that it will be useful,
14 # but WITHOUT ANY WARRANTY; without even the implied warranty of
15 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 # GNU General Public License for more details.
17 #
18 # You should have received a copy of the GNU General Public License
19 # along with this program. If not, see <http://www.gnu.org/licenses/> .
20 #
21 # Additional permission under GNU GPL version 3 section 7:
22 # If you modify this Program, or any covered work, by linking or combining it
23 # with independent modules provided by the FPGA vendor only (this permission
24 # does not extend to any 3-rd party modules, "soft cores" or macros) under
25 # different license terms solely for the purpose of generating binary "bitstream"
26 # files and/or simulating the code, the copyright holders of this Program give
27 # you the right to distribute the covered work without those independent modules
28 # as long as the source code for them is available from the FPGA vendor free of
29 # charge, and there is no dependence on any encrypted modules for simulating of
30 # the combined code. This permission applies to you if the distributed code
31 # contains all the components and scripts required to completely simulate it
32 # with at least one of the Free Software programs.
33 #################################################################################
34 cd ~/vdt/x393
35 set infile [open "system_defines.vh" r]
36 set HISPI 0
37 while { [gets $infile line] >= 0 } {
38  if { [regexp {(.*)`define(\s*)HISPI} $line matched prematch] } {
39  if {[regexp "//" $prematch] != 0} { continue}
40  set HISPI 1
41  break
42  }
43 }
44 close $infile
45 if { $HISPI} {
46  puts "using HISPI sensors"
47 } else {
48  puts "using parallel sensors"
49 }
50 #Placement constraints (I/O pads)
51 set_property PACKAGE_PIN J4 [get_ports {SDRST}]
52 set_property PACKAGE_PIN K3 [get_ports {SDCLK}]
53 set_property PACKAGE_PIN K2 [get_ports {SDNCLK}]
54 set_property PACKAGE_PIN N3 [get_ports {SDA[0]}]
55 set_property PACKAGE_PIN H2 [get_ports {SDA[1]}]
56 set_property PACKAGE_PIN M2 [get_ports {SDA[2]}]
57 set_property PACKAGE_PIN P5 [get_ports {SDA[3]}]
58 set_property PACKAGE_PIN H1 [get_ports {SDA[4]}]
59 set_property PACKAGE_PIN M3 [get_ports {SDA[5]}]
60 set_property PACKAGE_PIN J1 [get_ports {SDA[6]}]
61 set_property PACKAGE_PIN P4 [get_ports {SDA[7]}]
62 set_property PACKAGE_PIN K1 [get_ports {SDA[8]}]
63 set_property PACKAGE_PIN P3 [get_ports {SDA[9]}]
64 set_property PACKAGE_PIN F2 [get_ports {SDA[10]}]
65 set_property PACKAGE_PIN H3 [get_ports {SDA[11]}]
66 set_property PACKAGE_PIN G3 [get_ports {SDA[12]}]
67 set_property PACKAGE_PIN N2 [get_ports {SDA[13]}]
68 set_property PACKAGE_PIN J3 [get_ports {SDA[14]}]
69 set_property PACKAGE_PIN N1 [get_ports {SDBA[0]}]
70 set_property PACKAGE_PIN F1 [get_ports {SDBA[1]}]
71 set_property PACKAGE_PIN P1 [get_ports {SDBA[2]}]
72 set_property PACKAGE_PIN G4 [get_ports {SDWE}]
73 set_property PACKAGE_PIN L2 [get_ports {SDRAS}]
74 set_property PACKAGE_PIN L1 [get_ports {SDCAS}]
75 set_property PACKAGE_PIN E1 [get_ports {SDCKE}]
76 set_property PACKAGE_PIN M7 [get_ports {SDODT}]
77 set_property PACKAGE_PIN K6 [get_ports {SDD[0]}]
78 set_property PACKAGE_PIN L4 [get_ports {SDD[1]}]
79 set_property PACKAGE_PIN K7 [get_ports {SDD[2]}]
80 set_property PACKAGE_PIN K4 [get_ports {SDD[3]}]
81 set_property PACKAGE_PIN L6 [get_ports {SDD[4]}]
82 set_property PACKAGE_PIN M4 [get_ports {SDD[5]}]
83 set_property PACKAGE_PIN L7 [get_ports {SDD[6]}]
84 set_property PACKAGE_PIN N5 [get_ports {SDD[7]}]
85 set_property PACKAGE_PIN H5 [get_ports {SDD[8]}]
86 set_property PACKAGE_PIN J6 [get_ports {SDD[9]}]
87 set_property PACKAGE_PIN G5 [get_ports {SDD[10]}]
88 set_property PACKAGE_PIN H6 [get_ports {SDD[11]}]
89 set_property PACKAGE_PIN F5 [get_ports {SDD[12]}]
90 set_property PACKAGE_PIN F7 [get_ports {SDD[13]}]
91 set_property PACKAGE_PIN F4 [get_ports {SDD[14]}]
92 set_property PACKAGE_PIN F6 [get_ports {SDD[15]}]
93 set_property PACKAGE_PIN N7 [get_ports {DQSL}]
94 set_property PACKAGE_PIN N6 [get_ports {NDQSL}]
95 set_property PACKAGE_PIN H7 [get_ports {DQSU}]
96 set_property PACKAGE_PIN G7 [get_ports {NDQSU}]
97 set_property PACKAGE_PIN L5 [get_ports {SDDML}]
98 set_property PACKAGE_PIN J5 [get_ports {SDDMU}]
99 
100 #not yet used, just for debugging
101 set_property PACKAGE_PIN M5 [get_ports {memclk}]
102 
103 
104 # ======== GPIO pins ===============
105 # inout [GPIO_N-1:0] gpio_pins,
106 set_property PACKAGE_PIN B4 [get_ports {gpio_pins[0]}]
107 set_property PACKAGE_PIN A4 [get_ports {gpio_pins[1]}]
108 set_property PACKAGE_PIN A2 [get_ports {gpio_pins[2]}]
109 set_property PACKAGE_PIN A1 [get_ports {gpio_pins[3]}]
110 set_property PACKAGE_PIN C3 [get_ports {gpio_pins[4]}]
111 set_property PACKAGE_PIN D3 [get_ports {gpio_pins[5]}]
112 set_property PACKAGE_PIN D1 [get_ports {gpio_pins[6]}]
113 set_property PACKAGE_PIN C1 [get_ports {gpio_pins[7]}]
114 set_property PACKAGE_PIN C2 [get_ports {gpio_pins[8]}]
115 set_property PACKAGE_PIN B2 [get_ports {gpio_pins[9]}]
116 
117 # =========Differential clock inputs ==========
118 # input ffclk0p, // Y12
119 # input ffclk0n, // Y11
120 # input ffclk1p, // W14
121 # input ffclk1n // W13
122 set_property PACKAGE_PIN Y12 [get_ports {ffclk0p}]
123 set_property PACKAGE_PIN Y11 [get_ports {ffclk0n}]
124 set_property PACKAGE_PIN W14 [get_ports {ffclk1p}]
125 set_property PACKAGE_PIN W13 [get_ports {ffclk1n}]
126 
127 
128 
129 # ================= Sensor port 0 =================
130 set_property PACKAGE_PIN T10 [get_ports {sns1_dp[0]}]
131 set_property PACKAGE_PIN T9 [get_ports {sns1_dn[0]}]
132 set_property PACKAGE_PIN U10 [get_ports {sns1_dp[1]}]
133 set_property PACKAGE_PIN V10 [get_ports {sns1_dn[1]}]
134 set_property PACKAGE_PIN V8 [get_ports {sns1_dp[2]}]
135 set_property PACKAGE_PIN W8 [get_ports {sns1_dn[2]}]
136 set_property PACKAGE_PIN W9 [get_ports {sns1_dp[3]}]
137 set_property PACKAGE_PIN Y8 [get_ports {sns1_dn[3]}]
138 if { $HISPI } {
139  set_property PACKAGE_PIN AB9 [get_ports {sns1_dp74[4]}]
140  set_property PACKAGE_PIN AB8 [get_ports {sns1_dn74[4]}]
141  set_property PACKAGE_PIN AB13 [get_ports {sns1_dp74[5]}]
142  set_property PACKAGE_PIN AB12 [get_ports {sns1_dn74[5]}]
143  set_property PACKAGE_PIN AA12 [get_ports {sns1_dp74[6]}]
144  set_property PACKAGE_PIN AA11 [get_ports {sns1_dn74[6]}]
145  set_property PACKAGE_PIN W11 [get_ports {sns1_dp74[7]}]
146  set_property PACKAGE_PIN W10 [get_ports {sns1_dn74[7]}]
147 } else {
148  set_property PACKAGE_PIN AB9 [get_ports {sns1_dp[4]}]
149  set_property PACKAGE_PIN AB8 [get_ports {sns1_dn[4]}]
150  set_property PACKAGE_PIN AB13 [get_ports {sns1_dp[5]}]
151  set_property PACKAGE_PIN AB12 [get_ports {sns1_dn[5]}]
152  set_property PACKAGE_PIN AA12 [get_ports {sns1_dp[6]}]
153  set_property PACKAGE_PIN AA11 [get_ports {sns1_dn[6]}]
154  set_property PACKAGE_PIN W11 [get_ports {sns1_dp[7]}]
155  set_property PACKAGE_PIN W10 [get_ports {sns1_dn[7]}]
156 }
157 set_property PACKAGE_PIN AA10 [get_ports {sns1_clkp}]
158 set_property PACKAGE_PIN AB10 [get_ports {sns1_clkn}]
159 set_property PACKAGE_PIN Y9 [get_ports {sns1_scl}]
160 set_property PACKAGE_PIN AA9 [get_ports {sns1_sda}]
161 set_property PACKAGE_PIN U9 [get_ports {sns1_ctl}]
162 set_property PACKAGE_PIN U8 [get_ports {sns1_pg}]
163 
164 
165 # ================= Sensor port 1 =================
166 set_property PACKAGE_PIN U15 [get_ports {sns2_dp[0]}]
167 set_property PACKAGE_PIN U14 [get_ports {sns2_dn[0]}]
168 set_property PACKAGE_PIN V15 [get_ports {sns2_dp[1]}]
169 set_property PACKAGE_PIN W15 [get_ports {sns2_dn[1]}]
170 set_property PACKAGE_PIN U13 [get_ports {sns2_dp[2]}]
171 set_property PACKAGE_PIN V13 [get_ports {sns2_dn[2]}]
172 set_property PACKAGE_PIN V12 [get_ports {sns2_dp[3]}]
173 set_property PACKAGE_PIN V11 [get_ports {sns2_dn[3]}]
174 if { $HISPI } {
175  set_property PACKAGE_PIN AA17 [get_ports {sns2_dp74[4]}]
176  set_property PACKAGE_PIN AB17 [get_ports {sns2_dn74[4]}]
177  set_property PACKAGE_PIN AA15 [get_ports {sns2_dp74[5]}]
178  set_property PACKAGE_PIN AB15 [get_ports {sns2_dn74[5]}]
179  set_property PACKAGE_PIN AA14 [get_ports {sns2_dp74[6]}]
180  set_property PACKAGE_PIN AB14 [get_ports {sns2_dn74[6]}]
181  set_property PACKAGE_PIN Y14 [get_ports {sns2_dp74[7]}]
182  set_property PACKAGE_PIN Y13 [get_ports {sns2_dn74[7]}]
183 } else {
184  set_property PACKAGE_PIN AA17 [get_ports {sns2_dp[4]}]
185  set_property PACKAGE_PIN AB17 [get_ports {sns2_dn[4]}]
186  set_property PACKAGE_PIN AA15 [get_ports {sns2_dp[5]}]
187  set_property PACKAGE_PIN AB15 [get_ports {sns2_dn[5]}]
188  set_property PACKAGE_PIN AA14 [get_ports {sns2_dp[6]}]
189  set_property PACKAGE_PIN AB14 [get_ports {sns2_dn[6]}]
190  set_property PACKAGE_PIN Y14 [get_ports {sns2_dp[7]}]
191  set_property PACKAGE_PIN Y13 [get_ports {sns2_dn[7]}]
192 }
193 set_property PACKAGE_PIN Y16 [get_ports {sns2_clkp}]
194 set_property PACKAGE_PIN AA16 [get_ports {sns2_clkn}]
195 set_property PACKAGE_PIN T12 [get_ports {sns2_scl}]
196 set_property PACKAGE_PIN U12 [get_ports {sns2_sda}]
197 set_property PACKAGE_PIN V16 [get_ports {sns2_ctl}]
198 set_property PACKAGE_PIN W16 [get_ports {sns2_pg}]
199 
200 # ================= Sensor port 2 =================
201 set_property PACKAGE_PIN AA22 [get_ports {sns3_dp[0]}]
202 set_property PACKAGE_PIN AB22 [get_ports {sns3_dn[0]}]
203 set_property PACKAGE_PIN W21 [get_ports {sns3_dp[1]}]
204 set_property PACKAGE_PIN Y22 [get_ports {sns3_dn[1]}]
205 set_property PACKAGE_PIN V21 [get_ports {sns3_dp[2]}]
206 set_property PACKAGE_PIN V22 [get_ports {sns3_dn[2]}]
207 set_property PACKAGE_PIN W19 [get_ports {sns3_dp[3]}]
208 set_property PACKAGE_PIN W20 [get_ports {sns3_dn[3]}]
209 if { $HISPI } {
210  set_property PACKAGE_PIN N21 [get_ports {sns3_dp74[4]}]
211  set_property PACKAGE_PIN N22 [get_ports {sns3_dn74[4]}]
212  set_property PACKAGE_PIN R22 [get_ports {sns3_dp74[5]}]
213  set_property PACKAGE_PIN T22 [get_ports {sns3_dn74[5]}]
214  set_property PACKAGE_PIN P21 [get_ports {sns3_dp74[6]}]
215  set_property PACKAGE_PIN R21 [get_ports {sns3_dn74[6]}]
216  set_property PACKAGE_PIN T20 [get_ports {sns3_dp74[7]}]
217  set_property PACKAGE_PIN U20 [get_ports {sns3_dn74[7]}]
218 } else {
219  set_property PACKAGE_PIN N21 [get_ports {sns3_dp[4]}]
220  set_property PACKAGE_PIN N22 [get_ports {sns3_dn[4]}]
221  set_property PACKAGE_PIN R22 [get_ports {sns3_dp[5]}]
222  set_property PACKAGE_PIN T22 [get_ports {sns3_dn[5]}]
223  set_property PACKAGE_PIN P21 [get_ports {sns3_dp[6]}]
224  set_property PACKAGE_PIN R21 [get_ports {sns3_dn[6]}]
225  set_property PACKAGE_PIN T20 [get_ports {sns3_dp[7]}]
226  set_property PACKAGE_PIN U20 [get_ports {sns3_dn[7]}]
227 }
228 set_property PACKAGE_PIN T21 [get_ports {sns3_clkp}]
229 set_property PACKAGE_PIN U22 [get_ports {sns3_clkn}]
230 set_property PACKAGE_PIN Y21 [get_ports {sns3_scl}]
231 set_property PACKAGE_PIN AA21 [get_ports {sns3_sda}]
232 set_property PACKAGE_PIN AA20 [get_ports {sns3_ctl}]
233 set_property PACKAGE_PIN AB20 [get_ports {sns3_pg}]
234 
235 # ================= Sensor port 3 =================
236 set_property PACKAGE_PIN V17 [get_ports {sns4_dp[0]}]
237 set_property PACKAGE_PIN W18 [get_ports {sns4_dn[0]}]
238 set_property PACKAGE_PIN Y19 [get_ports {sns4_dp[1]}]
239 set_property PACKAGE_PIN AA19 [get_ports {sns4_dn[1]}]
240 set_property PACKAGE_PIN U19 [get_ports {sns4_dp[2]}]
241 set_property PACKAGE_PIN V20 [get_ports {sns4_dn[2]}]
242 set_property PACKAGE_PIN U18 [get_ports {sns4_dp[3]}]
243 set_property PACKAGE_PIN V18 [get_ports {sns4_dn[3]}]
244 if { $HISPI } {
245  set_property PACKAGE_PIN P18 [get_ports {sns4_dp74[4]}]
246  set_property PACKAGE_PIN P19 [get_ports {sns4_dn74[4]}]
247  set_property PACKAGE_PIN N17 [get_ports {sns4_dp74[5]}]
248  set_property PACKAGE_PIN N18 [get_ports {sns4_dn74[5]}]
249  set_property PACKAGE_PIN N20 [get_ports {sns4_dp74[6]}]
250  set_property PACKAGE_PIN P20 [get_ports {sns4_dn74[6]}]
251  set_property PACKAGE_PIN R17 [get_ports {sns4_dp74[7]}]
252  set_property PACKAGE_PIN R18 [get_ports {sns4_dn74[7]}]
253 } else {
254  set_property PACKAGE_PIN P18 [get_ports {sns4_dp[4]}]
255  set_property PACKAGE_PIN P19 [get_ports {sns4_dn[4]}]
256  set_property PACKAGE_PIN N17 [get_ports {sns4_dp[5]}]
257  set_property PACKAGE_PIN N18 [get_ports {sns4_dn[5]}]
258  set_property PACKAGE_PIN N20 [get_ports {sns4_dp[6]}]
259  set_property PACKAGE_PIN P20 [get_ports {sns4_dn[6]}]
260  set_property PACKAGE_PIN R17 [get_ports {sns4_dp[7]}]
261  set_property PACKAGE_PIN R18 [get_ports {sns4_dn[7]}]
262 }
263 set_property PACKAGE_PIN R16 [get_ports {sns4_clkp}]
264 set_property PACKAGE_PIN T16 [get_ports {sns4_clkn}]
265 set_property PACKAGE_PIN AB18 [get_ports {sns4_scl}]
266 set_property PACKAGE_PIN AB19 [get_ports {sns4_sda}]
267 set_property PACKAGE_PIN Y17 [get_ports {sns4_ctl}]
268 set_property PACKAGE_PIN Y18 [get_ports {sns4_pg}]
269 
270 # ===================== SATA ======================
271 
272 # bind gtx reference clock
273 set_property PACKAGE_PIN U6 [get_ports EXTCLK_P]
274 set_property PACKAGE_PIN U5 [get_ports EXTCLK_N]
275 
276 # bind sata inputs/outputs
277 set_property PACKAGE_PIN AA5 [get_ports RXN]
278 set_property PACKAGE_PIN AA6 [get_ports RXP]
279 set_property PACKAGE_PIN AB3 [get_ports TXN]
280 set_property PACKAGE_PIN AB4 [get_ports TXP]