cmd_encod_tiled_rd.v File Reference

Command sequencer generator for reading a tiled area up to 1 kB. More...

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Classes
Module	cmd_encod_tiled_rd

Detailed Description

Command sequencer generator for reading a tiled area up to 1 kB.

Module:cmd_encod_tiled_rd

Date

2015-01-23

Author

Andrey Filippov

Memory is mapped so 8 consecuitive rows have same RA, CA and alternating BA (0 to 7). Data will be read in columns 16 bytes wide, then proceding to the next column (if >1). If number of rows is less than 8 it is possible to use keep_open_in input, then there will be no ACTIVATE in other than first column and AUTO RECHARGE will be applied only to the last column (single column OK). if number of rows >=8, that port is ignored. If number of rows is less than 5 (less for slower clock) without keep_open_in tRTP may be not matched. Seems that actual tile heigt mod 8 should be only 0, 6 or7.

Copyright

Copyright (c) 2015 Elphel, Inc.

License:

cmd_encod_tiled_rd.v is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version.

cmd_encod_tiled_rd.v is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

You should have received a copy of the GNU General Public License along with this program. If not, see http://www.gnu.org/licenses/ .

Additional permission under GNU GPL version 3 section 7: If you modify this Program, or any covered work, by linking or combining it with independent modules provided by the FPGA vendor only (this permission does not extend to any 3-rd party modules, "soft cores" or macros) under different license terms solely for the purpose of generating binary "bitstream" files and/or simulating the code, the copyright holders of this Program give you the right to distribute the covered work without those independent modules as long as the source code for them is available from the FPGA vendor free of charge, and there is no dependence on any encrypted modules for simulating of the combined code. This permission applies to you if the distributed code contains all the components and scripts required to completely simulate it with at least one of the Free Software programs.

Definition in file cmd_encod_tiled_rd.v.