varlen_encode_snglclk.v

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module    varlen_encode_snglclk (
    input             clk,       // posedge
    input       [11:0] d,        // 12-bit 2-s complement
    output reg   [3:0] l,        // [3:0] code length, latency 2 clocks
    output reg  [10:0] q);       // [10:0] literal, latency = 2 clocks

    reg    [11:0] d1;

    wire          this0 =  |d1[ 3:0];
    wire          this1 =  |d1[ 7:4];
    wire          this2 =  |d1[10:8];
    wire    [1:0] codel0 = {|d1[ 3: 2],d1[ 3] || (d1[ 1] & ~d1[ 2])};
    wire    [1:0] codel1 = {|d1[ 7: 6],d1[ 7] || (d1[ 5] & ~d1[ 6])};
    wire    [1:0] codel2 = {|d1[   10],          (d1[ 9] & ~d1[10])};
    wire    [3:0] codel =  this2? {2'b10,codel2[1:0]} :
                     (this1? {2'b01, codel1[1:0]} :
                             (this0 ? {2'b00,codel0[1:0]} : 4'b1111));    // after +1 will be 0;

    always @(posedge clk) begin
        d1[  11]    <=  d[11];
        d1[10:0]    <=  d[11] ? -d[10:0] : d[10:0];
    
        q[10:0]     <= d1[11] ? ~d1[10:0] : d1[10:0];
        l    <= codel[3:0]+1;    // needed only ASAP, valid only 2 cycles after start

    end

endmodule