simulation_modules Directory Reference

Files
file	par12_hispi_psp4l.v [code]
	Convertp parallel 12bit to HiSPi packetized-SP 4 lanes.
file	sim_clk_div.v [code]
	Divide clock frequency by integer number.
file	sim_frac_clk_delay.v [code]
	Delay clock-synchronous signal by fractional number of periods.
file	sim_soc_interrupts.v [code]
	SOC interrupts simulation.
file	simul_axi_fifo_out.v [code]
file	simul_axi_hp_rd.v [code]
	Simplified model of AXI_HP read channel (64-bit only)
file	simul_axi_hp_wr.v [code]
	Simplified model of AXI_HP write channel (64-bit only)
file	simul_axi_master_rdaddr.v [code]
	Simulation model for AXI read address channel.
file	simul_axi_master_wdata.v [code]
	Simulation model for AXI write data channel.
file	simul_axi_master_wraddr.v [code]
	Simulation model for AXI write address channel.
file	simul_axi_read.v [code]
	simulation of read data through maxi channel
file	simul_axi_slow_ready.v [code]
	Simulation model for AXI: slow ready generation.
file	simul_clk.v [code]
	Generate clocks for simulation.
file	simul_clk_div_mult.v [code]
	Simulation clock rational multiplier.
file	simul_clk_mult.v [code]
	Clock multiplier.
file	simul_clk_mult_div.v [code]
	Simulation clock rational multiplier.
file	simul_fifo.v [code]
	simple fifo for simulation
file	simul_saxi_gp_wr.v [code]
	Simplified model of AXI_GP write channel.
file	simul_sensor12bits.v [code]
	Generate sensor data.