simul_clk_mult.v

Go to the documentation of this file.

`timescale 1ns/1ps

module  simul_clk_mult#(
        parameter MULTIPLIER = 3,
        parameter SKIP_FIRST = 5
    ) (
        input      clk_in,
        input      en,
        output     clk_out
    );
    real phase;
    real prev_phase = 0.0;
    real out_half_period = 0.0;
    integer num_period = 0;
    reg en1 = 0;
    reg clk_out_r = 0;
    assign clk_out = (MULTIPLIER == 1)? clk_in: clk_out_r;
    always @ (posedge clk_in) begin
        phase = $realtime;
        if (num_period >= SKIP_FIRST) begin
            out_half_period = (phase - prev_phase) / (2 * MULTIPLIER); 
            en1 = 1;
        end
        prev_phase = phase;
        num_period = num_period + 1;
    end
    
    always @ (posedge clk_in) if (en && en1) begin
        clk_out_r = 1;
        repeat (MULTIPLIER - 1) begin
            #out_half_period clk_out_r = 0;
            #out_half_period clk_out_r = 1;
        end
        #out_half_period clk_out_r = 0;
    end

endmodule