ahci Directory Reference

Files
file	ahci_ctrl_stat.v [code]
	Copy of significant register fields, updating them in axi_ahci_regs registers (software accessible)
file	ahci_dma.v [code]
	DMA R/W over 64-AXI channel for AHCI implementation.
file	ahci_dma_rd_fifo.v [code]
	cross clocks, word-realign, 64->32 Convertion from x64 QWORD-aligned AXI data to 32-bit word-aligned data at mclk
file	ahci_dma_rd_stuff.v [code]
	Stuff DWORD data with missing words into continuous 32-bit data.
file	ahci_dma_wr_fifo.v [code]
	cross clocks, word-realign, 32 -> 64 with byte write mask Convertion from x32 DWORD data received from FIS-es @ mclk to QWORD-aligned AXI data
file	ahci_fis_receive.v [code]
	Receives incoming FIS-es, forwards DMA ones to DMA engine Stores received FIS-es if requested.
file	ahci_fis_transmit.v [code]
	Fetches commands, command tables, creates/sends FIS.
file	ahci_fsm.v [code]
	AHCI host+port0 state machine.
file	ahci_sata_layers.v [code]
	Link and PHY SATA layers.
file	ahci_top.v [code]
	Top module of the AHCI implementation.
file	axi_ahci_regs.v [code]
	Registers for single-port AHCI over AXI implementation Combination of PCI Headers, PCI power management, and HBA memory 128 DWORD registers Registers, with bits being RO, RW, RWC, RW1.
file	axi_hp_abort.v [code]
	Trying to gracefully reset AXI HP after aborted transmission For read channel - just keep afi_rready on until RD FIFO is empty (afi_rcount ==0) For write - keep track aof all what was sent so far, assuming aw is always ahead of w Reset only by global reset (system POR) - probably it is not possible to just reset PL or relaod bitfile,.
file	freq_meter.v [code]
	Measure device clock frequency to set the local clock.
file	sata_ahci_top.v [code]
	Top of the AHCI implementation of the host adapter.