x393_dut Member List

This is the complete list of members for x393_dut, including all inherited members.

saxihp0_wid	x393_dut
saxihp0_wr_valid	x393_dut
saxihp0_wr_ready	x393_dut
saxihp0_wr_data	x393_dut
saxihp0_wr_stb	x393_dut
saxihp0_bresp_latency	x393_dut
saxihp0_wr_cap	x393_dut
saxihp0_wr_qos	x393_dut
saxihp0_rd_address	x393_dut
saxihp0_rid	x393_dut
saxihp0_rd_valid	x393_dut
saxihp0_rd_ready	x393_dut
saxihp0_rd_data	x393_dut
saxihp0_rd_resp	x393_dut
saxihp0_rd_cap	x393_dut
saxihp0_rd_qos	x393_dut
saxihp1_wr_address	x393_dut
saxihp1_wid	x393_dut
saxihp1_wr_valid	x393_dut
saxihp1_wr_ready	x393_dut
saxihp1_wr_data	x393_dut
saxihp1_wr_stb	x393_dut
saxihp1_bresp_latency	x393_dut
saxihp1_wr_cap	x393_dut
saxihp1_wr_qos	x393_dut
saxigp0_wr_address	x393_dut
saxigp0_wid	x393_dut
saxigp0_wr_valid	x393_dut
saxigp0_wr_ready	x393_dut
saxigp0_wr_data	x393_dut
saxigp0_wr_stb	x393_dut
saxigp0_wr_size	x393_dut
saxigp0_bresp_latency	x393_dut
ddr3_wrap.WIDTH	dly_16	Parameter
simul_axi_hp_wr.WIDTH	dly_16	Parameter
simul_saxi_gp_wr.WIDTH	dly_16	Parameter
ddr3_wrap.clk	dly_16	Input
simul_axi_hp_wr.clk	dly_16	Input
simul_saxi_gp_wr.clk	dly_16	Input
ddr3_wrap.rst	dly_16	Input
simul_axi_hp_wr.rst	dly_16	Input
simul_saxi_gp_wr.rst	dly_16	Input
ddr3_wrap.dly	dly_16	Input
simul_axi_hp_wr.dly	dly_16	Input
simul_saxi_gp_wr.dly	dly_16	Input
ddr3_wrap.din	dly_16	Input
simul_axi_hp_wr.din	dly_16	Input
simul_saxi_gp_wr.din	dly_16	Input
ddr3_wrap.dout	dly_16	Output
simul_axi_hp_wr.dout	dly_16	Output
simul_saxi_gp_wr.dout	dly_16	Output
saxigp0_wr_qos	x393_dut
irq_r	x393_dut
dutm0_xtra_rdlag	x393_dut
dutm0_xtra_blag	x393_dut
sata_rxn	x393_dut
sata_rxp	x393_dut
sata_txn	x393_dut
sata_txp	x393_dut
sata_extclkp	x393_dut
sata_extclkn	x393_dut
maxigp0aclk	x393_dut
simul_axi_hp_wr.DATA_WIDTH	fifo_same_clock_fill	Parameter
simul_saxi_gp_wr.DATA_WIDTH	fifo_same_clock_fill	Parameter
simul_axi_hp_wr.DATA_DEPTH	fifo_same_clock_fill	Parameter
simul_saxi_gp_wr.DATA_DEPTH	fifo_same_clock_fill	Parameter
simul_axi_hp_wr.rst	fifo_same_clock_fill	Input
simul_saxi_gp_wr.rst	fifo_same_clock_fill	Input
simul_axi_hp_wr.clk	fifo_same_clock_fill	Input
simul_saxi_gp_wr.clk	fifo_same_clock_fill	Input
simul_axi_hp_wr.sync_rst	fifo_same_clock_fill	Input
simul_saxi_gp_wr.sync_rst	fifo_same_clock_fill	Input
maxigp0aresetn	x393_dut
simul_axi_hp_wr.we	fifo_same_clock_fill	Input
simul_saxi_gp_wr.we	fifo_same_clock_fill	Input
simul_axi_hp_wr.re	fifo_same_clock_fill	Input
simul_saxi_gp_wr.re	fifo_same_clock_fill	Input
simul_axi_hp_wr.data_in	fifo_same_clock_fill	Input
simul_saxi_gp_wr.data_in	fifo_same_clock_fill	Input
simul_axi_hp_wr.data_out	fifo_same_clock_fill	Output
simul_saxi_gp_wr.data_out	fifo_same_clock_fill	Output
simul_axi_hp_wr.nempty	fifo_same_clock_fill	Output
simul_saxi_gp_wr.nempty	fifo_same_clock_fill	Output
simul_axi_hp_wr.half_full	fifo_same_clock_fill	Output
simul_saxi_gp_wr.half_full	fifo_same_clock_fill	Output
simul_axi_hp_wr.under	fifo_same_clock_fill	Output
simul_saxi_gp_wr.under	fifo_same_clock_fill	Output
simul_axi_hp_wr.over	fifo_same_clock_fill	Output
simul_saxi_gp_wr.over	fifo_same_clock_fill	Output
simul_axi_hp_wr.wcount	fifo_same_clock_fill	Output
simul_saxi_gp_wr.wcount	fifo_same_clock_fill	Output
simul_axi_hp_wr.rcount	fifo_same_clock_fill	Output
simul_saxi_gp_wr.rcount	fifo_same_clock_fill	Output
maxigp0araddr	x393_dut
simul_axi_hp_wr.wnum_in_fifo	fifo_same_clock_fill	Output
simul_saxi_gp_wr.wnum_in_fifo	fifo_same_clock_fill	Output
simul_axi_hp_wr.rnum_in_fifo	fifo_same_clock_fill	Output
simul_saxi_gp_wr.rnum_in_fifo	fifo_same_clock_fill	Output
simul_axi_hp_wr.DATA_2DEPTH	fifo_same_clock_fill	Parameter
simul_saxi_gp_wr.DATA_2DEPTH	fifo_same_clock_fill	Parameter
simul_axi_hp_wr.fill	fifo_same_clock_fill	Signal
simul_saxi_gp_wr.fill	fifo_same_clock_fill	Signal
simul_axi_hp_wr.wfifo_fill	fifo_same_clock_fill	Signal
simul_saxi_gp_wr.wfifo_fill	fifo_same_clock_fill	Signal
simul_axi_hp_wr.rfifo_fill	fifo_same_clock_fill	Signal
simul_saxi_gp_wr.rfifo_fill	fifo_same_clock_fill	Signal
simul_axi_hp_wr.inreg	fifo_same_clock_fill	Signal
simul_saxi_gp_wr.inreg	fifo_same_clock_fill	Signal
simul_axi_hp_wr.outreg	fifo_same_clock_fill	Signal
simul_saxi_gp_wr.outreg	fifo_same_clock_fill	Signal
simul_axi_hp_wr.ra	fifo_same_clock_fill	Signal
simul_saxi_gp_wr.ra	fifo_same_clock_fill	Signal
simul_axi_hp_wr.wa	fifo_same_clock_fill	Signal
simul_saxi_gp_wr.wa	fifo_same_clock_fill	Signal
maxigp0arvalid	x393_dut
simul_axi_hp_wr.next_fill	fifo_same_clock_fill	Signal
simul_saxi_gp_wr.next_fill	fifo_same_clock_fill	Signal
simul_axi_hp_wr.wem	fifo_same_clock_fill	Signal
simul_saxi_gp_wr.wem	fifo_same_clock_fill	Signal
simul_axi_hp_wr.rem	fifo_same_clock_fill	Signal
simul_saxi_gp_wr.rem	fifo_same_clock_fill	Signal
simul_axi_hp_wr.out_full	fifo_same_clock_fill	Signal
simul_saxi_gp_wr.out_full	fifo_same_clock_fill	Signal
simul_axi_hp_wr.ram	fifo_same_clock_fill	Signal
simul_saxi_gp_wr.ram	fifo_same_clock_fill	Signal
simul_axi_hp_wr.ram_nempty	fifo_same_clock_fill	Signal
simul_saxi_gp_wr.ram_nempty	fifo_same_clock_fill	Signal
maxigp0arready	x393_dut
maxigp0arid	x393_dut
maxigp0arlock	x393_dut
maxigp0arcache	x393_dut
maxigp0arprot	x393_dut
maxigp0arlen	x393_dut
maxigp0arsize	x393_dut
maxigp0arburst	x393_dut
maxigp0arqos	x393_dut
maxigp0rdata	x393_dut
maxigp0rvalid	x393_dut
maxigp0rready	x393_dut
maxigp0rid	x393_dut
maxigp0rlast	x393_dut
maxigp0rresp	x393_dut
maxigp0awaddr	x393_dut
maxigp0awvalid	x393_dut
maxigp0awready	x393_dut
maxigp0awid	x393_dut
maxigp0awlock	x393_dut
maxigp0awcache	x393_dut
maxigp0awprot	x393_dut
maxigp0awlen	x393_dut
maxigp0awsize	x393_dut
maxigp0awburst	x393_dut
EXTRA_DLY	pulse_cross_clock	Parameter
rst	pulse_cross_clock	Input
src_clk	pulse_cross_clock	Input
dst_clk	pulse_cross_clock	Input
in_pulse	pulse_cross_clock	Input
out_pulse	pulse_cross_clock	Output
busy	pulse_cross_clock	Output
EXTRA_DLY_SAFE	pulse_cross_clock	Parameter
in_reg	pulse_cross_clock	Signal
maxigp0awqos	x393_dut
out_reg	pulse_cross_clock	Signal
busy_r	pulse_cross_clock	Signal
maxigp0wdata	x393_dut
maxigp0wvalid	x393_dut
maxigp0wready	x393_dut
maxigp0wid	x393_dut
maxigp0wlast	x393_dut
maxigp0wstrb	x393_dut
maxigp0bvalid	x393_dut
maxigp0bready	x393_dut
maxigp0bid	x393_dut
maxigp0bresp	x393_dut
SIMUL_AXI_ADDR_W	x393_dut
SIMUL_AXI_MISMATCH	x393_dut
SIMUL_AXI_READ	x393_dut
SIMUL_AXI_ADDR	x393_dut
SIMUL_AXI_FULL	x393_dut
WAITING_STATUS	x393_dut
DEBUG1	x393_dut
DEBUG2	x393_dut
DEBUG3	x393_dut
AXI_TASK_HOLDdutm0_arid_w	x393_dut
AXI_TASK_HOLDdutm0_araddr_w	x393_dut
AXI_TASK_HOLDdutm0_arlen_w	x393_dut
AXI_TASK_HOLDdutm0_arsize_w	x393_dut
AXI_TASK_HOLDdutm0_arburst_w	x393_dut
AXI_TASK_HOLDdutm0_awid_w	x393_dut
AXI_TASK_HOLDdutm0_awaddr_w	x393_dut
AXI_TASK_HOLDdutm0_awlen_w	x393_dut
AXI_TASK_HOLDdutm0_awsize_w	x393_dut
AXI_TASK_HOLDdutm0_awburst_w	x393_dut
AXI_TASK_HOLDdutm0_wid_w	x393_dut
AXI_TASK_HOLDdutm0_wdata_w	x393_dut
AXI_TASK_HOLDdutm0_wstb_w	x393_dut
AXI_TASK_HOLDdutm0_wlast_w	x393_dut
AXI_TASK_HOLDdut_arvalid_w	x393_dut
AXI_TASK_HOLDdutm0_awvalid_w	x393_dut
ADDRESS_NUMBER	ddr3_wrap	Parameter
TRISTATE_DELAY_CLK	ddr3_wrap	Parameter
TRISTATE_DELAY	ddr3_wrap	Parameter
CLK_DELAY	ddr3_wrap	Parameter
AXI_TASK_HOLDdutm0_wvalid_w	x393_dut
CMDA_DELAY	ddr3_wrap	Parameter
DQS_IN_DELAY	ddr3_wrap	Parameter
DQ_IN_DELAY	ddr3_wrap	Parameter
DQS_OUT_DELAY	ddr3_wrap	Parameter
DQ_OUT_DELAY	ddr3_wrap	Parameter
mclk	ddr3_wrap	Input
dq_tri	ddr3_wrap	Input
dqs_tri	ddr3_wrap	Input
SDRST	ddr3_wrap	Input
SDCLK	ddr3_wrap	Input
SDNCLK	ddr3_wrap	Input
SDA	ddr3_wrap	Input
SDBA	ddr3_wrap	Input
SDWE	ddr3_wrap	Input
SDRAS	ddr3_wrap	Input
SDCAS	ddr3_wrap	Input
SDCKE	ddr3_wrap	Input
SDODT	ddr3_wrap	Input
SDD	ddr3_wrap	Inout
SDDML	ddr3_wrap	Input
DEPEND	x393_dut
DQSL	ddr3_wrap	Inout
NDQSL	ddr3_wrap	Inout
SDDMU	ddr3_wrap	Input
DQSU	ddr3_wrap	Inout
NDQSU	ddr3_wrap	Inout
CLK_DELAY_H	ddr3_wrap	Parameter
CMDA_DELAY_H	ddr3_wrap	Parameter
DQS_IN_DELAY_H	ddr3_wrap	Parameter
DQ_IN_DELAY_H	ddr3_wrap	Parameter
DQS_OUT_DELAY_H	ddr3_wrap	Parameter
HBLANK	x393_dut
DQ_OUT_DELAY_H	ddr3_wrap	Parameter
CLK_DELAY_HSDCLK_H1	ddr3_wrap	Signal
CLK_DELAY_HSDNCLK_H1	ddr3_wrap	Signal
CMDA_DELAY_HSDRST_H1	ddr3_wrap	Signal
CMDA_DELAY_HSDA_H1	ddr3_wrap	Signal
CMDA_DELAY_HSDBA_H1	ddr3_wrap	Signal
CMDA_DELAY_HSDWE_H1	ddr3_wrap	Signal
CMDA_DELAY_HSDRAS_H1	ddr3_wrap	Signal
CMDA_DELAY_HSDCAS_H1	ddr3_wrap	Signal
CMDA_DELAY_HSDCKE_H1	ddr3_wrap	Signal
BLANK_ROWS_BEFORE	x393_dut
CMDA_DELAY_HSDODT_H1	ddr3_wrap	Signal
CLK_DELAY_HSDCLK_H2	ddr3_wrap	Signal
CLK_DELAY_HSDNCLK_H2	ddr3_wrap	Signal
CMDA_DELAY_HSDRST_H2	ddr3_wrap	Signal
CMDA_DELAY_HSDA_H2	ddr3_wrap	Signal
CMDA_DELAY_HSDBA_H2	ddr3_wrap	Signal
CMDA_DELAY_HSDWE_H2	ddr3_wrap	Signal
CMDA_DELAY_HSDRAS_H2	ddr3_wrap	Signal
CMDA_DELAY_HSDCAS_H2	ddr3_wrap	Signal
CMDA_DELAY_HSDCKE_H2	ddr3_wrap	Signal
BLANK_ROWS_AFTER	x393_dut
CMDA_DELAY_HSDODT_H2	ddr3_wrap	Signal
CLK_DELAY_HSDCLK_H3	ddr3_wrap	Signal
CLK_DELAY_HSDNCLK_H3	ddr3_wrap	Signal
CMDA_DELAY_HSDRST_H3	ddr3_wrap	Signal
CMDA_DELAY_HSDA_H3	ddr3_wrap	Signal
CMDA_DELAY_HSDBA_H3	ddr3_wrap	Signal
CMDA_DELAY_HSDWE_H3	ddr3_wrap	Signal
CMDA_DELAY_HSDRAS_H3	ddr3_wrap	Signal
CMDA_DELAY_HSDCAS_H3	ddr3_wrap	Signal
CMDA_DELAY_HSDCKE_H3	ddr3_wrap	Signal
TRIG_LINES	x393_dut
CMDA_DELAY_HSDODT_H3	ddr3_wrap	Signal
CLK_DELAY_HSDCLK_D	ddr3_wrap	Signal
CLK_DELAY_HSDNCLK_D	ddr3_wrap	Signal
CMDA_DELAY_HSDRST_D	ddr3_wrap	Signal
CMDA_DELAY_HSDA_D	ddr3_wrap	Signal
CMDA_DELAY_HSDBA_D	ddr3_wrap	Signal
CMDA_DELAY_HSDWE_D	ddr3_wrap	Signal
CMDA_DELAY_HSDRAS_D	ddr3_wrap	Signal
CMDA_DELAY_HSDCAS_D	ddr3_wrap	Signal
CMDA_DELAY_HSDCKE_D	ddr3_wrap	Signal
VBLANK	x393_dut
CMDA_DELAY_HSDODT_D	ddr3_wrap	Signal
en_dq_dl	ddr3_wrap	Signal
en_dqs_dl	ddr3_wrap	Signal
TRISTATE_DELAYen_dq_d0	ddr3_wrap	Signal
TRISTATE_DELAYen_dqs_d0	ddr3_wrap	Signal
DQ_OUT_DELAY_Hen_dq_d1	ddr3_wrap	Signal
DQ_OUT_DELAY_Hen_dqs_d1	ddr3_wrap	Signal
DQ_OUT_DELAY_Hen_dq_d2	ddr3_wrap	Signal
DQ_OUT_DELAY_Hen_dqs_d2	ddr3_wrap	Signal
DQ_IN_DELAY_Hen_dq_d3	ddr3_wrap	Signal
CYCLES_PER_PIXEL	x393_dut
DQ_IN_DELAY_Hen_dqs_d3	ddr3_wrap	Signal
DQ_OUT_DELAY_Hen_dq_d4	ddr3_wrap	Signal
DQ_OUT_DELAY_Hen_dqs_d4	ddr3_wrap	Signal
DQ_OUT_DELAY_Hen_dq_d5	ddr3_wrap	Signal
DQ_OUT_DELAY_Hen_dqs_d5	ddr3_wrap	Signal
DQ_IN_DELAY_Hen_dq_d6	ddr3_wrap	Signal
DQ_IN_DELAY_Hen_dqs_d6	ddr3_wrap	Signal
DQ_IN_DELAY_Hen_dq_d7	ddr3_wrap	Signal
DQ_IN_DELAY_Hen_dqs_d7	ddr3_wrap	Signal
en_dq_out	ddr3_wrap	Signal
PF_HEIGHT	x393_dut
en_dqs_out	ddr3_wrap	Signal
en_dq_in	ddr3_wrap	Signal
en_dqs_in	ddr3_wrap	Signal
SDD_H1	ddr3_wrap	Signal
SDDML_H1	ddr3_wrap	Signal
SDDMU_H1	ddr3_wrap	Signal
DQSL_H1	ddr3_wrap	Signal
NDQSL_H1	ddr3_wrap	Signal
DQSU_H1	ddr3_wrap	Signal
NDQSU_H1	ddr3_wrap	Signal
FULL_HEIGHT	x393_dut
SDD_H2	ddr3_wrap	Signal
SDDML_H2	ddr3_wrap	Signal
SDDMU_H2	ddr3_wrap	Signal
DQSL_H2	ddr3_wrap	Signal
NDQSL_H2	ddr3_wrap	Signal
DQSU_H2	ddr3_wrap	Signal
NDQSU_H2	ddr3_wrap	Signal
SDD_H3	ddr3_wrap	Signal
SDDML_H3	ddr3_wrap	Signal
SDDMU_H3	ddr3_wrap	Signal
PF_STRIPES	x393_dut
DQSL_H3	ddr3_wrap	Signal
NDQSL_H3	ddr3_wrap	Signal
DQSU_H3	ddr3_wrap	Signal
NDQSU_H3	ddr3_wrap	Signal
SDD_D	ddr3_wrap	Signal
SDDML_D	ddr3_wrap	Signal
SDDMU_D	ddr3_wrap	Signal
DQSL_D	ddr3_wrap	Signal
NDQSL_D	ddr3_wrap	Signal
DQSU_D	ddr3_wrap	Signal
VIRTUAL_WIDTH	x393_dut
NDQSU_D	ddr3_wrap	Signal
SDD_DH1	ddr3_wrap	Signal
DQSL_DH1	ddr3_wrap	Signal
NDQSL_DH1	ddr3_wrap	Signal
DQSU_DH1	ddr3_wrap	Signal
NDQSU_DH1	ddr3_wrap	Signal
SDD_DH2	ddr3_wrap	Signal
DQSL_DH2	ddr3_wrap	Signal
NDQSL_DH2	ddr3_wrap	Signal
DQSU_DH2	ddr3_wrap	Signal
VIRTUAL_HEIGHT	x393_dut
NDQSU_DH2	ddr3_wrap	Signal
SDD_DH3	ddr3_wrap	Signal
DQSL_DH3	ddr3_wrap	Signal
NDQSL_DH3	ddr3_wrap	Signal
DQSU_DH3	ddr3_wrap	Signal
NDQSU_DH3	ddr3_wrap	Signal
TRIG_INTERFRAME	x393_dut
TRIG_DELAY	x393_dut
FULL_WIDTH	x393_dut
TEST_TITLE	x393_dut
PX1_MCLK	x393_dut
PX1_MRST	x393_dut
PX1_ARO	x393_dut
PX1_ARST	x393_dut
PX1_OFST	x393_dut
PX1_D	x393_dut
PX1_DCLK	x393_dut
PX1_HACT	x393_dut
PX1_VACT	x393_dut
PX2_MCLK	x393_dut
PX2_MRST	x393_dut
PX2_ARO	x393_dut
PX2_ARST	x393_dut
PX2_OFST	x393_dut
PX2_D	x393_dut
PX2_DCLK	x393_dut
PX2_HACT	x393_dut
PX2_VACT	x393_dut
PX3_MCLK	x393_dut
PX3_MRST	x393_dut
PX3_ARO	x393_dut
PX3_ARST	x393_dut
PX3_OFST	x393_dut
PX3_D	x393_dut
PX3_DCLK	x393_dut
PX3_HACT	x393_dut
PX3_VACT	x393_dut
PX4_MCLK	x393_dut
PX4_MRST	x393_dut
PX4_ARO	x393_dut
PX4_ARST	x393_dut
PX4_OFST	x393_dut
PX4_D	x393_dut
PX4_DCLK	x393_dut
PX4_HACT	x393_dut
PX4_VACT	x393_dut
PX1_MCLK_PRE	x393_dut
PX2_MCLK_PRE	x393_dut
PX3_MCLK_PRE	x393_dut
PX4_MCLK_PRE	x393_dut
sns1_dp	x393_dut
sns1_dn	x393_dut
sns1_clkp	x393_dut
sns1_clkn	x393_dut
sns1_scl	x393_dut
sns1_sda	x393_dut
sns1_ctl	x393_dut
sns1_pg	x393_dut
sns2_dp	x393_dut
sns2_dn	x393_dut
sns2_clkp	x393_dut
sns2_clkn	x393_dut
sns2_scl	x393_dut
sns2_sda	x393_dut
sns2_ctl	x393_dut
sns2_pg	x393_dut
sns3_dp	x393_dut
sns3_dn	x393_dut
sns3_clkp	x393_dut
sns3_clkn	x393_dut
sns3_scl	x393_dut
sns3_sda	x393_dut
sns3_ctl	x393_dut
sns3_pg	x393_dut
sns4_dp	x393_dut
sns4_dn	x393_dut
sns4_clkp	x393_dut
sns4_clkn	x393_dut
sns4_scl	x393_dut
sns4_sda	x393_dut
sns4_ctl	x393_dut
sns4_pg	x393_dut
PIX_CLK_DIV	x393_dut
PIX_CLK_MULT	x393_dut
HISPI_FULL_HEIGHT	x393_dut
HISPI_CLK_DIV	x393_dut
HISPI_CLK_MULT	x393_dut
HISPI_EMBED_LINES	x393_dut
HISPI_FIFO_LOGDEPTH	x393_dut
PX1_LANE_P	x393_dut
PX1_LANE_N	x393_dut
PX1_CLK_P	x393_dut
PX1_CLK_N	x393_dut
PX1_GP	x393_dut
PX1_FLASH	x393_dut
PX1_SHUTTER	x393_dut
PX2_LANE_P	x393_dut
PX2_LANE_N	x393_dut
sns1_dp	x393	Input
sns1_dn	x393	Input
sns1_dp74	x393	Inout
PX2_CLK_P	x393_dut
sns1_dn74	x393	Inout
sns1_clkp	x393	Input
sns1_clkn	x393	Input
sns1_scl	x393	Inout
sns1_sda	x393	Inout
sns1_ctl	x393	Inout
sns1_pg	x393	Inout
sns2_dp	x393	Input
sns2_dn	x393	Input
sns2_dp74	x393	Inout
PX2_CLK_N	x393_dut
sns2_dn74	x393	Inout
sns2_clkp	x393	Input
sns2_clkn	x393	Input
sns2_scl	x393	Inout
sns2_sda	x393	Inout
sns2_ctl	x393	Inout
sns2_pg	x393	Inout
sns3_dp	x393	Input
sns3_dn	x393	Input
sns3_dp74	x393	Inout
PX2_GP	x393_dut
sns3_dn74	x393	Inout
sns3_clkp	x393	Input
sns3_clkn	x393	Input
sns3_scl	x393	Inout
sns3_sda	x393	Inout
sns3_ctl	x393	Inout
sns3_pg	x393	Inout
sns4_dp	x393	Input
sns4_dn	x393	Input
sns4_dp74	x393	Inout
PX2_FLASH	x393_dut
sns4_dn74	x393	Inout
sns4_clkp	x393	Input
sns4_clkn	x393	Input
sns4_scl	x393	Inout
sns4_sda	x393	Inout
sns4_ctl	x393	Inout
sns4_pg	x393	Inout
gpio_pins	x393	Inout
SDRST	x393	Output
SDCLK	x393	Output
PX2_SHUTTER	x393_dut
SDNCLK	x393	Output
SDA	x393	Output
SDBA	x393	Output
SDWE	x393	Output
SDRAS	x393	Output
SDCAS	x393	Output
SDCKE	x393	Output
SDODT	x393	Output
SDD	x393	Inout
SDDML	x393	Output
PX3_LANE_P	x393_dut
DQSL	x393	Inout
NDQSL	x393	Inout
SDDMU	x393	Output
DQSU	x393	Inout
NDQSU	x393	Inout
memclk	x393	Input
ffclk0p	x393	Input
ffclk0n	x393	Input
ffclk1p	x393	Input
ffclk1n	x393	Input
PX3_LANE_N	x393_dut
RXN	x393	Input
RXP	x393	Input
TXN	x393	Output
TXP	x393	Output
EXTCLK_P	x393	Input
EXTCLK_N	x393	Input
fclk	x393	Signal
frst	x393	Signal
axi_aclk	x393	Signal
axi_grst	x393	Signal
PX3_CLK_P	x393_dut
maxi0_awaddr	x393	Signal
maxi0_awvalid	x393	Signal
maxi0_awready	x393	Signal
maxi0_awid	x393	Signal
maxi0_awlen	x393	Signal
maxi0_awsize	x393	Signal
maxi0_awburst	x393	Signal
maxi0_wdata	x393	Signal
maxi0_wvalid	x393	Signal
maxi0_wready	x393	Signal
PX3_CLK_N	x393_dut
maxi0_wid	x393	Signal
maxi0_wlast	x393	Signal
maxi0_wstb	x393	Signal
maxi0_bvalid	x393	Signal
maxi0_bready	x393	Signal
maxi0_bid	x393	Signal
maxi0_bresp	x393	Signal
axiwr_pre_awaddr	x393	Signal
axiwr_start_burst	x393	Signal
axiwr_dev_ready	x393	Signal
PX3_GP	x393_dut
axiwr_wclk	x393	Signal
axiwr_waddr	x393	Signal
axiwr_wen	x393	Signal
axiwr_bram_wstb	x393	Signal
axiwr_wdata	x393	Signal
maxi0_araddr	x393	Signal
maxi0_arvalid	x393	Signal
maxi0_arready	x393	Signal
maxi0_arid	x393	Signal
maxi0_arlen	x393	Signal
PX3_FLASH	x393_dut
maxi0_arsize	x393	Signal
maxi0_arburst	x393	Signal
maxi0_rdata	x393	Signal
maxi0_rvalid	x393	Signal
maxi0_rready	x393	Signal
maxi0_rid	x393	Signal
maxi0_rlast	x393	Signal
maxi0_rresp	x393	Signal
axird_pre_araddr	x393	Signal
axird_start_burst	x393	Signal
PX3_SHUTTER	x393_dut
axird_dev_ready	x393	Signal
axird_bram_rclk	x393	Signal
axird_raddr	x393	Signal
axird_ren	x393	Signal
axird_regen	x393	Signal
axird_rdata	x393	Signal
status_rdata	x393	Signal
status_selected	x393	Signal
readback_rdata	x393	Signal
readback_selected	x393	Signal
PX4_LANE_P	x393_dut
mcntrl_axird_rdata	x393	Signal
mcntrl_axird_selected	x393	Signal
status_selected_ren	x393	Signal
readback_selected_ren	x393	Signal
mcntrl_axird_selected_ren	x393	Signal
status_selected_regen	x393	Signal
readback_selected_regen	x393	Signal
mcntrl_axird_selected_regen	x393	Signal
mclk	x393	Signal
mcntrl_locked	x393	Signal
PX4_LANE_N	x393_dut
ref_clk	x393	Signal
hclk	x393	Signal
pclk	x393	Signal
xclk	x393	Signal
camsync_clk	x393	Signal
logger_clk	x393	Signal
mrst	x393	Signal
prst	x393	Signal
xrst	x393	Signal
crst	x393	Signal
PX4_CLK_P	x393_dut
lrst	x393	Signal
arst	x393	Signal
hrst	x393	Signal
locked_sync_clk	x393	Signal
locked_xclk	x393	Signal
locked_pclk	x393	Signal
locked_hclk	x393	Signal
idelay_ctrl_reset	x393	Signal
time_ref	x393	Signal
tmp_debug	x393	Signal
PX4_CLK_N	x393_dut
axiwr_dev_busy	x393	Signal
axird_dev_busy	x393	Signal
cseq_waddr	x393	Signal
cseq_wr_en	x393	Signal
cseq_wdata	x393	Signal
cseq_ackn	x393	Signal
frseq_waddr	x393	Signal
frseq_valid	x393	Signal
frseq_wdata	x393	Signal
frseq_ackn	x393	Signal
PX4_GP	x393_dut
frseq_is	x393	Signal
frseq_im	x393	Signal
frseq_irq	x393	Signal
par_waddr	x393	Signal
par_data	x393	Signal
cmd_root_ad	x393	Signal
cmd_root_stb	x393	Signal
status_root_ad	x393	Signal
status_root_rq	x393	Signal
status_root_start	x393	Signal
PX4_FLASH	x393_dut
status_mcontr_ad	x393	Signal
status_mcontr_rq	x393	Signal
status_mcontr_start	x393	Signal
status_membridge_ad	x393	Signal
status_membridge_rq	x393	Signal
status_membridge_start	x393	Signal
status_test01_ad	x393	Signal
status_test01_rq	x393	Signal
status_test01_start	x393	Signal
status_sensor_ad	x393	Signal
PX4_SHUTTER	x393_dut
status_sensor_rq	x393	Signal
status_sensor_start	x393	Signal
status_compressor_ad	x393	Signal
status_compressor_rq	x393	Signal
status_compressor_start	x393	Signal
status_sequencer_ad	x393	Signal
status_sequencer_rq	x393	Signal
status_sequencer_start	x393	Signal
status_logger_ad	x393	Signal
status_logger_rq	x393	Signal
gpio_pins	x393_dut
status_logger_start	x393	Signal
status_timing_ad	x393	Signal
status_timing_rq	x393	Signal
status_timing_start	x393	Signal
status_gpio_ad	x393	Signal
status_gpio_rq	x393	Signal
status_gpio_start	x393	Signal
status_saxi1wr_ad	x393	Signal
status_saxi1wr_rq	x393	Signal
status_saxi1wr_start	x393	Signal
SDRST	x393_dut
status_clocks_ad	x393	Signal
status_clocks_rq	x393	Signal
status_clocks_start	x393	Signal
status_debug_ad	x393	Signal
status_debug_rq	x393	Signal
status_debug_start	x393	Signal
DEBUG_RING_LENGTH	x393	Parameter
debug_ring	x393	Signal
debug_sl	x393	Signal
cmd_mcontr_ad	x393	Signal
SDCLK	x393_dut
cmd_mcontr_stb	x393	Signal
cmd_test01_ad	x393	Signal
cmd_test01_stb	x393	Signal
cmd_membridge_ad	x393	Signal
cmd_membridge_stb	x393	Signal
cmd_sensor_ad	x393	Signal
cmd_sensor_stb	x393	Signal
cmd_compressor_ad	x393	Signal
cmd_compressor_stb	x393	Signal
cmd_sequencer_ad	x393	Signal
SDNCLK	x393_dut
cmd_sequencer_stb	x393	Signal
cmd_logger_ad	x393	Signal
cmd_logger_stb	x393	Signal
cmd_timing_ad	x393	Signal
cmd_timing_stb	x393	Signal
cmd_gpio_ad	x393	Signal
cmd_gpio_stb	x393	Signal
cmd_saxi1wr_ad	x393	Signal
cmd_saxi1wr_stb	x393	Signal
cmd_clocks_ad	x393	Signal
SDA	x393_dut
cmd_clocks_stb	x393	Signal
cmd_debug_ad	x393	Signal
cmd_debug_stb	x393	Signal
frame_start_chn1	x393	Signal
next_page_chn1	x393	Signal
cmd_wrmem_chn1	x393	Signal
page_ready_chn1	x393	Signal
frame_done_chn1	x393	Signal
line_unfinished_chn1	x393	Signal
suspend_chn1	x393	Signal
SDBA	x393_dut
xfer_reset_page1_rd	x393	Signal
buf_wpage_nxt_chn1	x393	Signal
buf_wr_chn1	x393	Signal
buf_wdata_chn1	x393	Signal
xfer_reset_page1_wr	x393	Signal
rpage_nxt_chn1	x393	Signal
buf_rd_chn1	x393	Signal
buf_rdata_chn1	x393	Signal
frame_start_chn2	x393	Signal
next_page_chn2	x393	Signal
SDWE	x393_dut
page_ready_chn2	x393	Signal
frame_done_chn2	x393	Signal
line_unfinished_chn2	x393	Signal
suspend_chn2	x393	Signal
frame_start_chn3	x393	Signal
next_page_chn3	x393	Signal
page_ready_chn3	x393	Signal
frame_done_chn3	x393	Signal
line_unfinished_chn3	x393	Signal
suspend_chn3	x393	Signal
SDRAS	x393_dut
frame_start_chn4	x393	Signal
next_page_chn4	x393	Signal
page_ready_chn4	x393	Signal
frame_done_chn4	x393	Signal
line_unfinished_chn4	x393	Signal
suspend_chn4	x393	Signal
axi_rst_pre	x393	Signal
comb_rst	x393	Signal
gpio_in	x393	Signal
sens_rpage_set	x393	Signal
SDCAS	x393_dut
sens_frame_run	x393	Signal
sens_rpage_next	x393	Signal
sens_buf_rd	x393	Signal
sens_buf_dout	x393	Signal
sens_page_written	x393	Signal
sens_xfer_skipped	x393	Signal
sens_first_wr_in_frame	x393	Signal
trigger_mode	x393	Signal
trig_in	x393	Signal
sof_out_pclk	x393	Signal
SDCKE	x393_dut
eof_out_pclk	x393	Signal
sof_out_mclk	x393	Signal
sof_late_mclk	x393	Signal
frame_num	x393	Signal
frame_num_compressed	x393	Signal
cmprs_xfer_reset_page_rd	x393	Signal
cmprs_buf_wpage_nxt	x393	Signal
cmprs_buf_we	x393	Signal
cmprs_buf_din	x393	Signal
cmprs_page_ready	x393	Signal
SDODT	x393_dut
cmprs_next_page	x393	Signal
cmprs_frame_start_dst	x393	Signal
cmprs_line_unfinished_src	x393	Signal
cmprs_frame_number_src	x393	Signal
cmprs_frame_done_src	x393	Signal
cmprs_line_unfinished_dst	x393	Signal
cmprs_frame_number_dst	x393	Signal
cmprs_frame_done_dst	x393	Signal
cmprs_suspend	x393	Signal
cmprs_frame_number_finished	x393	Signal
SDD	x393_dut
ts_pre_stb	x393	Signal
ts_data	x393	Signal
ts_pre_logger_stb	x393	Signal
ts_logegr_data	x393	Signal
eof_written_mclk	x393	Signal
stuffer_done_mclk	x393	Signal
cmprs_irq	x393	Signal
gpio_rd	x393	Signal
gpio_camsync	x393	Signal
gpio_camsync_en	x393	Signal
SDDML	x393_dut
gpio_db	x393	Signal
gpio_db_en	x393	Signal
gpio_logger	x393	Signal
gpio_logger_en	x393	Signal
logger_snap	x393	Signal
logger_out	x393	Signal
logger_stb	x393	Signal
logger_saxi_en	x393	Signal
logger_has_burst	x393	Signal
logger_read_burst	x393	Signal
DQSL	x393_dut
logger_data32	x393	Signal
logger_pre_valid_chn	x393	Signal
idelay_ctrl_rdy	x393	Signal
maxi1_araddr	x393	Signal
maxi1_arvalid	x393	Signal
maxi1_arready	x393	Signal
maxi1_arid	x393	Signal
maxi1_arlen	x393	Signal
maxi1_arsize	x393	Signal
maxi1_arburst	x393	Signal
NDQSL	x393_dut
maxi1_rdata	x393	Signal
maxi1_rvalid	x393	Signal
maxi1_rready	x393	Signal
maxi1_rid	x393	Signal
maxi1_rlast	x393	Signal
maxi1_rresp	x393	Signal
maxi1_awaddr	x393	Signal
maxi1_awvalid	x393	Signal
maxi1_awready	x393	Signal
maxi1_awid	x393	Signal
SDDMU	x393_dut
maxi1_awlen	x393	Signal
maxi1_awsize	x393	Signal
maxi1_awburst	x393	Signal
maxi1_wdata	x393	Signal
maxi1_wvalid	x393	Signal
maxi1_wready	x393	Signal
maxi1_wid	x393	Signal
maxi1_wlast	x393	Signal
maxi1_wstb	x393	Signal
maxi1_bvalid	x393	Signal
DQSU	x393_dut
maxi1_bready	x393	Signal
maxi1_bid	x393	Signal
maxi1_bresp	x393	Signal
afi3_awaddr	x393	Signal
afi3_awvalid	x393	Signal
afi3_awready	x393	Signal
afi3_awid	x393	Signal
afi3_awlock	x393	Signal
afi3_awcache	x393	Signal
afi3_awprot	x393	Signal
NDQSU	x393_dut
afi3_awlen	x393	Signal
afi3_awsize	x393	Signal
afi3_awburst	x393	Signal
afi3_awqos	x393	Signal
afi3_wdata	x393	Signal
afi3_wvalid	x393	Signal
afi3_wready	x393	Signal
afi3_wid	x393	Signal
afi3_wlast	x393	Signal
afi3_wstrb	x393	Signal
memclk	x393_dut
afi3_bvalid	x393	Signal
afi3_bready	x393	Signal
afi3_bid	x393	Signal
afi3_bresp	x393	Signal
afi3_wcount	x393	Signal
afi3_wacount	x393	Signal
afi3_wrissuecap1en	x393	Signal
afi3_araddr	x393	Signal
afi3_arvalid	x393	Signal
afi3_arready	x393	Signal
ffclk0p	x393_dut
afi3_arid	x393	Signal
afi3_arlock	x393	Signal
afi3_arcache	x393	Signal
afi3_arprot	x393	Signal
afi3_arlen	x393	Signal
afi3_arsize	x393	Signal
afi3_arburst	x393	Signal
afi3_arqos	x393	Signal
afi3_rdata	x393	Signal
afi3_rvalid	x393	Signal
ffclk0n	x393_dut
afi3_rready	x393	Signal
afi3_rid	x393	Signal
afi3_rlast	x393	Signal
afi3_rresp	x393	Signal
afi3_rcount	x393	Signal
afi3_racount	x393	Signal
afi3_rdissuecap1en	x393	Signal
sata_irq	x393	Signal
sata_clk	x393	Signal
afi0_awaddr	x393	Signal
ffclk1p	x393_dut
afi0_awvalid	x393	Signal
afi0_awready	x393	Signal
afi0_awid	x393	Signal
afi0_awlock	x393	Signal
afi0_awcache	x393	Signal
afi0_awprot	x393	Signal
afi0_awlen	x393	Signal
afi0_awsize	x393	Signal
afi0_awburst	x393	Signal
afi0_awqos	x393	Signal
ffclk1n	x393_dut
afi0_wdata	x393	Signal
afi0_wvalid	x393	Signal
afi0_wready	x393	Signal
afi0_wid	x393	Signal
afi0_wlast	x393	Signal
afi0_wstrb	x393	Signal
afi0_bvalid	x393	Signal
afi0_bready	x393	Signal
afi0_bid	x393	Signal
afi0_bresp	x393	Signal
ps_reg_dout0w	x393_dut
afi0_wcount	x393	Signal
afi0_wacount	x393	Signal
afi0_wrissuecap1en	x393	Signal
afi0_araddr	x393	Signal
afi0_arvalid	x393	Signal
afi0_arready	x393	Signal
afi0_arid	x393	Signal
afi0_arlock	x393	Signal
afi0_arcache	x393	Signal
afi0_arprot	x393	Signal
ps_reg_dout0r	x393_dut
afi0_arlen	x393	Signal
afi0_arsize	x393	Signal
afi0_arburst	x393	Signal
afi0_arqos	x393	Signal
afi0_rdata	x393	Signal
afi0_rvalid	x393	Signal
afi0_rready	x393	Signal
afi0_rid	x393	Signal
afi0_rlast	x393	Signal
afi0_rresp	x393	Signal
ps_reg_dout1w	x393_dut
afi0_rcount	x393	Signal
afi0_racount	x393	Signal
afi0_rdissuecap1en	x393	Signal
saxi0_aclk	x393	Signal
saxi0_awaddr	x393	Signal
saxi0_awvalid	x393	Signal
saxi0_awready	x393	Signal
saxi0_awid	x393	Signal
saxi0_awlock	x393	Signal
saxi0_awcache	x393	Signal
ps_reg_dvalid0w	x393_dut
saxi0_awprot	x393	Signal
saxi0_awlen	x393	Signal
saxi0_awsize	x393	Signal
saxi0_awburst	x393	Signal
saxi0_awqos	x393	Signal
saxi0_wdata	x393	Signal
saxi0_wvalid	x393	Signal
saxi0_wready	x393	Signal
saxi0_wid	x393	Signal
saxi0_wlast	x393	Signal
ps_reg_dvalid0r	x393_dut
saxi0_wstrb	x393	Signal
saxi0_bvalid	x393	Signal
saxi0_bready	x393	Signal
saxi0_bid	x393	Signal
saxi0_bresp	x393	Signal
saxi1_aclk	x393	Signal
saxi1_awaddr	x393	Signal
saxi1_awvalid	x393	Signal
saxi1_awready	x393	Signal
saxi1_awid	x393	Signal
ps_reg_dvalid1w	x393_dut
saxi1_awlock	x393	Signal
saxi1_awcache	x393	Signal
saxi1_awprot	x393	Signal
saxi1_awlen	x393	Signal
saxi1_awsize	x393	Signal
saxi1_awburst	x393	Signal
saxi1_awqos	x393	Signal
saxi1_wdata	x393	Signal
saxi1_wvalid	x393	Signal
saxi1_wready	x393	Signal
CLK	x393_dut
saxi1_wid	x393	Signal
saxi1_wlast	x393	Signal
saxi1_wstrb	x393	Signal
saxi1_bvalid	x393	Signal
saxi1_bready	x393	Signal
saxi1_bid	x393	Signal
saxi1_bresp	x393	Signal
afi1_awaddr	x393	Signal
afi1_awvalid	x393	Signal
afi1_awready	x393	Signal
RST	x393_dut
afi1_awid	x393	Signal
afi1_awlock	x393	Signal
afi1_awcache	x393	Signal
afi1_awprot	x393	Signal
afi1_awlen	x393	Signal
afi1_awsize	x393	Signal
afi1_awburst	x393	Signal
afi1_awqos	x393	Signal
afi1_wdata	x393	Signal
afi1_wvalid	x393	Signal
WRAP_MCLK	x393_dut
afi1_wready	x393	Signal
afi1_wid	x393	Signal
afi1_wlast	x393	Signal
afi1_wstrb	x393	Signal
afi1_bvalid	x393	Signal
afi1_bready	x393	Signal
afi1_bid	x393	Signal
afi1_bresp	x393	Signal
afi1_wcount	x393	Signal
afi1_wacount	x393	Signal
WRAP_PHY_DQ_TRI	x393_dut
afi1_wrissuecap1en	x393	Signal
afi1_clk	x393	Signal
afi2_awaddr	x393	Signal
afi2_awvalid	x393	Signal
afi2_awready	x393	Signal
afi2_awid	x393	Signal
afi2_awlock	x393	Signal
afi2_awcache	x393	Signal
afi2_awprot	x393	Signal
afi2_awlen	x393	Signal
WRAP_PHY_DQS_TRI	x393_dut
afi2_awsize	x393	Signal
afi2_awburst	x393	Signal
afi2_awqos	x393	Signal
afi2_wdata	x393	Signal
afi2_wvalid	x393	Signal
afi2_wready	x393	Signal
afi2_wid	x393	Signal
afi2_wlast	x393	Signal
afi2_wstrb	x393	Signal
afi2_bvalid	x393	Signal
afi2_bready	x393	Signal
afi2_bid	x393	Signal
afi2_bresp	x393	Signal
afi2_wcount	x393	Signal
afi2_wacount	x393	Signal
afi2_wrissuecap1en	x393	Signal
FULL_HEIGHT	par12_hispi_psp4l	Parameter
CLOCK_MPY	par12_hispi_psp4l	Parameter
CLOCK_DIV	par12_hispi_psp4l	Parameter
LANE0_DLY	par12_hispi_psp4l	Parameter
LANE1_DLY	par12_hispi_psp4l	Parameter
LANE2_DLY	par12_hispi_psp4l	Parameter
LANE3_DLY	par12_hispi_psp4l	Parameter
CLK_DLY	par12_hispi_psp4l	Parameter
EMBED_LINES	par12_hispi_psp4l	Parameter
MSB_FIRST	par12_hispi_psp4l	Parameter
FIFO_LOGDEPTH	par12_hispi_psp4l	Parameter
pclk	par12_hispi_psp4l	Input
rst	par12_hispi_psp4l	Input
pxd	par12_hispi_psp4l	Input
vact	par12_hispi_psp4l	Input
hact_in	par12_hispi_psp4l	Input
lane_p	par12_hispi_psp4l	Output
lane_n	par12_hispi_psp4l	Output
clk_p	par12_hispi_psp4l	Output
clk_n	par12_hispi_psp4l	Output
FIFO_DEPTH	par12_hispi_psp4l	Parameter
SYNC_SOF	par12_hispi_psp4l	Parameter
SYNC_SOL	par12_hispi_psp4l	Parameter
SYNC_EOF	par12_hispi_psp4l	Parameter
SYNC_EOL	par12_hispi_psp4l	Parameter
lines_left	par12_hispi_psp4l	Signal
pre_lines	par12_hispi_psp4l	Signal
lane_pcntr	par12_hispi_psp4l	Signal
hact	par12_hispi_psp4l	Signal
image_lines	par12_hispi_psp4l	Signal
vact_d	par12_hispi_psp4l	Signal
pxd_d	par12_hispi_psp4l	Signal
fifo_di	par12_hispi_psp4l	Signal
fifo_we	par12_hispi_psp4l	Signal
hact_d	par12_hispi_psp4l	Signal
next_sof	par12_hispi_psp4l	Signal
next_line_pclk	par12_hispi_psp4l	Signal
next_frame_pclk	par12_hispi_psp4l	Signal
pre_fifo_we_eof_w	par12_hispi_psp4l	Signal
pre_fifo_we_sof_sol_w	par12_hispi_psp4l	Signal
pre_fifo_we_data_w	par12_hispi_psp4l	Signal
pre_fifo_we_w	par12_hispi_psp4l	Signal
fifo_ram	par12_hispi_psp4l	Signal
fifo_wa	par12_hispi_psp4l	Signal
oclk	par12_hispi_psp4l	Signal
next_line_oclk	par12_hispi_psp4l	Signal
next_frame_oclk	par12_hispi_psp4l	Signal
orst_r	par12_hispi_psp4l	Signal
orst	par12_hispi_psp4l	Signal
rdy	par12_hispi_psp4l	Signal
sdata	par12_hispi_psp4l	Signal
sdata_dly	par12_hispi_psp4l	Signal
fifo_ra	par12_hispi_psp4l	Signal
fifo_out	par12_hispi_psp4l	Signal
fifo_dav	par12_hispi_psp4l	Signal
sof_sol_sent	par12_hispi_psp4l	Signal
lines_available	par12_hispi_psp4l	Signal
line_available	par12_hispi_psp4l	Signal
frames_open	par12_hispi_psp4l	Signal
eof_sent	par12_hispi_psp4l	Signal
clk_pn	par12_hispi_psp4l	Signal
clk_pn_dly	par12_hispi_psp4l	Signal
DIVISOR	sim_clk_div	Parameter
clk_in	sim_clk_div	Input
en	sim_clk_div	Input
clk_out	sim_clk_div	Output
cntr	sim_clk_div	Signal
clk_out_r	sim_clk_div	Signal
simul_axi_master_wraddr.WIDTH	simul_axi_fifo	Parameter
simul_axi_master_wdata.WIDTH	simul_axi_fifo	Parameter
simul_axi_master_wraddr.LATENCY	simul_axi_fifo	Parameter
simul_axi_master_wdata.LATENCY	simul_axi_fifo	Parameter
simul_axi_master_wraddr.DEPTH	simul_axi_fifo	Parameter
simul_axi_master_wdata.DEPTH	simul_axi_fifo	Parameter
simul_axi_master_wraddr.FIFO_DEPTH	simul_axi_fifo	Parameter
simul_axi_master_wdata.FIFO_DEPTH	simul_axi_fifo	Parameter
simul_axi_master_wraddr.clk	simul_axi_fifo	Input
simul_axi_master_wdata.clk	simul_axi_fifo	Input
simul_axi_master_wraddr.reset	simul_axi_fifo	Input
simul_axi_master_wdata.reset	simul_axi_fifo	Input
simul_axi_master_wraddr.data_in	simul_axi_fifo	Input
simul_axi_master_wdata.data_in	simul_axi_fifo	Input
simul_axi_master_wraddr.load	simul_axi_fifo	Input
simul_axi_master_wdata.load	simul_axi_fifo	Input
simul_axi_master_wraddr.input_ready	simul_axi_fifo	Output
simul_axi_master_wdata.input_ready	simul_axi_fifo	Output
simul_axi_master_wraddr.data_out	simul_axi_fifo	Output
simul_axi_master_wdata.data_out	simul_axi_fifo	Output
simul_axi_master_wraddr.valid	simul_axi_fifo	Output
simul_axi_master_wdata.valid	simul_axi_fifo	Output
simul_axi_master_wraddr.ready	simul_axi_fifo	Input
simul_axi_master_wdata.ready	simul_axi_fifo	Input
simul_axi_master_wraddr.fifo	simul_axi_fifo	Signal
simul_axi_master_wdata.fifo	simul_axi_fifo	Signal
simul_axi_master_wraddr.in_address	simul_axi_fifo	Signal
simul_axi_master_wdata.in_address	simul_axi_fifo	Signal
simul_axi_master_wraddr.out_address	simul_axi_fifo	Signal
simul_axi_master_wdata.out_address	simul_axi_fifo	Signal
simul_axi_master_wraddr.in_count	simul_axi_fifo	Signal
simul_axi_master_wdata.in_count	simul_axi_fifo	Signal
simul_axi_master_wraddr.out_count	simul_axi_fifo	Signal
simul_axi_master_wdata.out_count	simul_axi_fifo	Signal
simul_axi_master_wraddr.latency_delay_r	simul_axi_fifo	Signal
simul_axi_master_wdata.latency_delay_r	simul_axi_fifo	Signal
simul_axi_master_wraddr.out_inc	simul_axi_fifo	Signal
simul_axi_master_wdata.out_inc	simul_axi_fifo	Signal
simul_axi_master_wraddr.input_ready_w	simul_axi_fifo	Signal
simul_axi_master_wdata.input_ready_w	simul_axi_fifo	Signal
simul_axi_master_wraddr.load_and_ready	simul_axi_fifo	Signal
simul_axi_master_wdata.load_and_ready	simul_axi_fifo	Signal
simul_axi_master_wraddr.latency_delay	simul_axi_fifo	Signal
simul_axi_master_wdata.latency_delay	simul_axi_fifo	Signal
HP_PORT	simul_axi_hp_rd	Parameter
rst	simul_axi_hp_rd	Input
aclk	simul_axi_hp_rd	Input
aresetn	simul_axi_hp_rd	Output
araddr	simul_axi_hp_rd	Input
arvalid	simul_axi_hp_rd	Input
arready	simul_axi_hp_rd	Output
arid	simul_axi_hp_rd	Input
arlock	simul_axi_hp_rd	Input
arcache	simul_axi_hp_rd	Input
arprot	simul_axi_hp_rd	Input
arlen	simul_axi_hp_rd	Input
arsize	simul_axi_hp_rd	Input
arburst	simul_axi_hp_rd	Input
arqos	simul_axi_hp_rd	Input
rdata	simul_axi_hp_rd	Output
rvalid	simul_axi_hp_rd	Output
rready	simul_axi_hp_rd	Input
rid	simul_axi_hp_rd	Output
rlast	simul_axi_hp_rd	Output
rresp	simul_axi_hp_rd	Output
rcount	simul_axi_hp_rd	Output
racount	simul_axi_hp_rd	Output
rdissuecap1en	simul_axi_hp_rd	Input
sim_rd_address	simul_axi_hp_rd	Output
sim_rid	simul_axi_hp_rd	Output
sim_rd_valid	simul_axi_hp_rd	Input
sim_rd_ready	simul_axi_hp_rd	Output
sim_rd_data	simul_axi_hp_rd	Input
sim_rd_cap	simul_axi_hp_rd	Output
sim_rd_qos	simul_axi_hp_rd	Output
sim_rd_resp	simul_axi_hp_rd	Input
reg_addr	simul_axi_hp_rd	Input
reg_wr	simul_axi_hp_rd	Input
reg_rd	simul_axi_hp_rd	Input
reg_din	simul_axi_hp_rd	Input
reg_dout	simul_axi_hp_rd	Output
reg_dvalid	simul_axi_hp_rd	Output
AFI_BASECTRL	simul_axi_hp_rd	Parameter
AFI_RDCHAN_CTRL	simul_axi_hp_rd	Parameter
AFI_RDCHAN_ISSUINGCAP	simul_axi_hp_rd	Parameter
AFI_RDQOS	simul_axi_hp_rd	Parameter
AFI_RDDATAFIFO_LEVEL	simul_axi_hp_rd	Parameter
AFI_RDDEBUG	simul_axi_hp_rd	Parameter
VALID_ARLOCK	simul_axi_hp_rd	Parameter
VALID_ARCACHE	simul_axi_hp_rd	Parameter
VALID_ARPROT	simul_axi_hp_rd	Parameter
VALID_ARLOCK_MASK	simul_axi_hp_rd	Parameter
VALID_ARCACHE_MASK	simul_axi_hp_rd	Parameter
VALID_ARPROT_MASK	simul_axi_hp_rd	Parameter
rdQosHeadOfCmdQEn	simul_axi_hp_rd	Signal
rdFabricOutCmdEn	simul_axi_hp_rd	Signal
rdFabricQosEn	simul_axi_hp_rd	Signal
rd32BitEn	simul_axi_hp_rd	Signal
rdIssueCap1	simul_axi_hp_rd	Signal
rdIssueCap0	simul_axi_hp_rd	Signal
rdStaticQos	simul_axi_hp_rd	Signal
rd_qos_in	simul_axi_hp_rd	Signal
rd_qos_out	simul_axi_hp_rd	Signal
arid_out	simul_axi_hp_rd	Signal
arburst_out	simul_axi_hp_rd	Signal
arsize_out	simul_axi_hp_rd	Signal
arlen_out	simul_axi_hp_rd	Signal
araddr_out	simul_axi_hp_rd	Signal
ar_nempty	simul_axi_hp_rd	Signal
r_nempty	simul_axi_hp_rd	Signal
fifo_with_requested	simul_axi_hp_rd	Signal
fifo_data_rd	simul_axi_hp_rd	Signal
next_with_requested	simul_axi_hp_rd	Signal
start_read_burst_w	simul_axi_hp_rd	Signal
was_data_fifo_read	simul_axi_hp_rd	Signal
was_data_fifo_write	simul_axi_hp_rd	Signal
was_addr_fifo_write	simul_axi_hp_rd	Signal
read_in_progress_w	simul_axi_hp_rd	Signal
read_in_progress	simul_axi_hp_rd	Signal
read_left	simul_axi_hp_rd	Signal
rburst	simul_axi_hp_rd	Signal
rlen	simul_axi_hp_rd	Signal
next_rd_address	simul_axi_hp_rd	Signal
read_address	simul_axi_hp_rd	Signal
last_confirmed_read	simul_axi_hp_rd	Signal
last_read	simul_axi_hp_rd	Signal
HP_PORT	simul_axi_hp_wr	Parameter
rst	simul_axi_hp_wr	Input
aclk	simul_axi_hp_wr	Input
aresetn	simul_axi_hp_wr	Output
awaddr	simul_axi_hp_wr	Input
awvalid	simul_axi_hp_wr	Input
awready	simul_axi_hp_wr	Output
awid	simul_axi_hp_wr	Input
awlock	simul_axi_hp_wr	Input
awcache	simul_axi_hp_wr	Input
awprot	simul_axi_hp_wr	Input
awlen	simul_axi_hp_wr	Input
awsize	simul_axi_hp_wr	Input
awburst	simul_axi_hp_wr	Input
awqos	simul_axi_hp_wr	Input
wdata	simul_axi_hp_wr	Input
wvalid	simul_axi_hp_wr	Input
wready	simul_axi_hp_wr	Output
wid	simul_axi_hp_wr	Input
wlast	simul_axi_hp_wr	Input
wstrb	simul_axi_hp_wr	Input
bvalid	simul_axi_hp_wr	Output
bready	simul_axi_hp_wr	Input
bid	simul_axi_hp_wr	Output
bresp	simul_axi_hp_wr	Output
wcount	simul_axi_hp_wr	Output
wacount	simul_axi_hp_wr	Output
wrissuecap1en	simul_axi_hp_wr	Input
sim_wr_address	simul_axi_hp_wr	Output
sim_wid	simul_axi_hp_wr	Output
sim_wr_valid	simul_axi_hp_wr	Output
sim_wr_ready	simul_axi_hp_wr	Input
sim_wr_data	simul_axi_hp_wr	Output
sim_wr_stb	simul_axi_hp_wr	Output
sim_bresp_latency	simul_axi_hp_wr	Input
sim_wr_cap	simul_axi_hp_wr	Output
sim_wr_qos	simul_axi_hp_wr	Output
reg_addr	simul_axi_hp_wr	Input
reg_wr	simul_axi_hp_wr	Input
reg_rd	simul_axi_hp_wr	Input
reg_din	simul_axi_hp_wr	Input
reg_dout	simul_axi_hp_wr	Output
reg_dvalid	simul_axi_hp_wr	Output
AFI_BASECTRL	simul_axi_hp_wr	Parameter
AFI_WRCHAN_CTRL	simul_axi_hp_wr	Parameter
AFI_WRCHAN_ISSUINGCAP	simul_axi_hp_wr	Parameter
AFI_WRQOS	simul_axi_hp_wr	Parameter
AFI_WRDATAFIFO_LEVEL	simul_axi_hp_wr	Parameter
AFI_WRDEBUG	simul_axi_hp_wr	Parameter
VALID_AWLOCK	simul_axi_hp_wr	Parameter
VALID_AWCACHE	simul_axi_hp_wr	Parameter
VALID_AWPROT	simul_axi_hp_wr	Parameter
VALID_AWLOCK_MASK	simul_axi_hp_wr	Parameter
VALID_AWCACHE_MASK	simul_axi_hp_wr	Parameter
VALID_AWPROT_MASK	simul_axi_hp_wr	Parameter
WrDataThreshold	simul_axi_hp_wr	Signal
WrCmdReleaseMode	simul_axi_hp_wr	Signal
wrQosHeadOfCmdQEn	simul_axi_hp_wr	Signal
wrFabricOutCmdEn	simul_axi_hp_wr	Signal
wrFabricQosEn	simul_axi_hp_wr	Signal
wr32BitEn	simul_axi_hp_wr	Signal
wrIssueCap1	simul_axi_hp_wr	Signal
wrIssueCap0	simul_axi_hp_wr	Signal
staticQos	simul_axi_hp_wr	Signal
wr_qos_in	simul_axi_hp_wr	Signal
wr_qos_out	simul_axi_hp_wr	Signal
aw_nempty	simul_axi_hp_wr	Signal
w_nempty	simul_axi_hp_wr	Signal
enough_data	simul_axi_hp_wr	Signal
next_wr_address	simul_axi_hp_wr	Signal
write_address	simul_axi_hp_wr	Signal
awid_r	simul_axi_hp_wr	Signal
fifo_wd_rd	simul_axi_hp_wr	Signal
last_confirmed_write	simul_axi_hp_wr	Signal
awid_out	simul_axi_hp_wr	Signal
awburst_out	simul_axi_hp_wr	Signal
awsize_out	simul_axi_hp_wr	Signal
awlen_out	simul_axi_hp_wr	Signal
awaddr_out	simul_axi_hp_wr	Signal
wid_out	simul_axi_hp_wr	Signal
wlast_out	simul_axi_hp_wr	Signal
wstrb_out	simul_axi_hp_wr	Signal
wdata_out	simul_axi_hp_wr	Signal
fifo_data_we_d	simul_axi_hp_wr	Signal
fifo_addr_we_d	simul_axi_hp_wr	Signal
write_left	simul_axi_hp_wr	Signal
wburst	simul_axi_hp_wr	Signal
wlen	simul_axi_hp_wr	Signal
start_write_burst_w	simul_axi_hp_wr	Signal
start_write_burst_r	simul_axi_hp_wr	Signal
write_in_progress_w	simul_axi_hp_wr	Signal
write_in_progress	simul_axi_hp_wr	Signal
wresp_num_in_fifo	simul_axi_hp_wr	Signal
was_wresp_re	simul_axi_hp_wr	Signal
wresp_re	simul_axi_hp_wr	Signal
num_full_data	simul_axi_hp_wr	Signal
inc_num_full_data	simul_axi_hp_wr	Signal
bresp_value	simul_axi_hp_wr	Signal
bresp_in	simul_axi_hp_wr	Signal
fifo_wd_rd_dly	simul_axi_hp_wr	Signal
bid_in	simul_axi_hp_wr	Signal
ID_WIDTH	simul_axi_master_rdaddr	Parameter
ADDRESS_WIDTH	simul_axi_master_rdaddr	Parameter
LATENCY	simul_axi_master_rdaddr	Parameter
DEPTH	simul_axi_master_rdaddr	Parameter
DATA_DELAY	simul_axi_master_rdaddr	Parameter
VALID_DELAY	simul_axi_master_rdaddr	Parameter
clk	simul_axi_master_rdaddr	Input
reset	simul_axi_master_rdaddr	Input
arid_in	simul_axi_master_rdaddr	Input
araddr_in	simul_axi_master_rdaddr	Input
arlen_in	simul_axi_master_rdaddr	Input
arsize_in	simul_axi_master_rdaddr	Input
arburst_in	simul_axi_master_rdaddr	Input
arcache_in	simul_axi_master_rdaddr	Input
arprot_in	simul_axi_master_rdaddr	Input
arid	simul_axi_master_rdaddr	Output
araddr	simul_axi_master_rdaddr	Output
arlen	simul_axi_master_rdaddr	Output
arsize	simul_axi_master_rdaddr	Output
arburst	simul_axi_master_rdaddr	Output
arcache	simul_axi_master_rdaddr	Output
arprot	simul_axi_master_rdaddr	Output
arvalid	simul_axi_master_rdaddr	Output
arready	simul_axi_master_rdaddr	Input
set_cmd	simul_axi_master_rdaddr	Input
ready	simul_axi_master_rdaddr	Output
arid_out	simul_axi_master_rdaddr	Signal
araddr_out	simul_axi_master_rdaddr	Signal
arlen_out	simul_axi_master_rdaddr	Signal
arsize_out	simul_axi_master_rdaddr	Signal
arburst_out	simul_axi_master_rdaddr	Signal
arcache_out	simul_axi_master_rdaddr	Signal
arprot_out	simul_axi_master_rdaddr	Signal
arvalid_out	simul_axi_master_rdaddr	Signal
ID_WIDTH	simul_axi_master_wdata	Parameter
DATA_WIDTH	simul_axi_master_wdata	Parameter
WSTB_WIDTH	simul_axi_master_wdata	Parameter
LATENCY	simul_axi_master_wdata	Parameter
DEPTH	simul_axi_master_wdata	Parameter
DATA_DELAY	simul_axi_master_wdata	Parameter
VALID_DELAY	simul_axi_master_wdata	Parameter
clk	simul_axi_master_wdata	Input
reset	simul_axi_master_wdata	Input
wid_in	simul_axi_master_wdata	Input
wdata_in	simul_axi_master_wdata	Input
wstrb_in	simul_axi_master_wdata	Input
wlast_in	simul_axi_master_wdata	Input
wid	simul_axi_master_wdata	Output
wdata	simul_axi_master_wdata	Output
wstrb	simul_axi_master_wdata	Output
wlast	simul_axi_master_wdata	Output
wvalid	simul_axi_master_wdata	Output
wready	simul_axi_master_wdata	Input
set_cmd	simul_axi_master_wdata	Input
ready	simul_axi_master_wdata	Output
wid_out	simul_axi_master_wdata	Signal
wdata_out	simul_axi_master_wdata	Signal
wstrb_out	simul_axi_master_wdata	Signal
wlast_out	simul_axi_master_wdata	Signal
wvalid_out	simul_axi_master_wdata	Signal
ID_WIDTH	simul_axi_master_wraddr	Parameter
ADDRESS_WIDTH	simul_axi_master_wraddr	Parameter
LATENCY	simul_axi_master_wraddr	Parameter
DEPTH	simul_axi_master_wraddr	Parameter
DATA_DELAY	simul_axi_master_wraddr	Parameter
VALID_DELAY	simul_axi_master_wraddr	Parameter
clk	simul_axi_master_wraddr	Input
reset	simul_axi_master_wraddr	Input
awid_in	simul_axi_master_wraddr	Input
awaddr_in	simul_axi_master_wraddr	Input
awlen_in	simul_axi_master_wraddr	Input
awsize_in	simul_axi_master_wraddr	Input
awburst_in	simul_axi_master_wraddr	Input
awcache_in	simul_axi_master_wraddr	Input
awprot_in	simul_axi_master_wraddr	Input
awid	simul_axi_master_wraddr	Output
awaddr	simul_axi_master_wraddr	Output
awlen	simul_axi_master_wraddr	Output
awsize	simul_axi_master_wraddr	Output
awburst	simul_axi_master_wraddr	Output
awcache	simul_axi_master_wraddr	Output
awprot	simul_axi_master_wraddr	Output
awvalid	simul_axi_master_wraddr	Output
awready	simul_axi_master_wraddr	Input
set_cmd	simul_axi_master_wraddr	Input
ready	simul_axi_master_wraddr	Output
awid_out	simul_axi_master_wraddr	Signal
awaddr_out	simul_axi_master_wraddr	Signal
awlen_out	simul_axi_master_wraddr	Signal
awsize_out	simul_axi_master_wraddr	Signal
awburst_out	simul_axi_master_wraddr	Signal
awcache_out	simul_axi_master_wraddr	Signal
awprot_out	simul_axi_master_wraddr	Signal
awvalid_out	simul_axi_master_wraddr	Signal
ADDRESS_WIDTH	simul_axi_read	Parameter
clk	simul_axi_read	Input
reset	simul_axi_read	Input
last	simul_axi_read	Input
data_stb	simul_axi_read	Input
raddr	simul_axi_read	Input
rlen	simul_axi_read	Input
rcmd	simul_axi_read	Input
addr_out	simul_axi_read	Output
burst	simul_axi_read	Output
err_out	simul_axi_read	Output
raddr_fifo	simul_axi_read	Signal
rlen_fifo	simul_axi_read	Signal
fifo_valid	simul_axi_read	Signal
burst_r	simul_axi_read	Signal
left_plus_1	simul_axi_read	Signal
start_burst	simul_axi_read	Signal
generated_last	simul_axi_read	Signal
fifo_in_rdy	simul_axi_read	Signal
error_w	simul_axi_read	Signal
adr_out_r	simul_axi_read	Signal
clk	simul_axi_slow_ready	Input
reset	simul_axi_slow_ready	Input
delay	simul_axi_slow_ready	Input
valid	simul_axi_slow_ready	Input
ready	simul_axi_slow_ready	Output
rdy_reg	simul_axi_slow_ready	Signal
CLKIN_PERIOD	simul_clk	Parameter
MEMCLK_PERIOD	simul_clk	Parameter
FCLK0_PERIOD	simul_clk	Parameter
FCLK1_PERIOD	simul_clk	Parameter
rst	simul_clk	Input
clk	simul_clk	Output
memclk	simul_clk	Output
ffclk0	simul_clk	Output
ffclk1	simul_clk	Output
ffclk0_w	simul_clk	Signal
ffclk1_w	simul_clk	Signal
MULTIPLIER	simul_clk_mult	Parameter
SKIP_FIRST	simul_clk_mult	Parameter
clk_in	simul_clk_mult	Input
en	simul_clk_mult	Input
clk_out	simul_clk_mult	Output
phase	simul_clk_mult	Signal
prev_phase	simul_clk_mult	Signal
out_half_period	simul_clk_mult	Signal
num_period	simul_clk_mult	Signal
en1	simul_clk_mult	Signal
clk_out_r	simul_clk_mult	Signal
MULTIPLIER	simul_clk_mult_div	Parameter
DIVISOR	simul_clk_mult_div	Parameter
SKIP_FIRST	simul_clk_mult_div	Parameter
clk_in	simul_clk_mult_div	Input
en	simul_clk_mult_div	Input
clk_out	simul_clk_mult_div	Output
clk_int	simul_clk_mult_div	Signal
rst	simul_saxi_gp_wr	Input
aclk	simul_saxi_gp_wr	Input
aresetn	simul_saxi_gp_wr	Output
awaddr	simul_saxi_gp_wr	Input
awvalid	simul_saxi_gp_wr	Input
awready	simul_saxi_gp_wr	Output
awid	simul_saxi_gp_wr	Input
awlock	simul_saxi_gp_wr	Input
awcache	simul_saxi_gp_wr	Input
awprot	simul_saxi_gp_wr	Input
awlen	simul_saxi_gp_wr	Input
awsize	simul_saxi_gp_wr	Input
awburst	simul_saxi_gp_wr	Input
awqos	simul_saxi_gp_wr	Input
wdata	simul_saxi_gp_wr	Input
wvalid	simul_saxi_gp_wr	Input
wready	simul_saxi_gp_wr	Output
wid	simul_saxi_gp_wr	Input
wlast	simul_saxi_gp_wr	Input
wstrb	simul_saxi_gp_wr	Input
bvalid	simul_saxi_gp_wr	Output
bready	simul_saxi_gp_wr	Input
bid	simul_saxi_gp_wr	Output
bresp	simul_saxi_gp_wr	Output
sim_wr_address	simul_saxi_gp_wr	Output
sim_wid	simul_saxi_gp_wr	Output
sim_wr_valid	simul_saxi_gp_wr	Output
sim_wr_ready	simul_saxi_gp_wr	Input
sim_wr_data	simul_saxi_gp_wr	Output
sim_wr_stb	simul_saxi_gp_wr	Output
sim_wr_size	simul_saxi_gp_wr	Output
sim_bresp_latency	simul_saxi_gp_wr	Input
sim_wr_qos	simul_saxi_gp_wr	Output
AW_FIFO_DEPTH	simul_saxi_gp_wr	Parameter
W_FIFO_DEPTH	simul_saxi_gp_wr	Parameter
AW_FIFO_NUM	simul_saxi_gp_wr	Parameter
W_FIFO_NUM	simul_saxi_gp_wr	Parameter
VALID_AWLOCK	simul_saxi_gp_wr	Parameter
VALID_AWCACHE	simul_saxi_gp_wr	Parameter
VALID_AWPROT	simul_saxi_gp_wr	Parameter
VALID_AWLOCK_MASK	simul_saxi_gp_wr	Parameter
VALID_AWCACHE_MASK	simul_saxi_gp_wr	Parameter
VALID_AWPROT_MASK	simul_saxi_gp_wr	Parameter
aw_nempty	simul_saxi_gp_wr	Signal
w_nempty	simul_saxi_gp_wr	Signal
next_wr_address_w	simul_saxi_gp_wr	Signal
write_address	simul_saxi_gp_wr	Signal
fifo_wd_rd	simul_saxi_gp_wr	Signal
last_confirmed_write	simul_saxi_gp_wr	Signal
awid_out	simul_saxi_gp_wr	Signal
awburst_out	simul_saxi_gp_wr	Signal
awsize_out	simul_saxi_gp_wr	Signal
awlen_out	simul_saxi_gp_wr	Signal
awaddr_out	simul_saxi_gp_wr	Signal
wid_out	simul_saxi_gp_wr	Signal
wlast_out	simul_saxi_gp_wr	Signal
wstrb_out	simul_saxi_gp_wr	Signal
wdata_out	simul_saxi_gp_wr	Signal
fifo_data_we_d	simul_saxi_gp_wr	Signal
fifo_addr_we_d	simul_saxi_gp_wr	Signal
write_left	simul_saxi_gp_wr	Signal
wburst	simul_saxi_gp_wr	Signal
wlen	simul_saxi_gp_wr	Signal
wsize	simul_saxi_gp_wr	Signal
start_write_burst_w	simul_saxi_gp_wr	Signal
write_in_progress_w	simul_saxi_gp_wr	Signal
write_in_progress	simul_saxi_gp_wr	Signal
num_full_data	simul_saxi_gp_wr	Signal
wresp_num_in_fifo	simul_saxi_gp_wr	Signal
was_wresp_re	simul_saxi_gp_wr	Signal
wresp_re	simul_saxi_gp_wr	Signal
wacount	simul_saxi_gp_wr	Signal
wcount	simul_saxi_gp_wr	Signal
sim_wr_mask	simul_saxi_gp_wr	Signal
bresp_value	simul_saxi_gp_wr	Signal
bresp_in	simul_saxi_gp_wr	Signal
fifo_wd_rd_dly	simul_saxi_gp_wr	Signal
bid_in	simul_saxi_gp_wr	Signal
SENSOR_IMAGE_TYPE	simul_sensor12bits	Parameter
lline	simul_sensor12bits	Parameter
ncols	simul_sensor12bits	Parameter
nrows	simul_sensor12bits	Parameter
nrowb	simul_sensor12bits	Parameter
nrowa	simul_sensor12bits	Parameter
nbpf	simul_sensor12bits	Parameter
ngp1	simul_sensor12bits	Parameter
nVLO	simul_sensor12bits	Parameter
tMD	simul_sensor12bits	Parameter
tDDO	simul_sensor12bits	Parameter
tDDO1	simul_sensor12bits	Parameter
trigdly	simul_sensor12bits	Parameter
ramp	simul_sensor12bits	Parameter
new_bayer	simul_sensor12bits	Parameter
MCLK	simul_sensor12bits	Input
MRST	simul_sensor12bits	Input
ARO	simul_sensor12bits	Input
ARST	simul_sensor12bits	Input
OE	simul_sensor12bits	Input
SCL	simul_sensor12bits	Input
SDA	simul_sensor12bits	Inout
OFST	simul_sensor12bits	Input
D	simul_sensor12bits	Output
DCLK	simul_sensor12bits	Output
BPF	simul_sensor12bits	Output
HACT	simul_sensor12bits	Output
VACT	simul_sensor12bits	Output
VACT1	simul_sensor12bits	Output
s_stop	simul_sensor12bits	Parameter
s_preVACT	simul_sensor12bits	Parameter
s_firstline	simul_sensor12bits	Parameter
s_BPF	simul_sensor12bits	Parameter
s_preHACT	simul_sensor12bits	Parameter
s_HACT	simul_sensor12bits	Parameter
s_afterHACT	simul_sensor12bits	Parameter
s_lastline	simul_sensor12bits	Parameter
s_frame_done	simul_sensor12bits	Parameter
t_preVACT	simul_sensor12bits	Parameter
t_firstline	simul_sensor12bits	Parameter
t_BPF	simul_sensor12bits	Parameter
t_preHACT	simul_sensor12bits	Parameter
t_HACT	simul_sensor12bits	Parameter
t_afterHACT	simul_sensor12bits	Parameter
t_lastline	simul_sensor12bits	Parameter
sensor_data	simul_sensor12bits	Signal
c	simul_sensor12bits	Signal
stopped	simul_sensor12bits	Signal
stoppedd	simul_sensor12bits	Signal
ibpf	simul_sensor12bits	Signal
ihact	simul_sensor12bits	Signal
ivact	simul_sensor12bits	Signal
ivact1	simul_sensor12bits	Signal
arst1	simul_sensor12bits	Signal
col	simul_sensor12bits	Signal
row	simul_sensor12bits	Signal
state	simul_sensor12bits	Signal
cntr	simul_sensor12bits	Signal
cold	simul_sensor12bits	Signal
rowd	simul_sensor12bits	Signal
stated	simul_sensor12bits	Signal
cntrd	simul_sensor12bits	Signal
NMRST	simul_sensor12bits	Signal
row_index	simul_sensor12bits	Signal
col_index	simul_sensor12bits	Signal
seed	simul_sensor12bits	Signal
r	simul_sensor12bits	Signal
c_rand	simul_sensor12bits	Signal
d_rand	simul_sensor12bits	Signal
dutm0_aclk	x393_dut
reset_out	x393_dut
dutm0_araddr	x393_dut
dutm0_arready	x393_dut
dutm0_arvalid	x393_dut
dutm0_arid	x393_dut
dutm0_arlock	x393_dut
dutm0_arcache	x393_dut
dutm0_arprot	x393_dut
dutm0_arlen	x393_dut
dutm0_arsize	x393_dut
dutm0_arburst	x393_dut
dutm0_arqos	x393_dut
dutm0_rdata	x393_dut
dutm0_rvalid	x393_dut
dutm0_rready	x393_dut
dutm0_rid	x393_dut
dutm0_rlast	x393_dut
dutm0_rresp	x393_dut
dutm0_awaddr	x393_dut
dutm0_awvalid	x393_dut
dutm0_awready	x393_dut
dutm0_awid	x393_dut
dutm0_awlock	x393_dut
dutm0_awcache	x393_dut
dutm0_awprot	x393_dut
dutm0_awlen	x393_dut
dutm0_awsize	x393_dut
dutm0_awburst	x393_dut
dutm0_awqos	x393_dut
dutm0_wdata	x393_dut
dutm0_wvalid	x393_dut
dutm0_wready	x393_dut
dutm0_wid	x393_dut
dutm0_wlast	x393_dut
dutm0_wstb	x393_dut
dutm0_bvalid	x393_dut
dutm0_bready	x393_dut
dutm0_bid	x393_dut
dutm0_bresp	x393_dut
ps_sbus_clk	x393_dut
ps_sbus_addr	x393_dut
ps_sbus_wr	x393_dut
ps_sbus_rd	x393_dut
ps_sbus_din	x393_dut
ps_sbus_dout	x393_dut
axi_hclk	x393_dut
saxi0_aclk	x393_dut
saxihp0_wr_address	x393_dut
ALWAYS_398 pclk	par12_hispi_psp4l	Always Construct
ALWAYS_399 pclk	par12_hispi_psp4l	Always Construct
ALWAYS_400 pclk	par12_hispi_psp4l	Always Construct
ALWAYS_401 oclk	par12_hispi_psp4l	Always Construct
ALWAYS_402 oclk	par12_hispi_psp4l	Always Construct
ALWAYS_403 oclk	par12_hispi_psp4l	Always Construct
ALWAYS_405 clk_in	sim_clk_div	Always Construct
simul_axi_master_wraddr.ALWAYS_410 clk or reset	simul_axi_fifo	Always Construct
simul_axi_master_wdata.ALWAYS_410 clk or reset	simul_axi_fifo	Always Construct
simul_axi_master_wraddr.ALWAYS_411 clk	simul_axi_fifo	Always Construct
simul_axi_master_wdata.ALWAYS_411 clk	simul_axi_fifo	Always Construct
ALWAYS_412 aclk or rst	simul_axi_hp_rd	Always Construct
ALWAYS_413 aclk	simul_axi_hp_rd	Always Construct
ALWAYS_414 aclk or rst	simul_axi_hp_rd	Always Construct
ALWAYS_415 aclk or rst	simul_axi_hp_wr	Always Construct
ALWAYS_416 rst or aclk	simul_axi_hp_wr	Always Construct
ALWAYS_417 rst or aclk	simul_axi_hp_wr	Always Construct
ALWAYS_418 rst or aclk	simul_axi_hp_wr	Always Construct
ALWAYS_419 aclk	simul_axi_hp_wr	Always Construct
ALWAYS_420 aclk or rst	simul_axi_hp_wr	Always Construct
ALWAYS_421 rst or aclk	simul_axi_hp_wr	Always Construct
ALWAYS_422 reset or clk	simul_axi_read	Always Construct
ALWAYS_423 clk	simul_axi_read	Always Construct
ALWAYS_424 clk or reset	simul_axi_slow_ready	Always Construct
ALWAYS_425 clk_in	simul_clk_mult	Always Construct
ALWAYS_426 clk_in	simul_clk_mult	Always Construct
ALWAYS_429 rst or aclk	simul_saxi_gp_wr	Always Construct
ALWAYS_430 rst or aclk	simul_saxi_gp_wr	Always Construct
ALWAYS_431 rst or aclk	simul_saxi_gp_wr	Always Construct
ALWAYS_432 **	simul_saxi_gp_wr	Always Construct
ALWAYS_433 aclk	simul_saxi_gp_wr	Always Construct
ALWAYS_434 aclk or rst	simul_saxi_gp_wr	Always Construct
ALWAYS_435 rst or aclk	simul_saxi_gp_wr	Always Construct
ALWAYS_436 NMRST	simul_sensor12bits	Always Construct
ALWAYS_437	simul_sensor12bits	Always Construct
ALWAYS_438 MCLK	simul_sensor12bits	Always Construct
ALWAYS_439 MCLK	simul_sensor12bits	Always Construct
ALWAYS_440 c	simul_sensor12bits	Always Construct
ALWAYS_441 stoppedd or c	simul_sensor12bits	Always Construct
simul_axi_hp_wr.ALWAYS_510 clk or rst	fifo_same_clock_fill	Always Construct
simul_saxi_gp_wr.ALWAYS_510 clk or rst	fifo_same_clock_fill	Always Construct
simul_axi_hp_wr.ALWAYS_511 clk	fifo_same_clock_fill	Always Construct
simul_saxi_gp_wr.ALWAYS_511 clk	fifo_same_clock_fill	Always Construct
ALWAYS_532 src_clk or rst	pulse_cross_clock	Always Construct
ALWAYS_533 dst_clk	pulse_cross_clock	Always Construct
ALWAYS_555 mclk	x393	Always Construct
ALWAYS_556 axird_bram_rclk	x393	Always Construct
ALWAYS_557 comb_rst or axi_aclk	x393	Always Construct
axibram_read	x393	Module Instance
axibram_write	x393	Module Instance
clocks393m	x393	Module Instance
cmd_frame_sequencer	x393	Module Instance
cmd_mux	x393	Module Instance
cmd_readback	x393	Module Instance
cmd_seq_mux	x393	Module Instance
compressor393	x393	Module Instance
DATAPATH	x393_dut
ddr3	ddr3_wrap	Module Instance
ddr3_wrap	x393_dut
debug_master	x393	Module Instance
DEBUG_RD_DATA	x393_dut
DEBUG_WR_SINGLE	x393_dut
ddr3_wrap.dly01_16	dly_16	Module Instance
simul_axi_hp_wr.dly01_16	dly_16	Module Instance
simul_saxi_gp_wr.dly01_16	dly_16	Module Instance
ddr3_wrap.dly_16	ddr3_wrap	Module Instance
simul_axi_hp_wr.dly_16	simul_axi_hp_wr	Module Instance
simul_saxi_gp_wr.dly_16	simul_saxi_gp_wr	Module Instance
event_logger	x393	Module Instance
simul_axi_hp_rd.fifo_same_clock_fill	simul_axi_hp_rd	Module Instance
simul_axi_hp_rd.fifo_same_clock_fill	simul_axi_hp_rd	Module Instance
simul_axi_hp_wr.fifo_same_clock_fill	simul_axi_hp_wr	Module Instance
simul_saxi_gp_wr.fifo_same_clock_fill	simul_saxi_gp_wr	Module Instance
fpga_version.vh	x393	Include
frame_num_sync	x393	Module Instance
GENERATE [191]	par12_hispi_psp4l	GENERATE
ddr3_wrap.GENERATE [50]	dly_16	GENERATE
simul_axi_hp_wr.GENERATE [50]	dly_16	GENERATE
simul_saxi_gp_wr.GENERATE [50]	dly_16	GENERATE
par12_hispi_psp4l.GENERATE [51]	simul_clk_mult_div	GENERATE
simul_clk_mult_div.GENERATE [51]	simul_clk_mult_div	GENERATE
GENERATE [58]	simul_clk	GENERATE
GENERATE [64]	simul_clk_mult_div	GENERATE
GENERATE [65]	simul_clk	GENERATE
GENERATE [72]	simul_clk	GENERATE
GENERATE [79]	simul_clk	GENERATE
GENERATE [866]	x393	GENERATE
gpio393	x393	Module Instance
IVERILOG_INCLUDE.v	x393_dut
mcntrl393	x393	Module Instance
mcntrl393_test01	x393	Module Instance
membridge	x393	Module Instance
mult_saxi_wr	x393	Module Instance
mult_saxi_wr_inbuf	x393	Module Instance
par12_hispi_psp4l	x393_dut
par12_hispi_psp4l	x393_dut
par12_hispi_psp4l	x393_dut
par12_hispi_psp4l	x393_dut
par12_hispi_psp4l_lane	par12_hispi_psp4l	Module Instance
PS7	x393	Module Instance
pulse_cross_clock	par12_hispi_psp4l	Module Instance
sata_ahci_top	x393	Module Instance
sensors393	x393	Module Instance
sim_clk_div	simul_clk_mult_div	Module Instance
sim_frac_clk_delay	par12_hispi_psp4l	Module Instance
sim_frac_clk_delay	par12_hispi_psp4l	Module Instance
sim_frac_clk_delay	par12_hispi_psp4l	Module Instance
sim_frac_clk_delay	par12_hispi_psp4l	Module Instance
sim_frac_clk_delay	par12_hispi_psp4l	Module Instance
simul_axi_master_rdaddr.simul_axi_fifo	simul_axi_master_rdaddr	Module Instance
simul_axi_master_wraddr.simul_axi_fifo	simul_axi_master_wraddr	Module Instance
simul_axi_master_wdata.simul_axi_fifo	simul_axi_master_wdata	Module Instance
simul_axi_hp_rd	x393_dut
simul_axi_hp_wr	x393_dut
simul_axi_hp_wr	x393_dut
simul_axi_master_rdaddr	x393_dut
simul_axi_master_wdata	x393_dut
simul_axi_master_wraddr	x393_dut
simul_axi_read	x393_dut
simul_axi_slow_ready	x393_dut
simul_axi_slow_ready	x393_dut
simul_clk	x393_dut
simul_clk_mult	simul_clk_mult_div	Module Instance
simul_clk_mult_div	x393_dut
simul_clk_mult_div	x393_dut
simul_clk_mult_div	x393_dut
simul_clk_mult_div	x393_dut
simul_clk_single	simul_clk	Module Instance
simul_clk_single	simul_clk	Module Instance
simul_clk_single	simul_clk	Module Instance
simul_clk_single	simul_clk	Module Instance
simul_fifo	simul_axi_read	Module Instance
simul_saxi_gp_wr	x393_dut
simul_sensor12bits	x393_dut
simul_sensor12bits	x393_dut
simul_sensor12bits	x393_dut
simul_sensor12bits	x393_dut
status_read	x393	Module Instance
status_router16	x393	Module Instance
sync_resets	x393	Module Instance
timing393	x393	Module Instance
x393	x393_dut
x393_parameters.vh	x393_dut
x393_simulation_parameters.vh	x393_dut