x393  1.0
FPGAcodeforElphelNC393camera
Static Public Member Functions | Public Attributes | List of all members
par12_hispi_psp4l Module Reference
Inheritance diagram for par12_hispi_psp4l:
Inheritance graph
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Collaboration diagram for par12_hispi_psp4l:
Collaboration graph
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Static Public Member Functions

Always Constructs

ALWAYS_398  ( pclk )
ALWAYS_399  ( pclk )
ALWAYS_400  ( pclk )
ALWAYS_401  ( oclk )
ALWAYS_402  ( oclk )
ALWAYS_403  ( oclk )

Public Attributes

Inputs

pclk  
rst  
pxd   [ 11 : 0 ]
vact  
hact_in  

Outputs

lane_p   [ 3 : 0 ]
lane_n   [ 3 : 0 ]
clk_p  
clk_n  

Parameters

FULL_HEIGHT   0
CLOCK_MPY   10
CLOCK_DIV   3
LANE0_DLY   1 . 3
LANE1_DLY   2 . 7
LANE2_DLY   0 . 2
LANE3_DLY   1 . 8
CLK_DLY   2 . 3
EMBED_LINES   2
MSB_FIRST   0
FIFO_LOGDEPTH   12
FIFO_DEPTH   1 << FIFO_LOGDEPTH
SYNC_SOF   [ 3 : 0 ] 3
SYNC_SOL   [ 3 : 0 ] 1
SYNC_EOF   [ 3 : 0 ] 7
SYNC_EOL   [ 3 : 0 ] 6

GENERATE

GENERATE [191]  

Signals

integer  lines_left
integer  pre_lines
reg[ 1 : 0 ]  lane_pcntr
wire  hact
reg  image_lines
reg  vact_d
reg[ 47 : 0 ]  pxd_d
reg[ 48 : 0 ]  fifo_di
reg  fifo_we
reg  hact_d
reg  next_sof
reg  next_line_pclk
reg  next_frame_pclk
wire  pre_fifo_we_eof_w
wire  pre_fifo_we_sof_sol_w
wire  pre_fifo_we_data_w
wire  pre_fifo_we_w
reg[ 48 : 0 ]  fifo_ram [ 0 :FIFO_DEPTH - 1 ]
reg[FIFO_LOGDEPTH - 1 : 0 ]  fifo_wa
wire  oclk
wire  next_line_oclk
wire  next_frame_oclk
reg  orst_r
wire  orst
wire[ 3 : 0 ]  rdy
wire[ 3 : 0 ]  sdata
wire[ 3 : 0 ]  sdata_dly
reg[FIFO_LOGDEPTH - 1 : 0 ]  fifo_ra
wire[ 48 : 0 ]  fifo_out
wire  fifo_dav
wire  sof_sol_sent
reg[ 1 : 0 ]  lines_available
wire  line_available
reg[ 1 : 0 ]  frames_open
wire  eof_sent
reg  clk_pn
wire  clk_pn_dly

Module Instances

simul_clk_mult_div::simul_clk_div_mult_i   Module simul_clk_mult_div
pulse_cross_clock::pulse_cross_clock_sof_sol_i   Module pulse_cross_clock
pulse_cross_clock::pulse_cross_clock_sof_i   Module pulse_cross_clock
par12_hispi_psp4l_lane::par12_hispi_psp4l_lane_i   Module par12_hispi_psp4l_lane [generate]
sim_frac_clk_delay::sim_frac_clk_delay0_i   Module sim_frac_clk_delay
sim_frac_clk_delay::sim_frac_clk_delay1_i   Module sim_frac_clk_delay
sim_frac_clk_delay::sim_frac_clk_delay2_i   Module sim_frac_clk_delay
sim_frac_clk_delay::sim_frac_clk_delay3_i   Module sim_frac_clk_delay
sim_frac_clk_delay::sim_frac_clk_delay_clk_i   Module sim_frac_clk_delay

Detailed Description

Definition at line 41 of file par12_hispi_psp4l.v.

Member Function Documentation

ALWAYS_398 (   pclk  
)
Always Construct

Definition at line 91 of file par12_hispi_psp4l.v.

ALWAYS_399 (   pclk  
)
Always Construct

Definition at line 96 of file par12_hispi_psp4l.v.

ALWAYS_400 (   pclk  
)
Always Construct

Definition at line 131 of file par12_hispi_psp4l.v.

ALWAYS_401 (   oclk  
)
Always Construct

Definition at line 177 of file par12_hispi_psp4l.v.

ALWAYS_402 (   oclk  
)
Always Construct

Definition at line 217 of file par12_hispi_psp4l.v.

ALWAYS_403 (   oclk  
)
Always Construct

Definition at line 266 of file par12_hispi_psp4l.v.

Member Data Documentation

FULL_HEIGHT 0
Parameter

Definition at line 42 of file par12_hispi_psp4l.v.

CLOCK_MPY 10
Parameter

Definition at line 43 of file par12_hispi_psp4l.v.

CLOCK_DIV 3
Parameter

Definition at line 44 of file par12_hispi_psp4l.v.

LANE0_DLY 1 . 3
Parameter

Definition at line 45 of file par12_hispi_psp4l.v.

LANE1_DLY 2 . 7
Parameter

Definition at line 46 of file par12_hispi_psp4l.v.

LANE2_DLY 0 . 2
Parameter

Definition at line 47 of file par12_hispi_psp4l.v.

LANE3_DLY 1 . 8
Parameter

Definition at line 48 of file par12_hispi_psp4l.v.

CLK_DLY 2 . 3
Parameter

Definition at line 49 of file par12_hispi_psp4l.v.

EMBED_LINES 2
Parameter

Definition at line 50 of file par12_hispi_psp4l.v.

MSB_FIRST 0
Parameter

Definition at line 51 of file par12_hispi_psp4l.v.

FIFO_LOGDEPTH 12
Parameter

Definition at line 52 of file par12_hispi_psp4l.v.

pclk
Input

Definition at line 54 of file par12_hispi_psp4l.v.

rst
Input

Definition at line 55 of file par12_hispi_psp4l.v.

pxd [ 11 : 0 ]
Input

Definition at line 56 of file par12_hispi_psp4l.v.

vact
Input

Definition at line 57 of file par12_hispi_psp4l.v.

hact_in
Input

Definition at line 58 of file par12_hispi_psp4l.v.

lane_p [ 3 : 0 ]
Output

Definition at line 59 of file par12_hispi_psp4l.v.

lane_n [ 3 : 0 ]
Output

Definition at line 60 of file par12_hispi_psp4l.v.

clk_p
Output

Definition at line 61 of file par12_hispi_psp4l.v.

clk_n
Output

Definition at line 62 of file par12_hispi_psp4l.v.

FIFO_DEPTH 1 << FIFO_LOGDEPTH
Parameter

Definition at line 64 of file par12_hispi_psp4l.v.

SYNC_SOF 3
Parameter

Definition at line 65 of file par12_hispi_psp4l.v.

SYNC_SOL 1
Parameter

Definition at line 66 of file par12_hispi_psp4l.v.

SYNC_EOF 7
Parameter

Definition at line 67 of file par12_hispi_psp4l.v.

SYNC_EOL 6
Parameter

Definition at line 68 of file par12_hispi_psp4l.v.

lines_left
Signal

Definition at line 71 of file par12_hispi_psp4l.v.

pre_lines
Signal

Definition at line 72 of file par12_hispi_psp4l.v.

lane_pcntr
Signal

Definition at line 73 of file par12_hispi_psp4l.v.

hact
Signal

Definition at line 74 of file par12_hispi_psp4l.v.

image_lines
Signal

Definition at line 75 of file par12_hispi_psp4l.v.

vact_d
Signal

Definition at line 76 of file par12_hispi_psp4l.v.

pxd_d
Signal

Definition at line 77 of file par12_hispi_psp4l.v.

fifo_di
Signal

Definition at line 78 of file par12_hispi_psp4l.v.

fifo_we
Signal

Definition at line 79 of file par12_hispi_psp4l.v.

hact_d
Signal

Definition at line 80 of file par12_hispi_psp4l.v.

next_sof
Signal

Definition at line 81 of file par12_hispi_psp4l.v.

next_line_pclk
Signal

Definition at line 82 of file par12_hispi_psp4l.v.

next_frame_pclk
Signal

Definition at line 83 of file par12_hispi_psp4l.v.

pre_fifo_we_eof_w
Signal

Definition at line 84 of file par12_hispi_psp4l.v.

pre_fifo_we_sof_sol_w
Signal

Definition at line 86 of file par12_hispi_psp4l.v.

pre_fifo_we_data_w
Signal

Definition at line 88 of file par12_hispi_psp4l.v.

pre_fifo_we_w
Signal

Definition at line 89 of file par12_hispi_psp4l.v.

fifo_ram [ 0 :FIFO_DEPTH - 1 ]
Signal

Definition at line 128 of file par12_hispi_psp4l.v.

fifo_wa
Signal

Definition at line 129 of file par12_hispi_psp4l.v.

oclk
Signal

Definition at line 139 of file par12_hispi_psp4l.v.

next_line_oclk
Signal

Definition at line 141 of file par12_hispi_psp4l.v.

next_frame_oclk
Signal

Definition at line 142 of file par12_hispi_psp4l.v.

orst_r
Signal

Definition at line 143 of file par12_hispi_psp4l.v.

orst
Signal

Definition at line 144 of file par12_hispi_psp4l.v.

rdy
Signal

Definition at line 181 of file par12_hispi_psp4l.v.

sdata
Signal

Definition at line 182 of file par12_hispi_psp4l.v.

sdata_dly
Signal

Definition at line 183 of file par12_hispi_psp4l.v.

fifo_ra
Signal

Definition at line 184 of file par12_hispi_psp4l.v.

fifo_out
Signal

Definition at line 185 of file par12_hispi_psp4l.v.

fifo_dav
Signal

Definition at line 186 of file par12_hispi_psp4l.v.

sof_sol_sent
Signal

Definition at line 188 of file par12_hispi_psp4l.v.

lines_available
Signal

Definition at line 189 of file par12_hispi_psp4l.v.

line_available
Signal

Definition at line 190 of file par12_hispi_psp4l.v.

frames_open
Signal

Definition at line 214 of file par12_hispi_psp4l.v.

eof_sent
Signal

Definition at line 215 of file par12_hispi_psp4l.v.

clk_pn
Signal

Definition at line 264 of file par12_hispi_psp4l.v.

clk_pn_dly
Signal

Definition at line 265 of file par12_hispi_psp4l.v.

GENERATE [191]
GENERATE

Definition at line 191 of file par12_hispi_psp4l.v.

par12_hispi_psp4l_lane par12_hispi_psp4l_lane_i
Module Instance

Definition at line 194 of file par12_hispi_psp4l.v.

pulse_cross_clock pulse_cross_clock_sof_sol_i
Module Instance

Definition at line 155 of file par12_hispi_psp4l.v.

pulse_cross_clock pulse_cross_clock_sof_i
Module Instance

Definition at line 166 of file par12_hispi_psp4l.v.

sim_frac_clk_delay sim_frac_clk_delay0_i
Module Instance

Definition at line 231 of file par12_hispi_psp4l.v.

sim_frac_clk_delay sim_frac_clk_delay1_i
Module Instance

Definition at line 240 of file par12_hispi_psp4l.v.

sim_frac_clk_delay sim_frac_clk_delay2_i
Module Instance

Definition at line 248 of file par12_hispi_psp4l.v.

sim_frac_clk_delay sim_frac_clk_delay3_i
Module Instance

Definition at line 256 of file par12_hispi_psp4l.v.

sim_frac_clk_delay sim_frac_clk_delay_clk_i
Module Instance

Definition at line 271 of file par12_hispi_psp4l.v.

simul_clk_mult_div simul_clk_div_mult_i
Module Instance

Definition at line 145 of file par12_hispi_psp4l.v.

The documentation for this Module was generated from the following files: