Public Attributes |
Inputs | |
| rst | |
Outputs | |
| clk | |
| memclk | |
| ffclk0 | [ 1 : 0 ] |
| ffclk1 | [ 1 : 0 ] |
Parameters | |
| CLKIN_PERIOD | 5 . 0 |
| MEMCLK_PERIOD | 5 . 0 |
| FCLK0_PERIOD | 10 . 417 |
| FCLK1_PERIOD | 0 . 0 |
GENERATE | |
| GENERATE [58] | |
| GENERATE [65] | |
| GENERATE [72] | |
| GENERATE [79] | |
Signals | |
| wire | ffclk0_w |
| wire | ffclk1_w |
Module Instances | |
| simul_clk_single::simul_clk_i | Module simul_clk_single [generate] |
| simul_clk_single::simul_memclk_i | Module simul_clk_single [generate] |
| simul_clk_single::simul_ffclk0_i | Module simul_clk_single [generate] |
| simul_clk_single::simul_ffclk1_i | Module simul_clk_single [generate] |
Detailed Description
Definition at line 41 of file simul_clk.v.
Member Data Documentation
|
Parameter |
Definition at line 42 of file simul_clk.v.
|
Parameter |
Definition at line 43 of file simul_clk.v.
|
Parameter |
Definition at line 44 of file simul_clk.v.
|
Parameter |
Definition at line 45 of file simul_clk.v.
|
Input |
Definition at line 47 of file simul_clk.v.
|
Output |
Definition at line 48 of file simul_clk.v.
|
Output |
Definition at line 49 of file simul_clk.v.
|
Output |
Definition at line 50 of file simul_clk.v.
|
Output |
Definition at line 51 of file simul_clk.v.
|
Signal |
Definition at line 54 of file simul_clk.v.
|
Signal |
Definition at line 55 of file simul_clk.v.
|
GENERATE |
Definition at line 58 of file simul_clk.v.
|
GENERATE |
Definition at line 65 of file simul_clk.v.
|
GENERATE |
Definition at line 72 of file simul_clk.v.
|
GENERATE |
Definition at line 79 of file simul_clk.v.
|
Module Instance |
Definition at line 60 of file simul_clk.v.
|
Module Instance |
Definition at line 67 of file simul_clk.v.
|
Module Instance |
Definition at line 74 of file simul_clk.v.
|
Module Instance |
Definition at line 81 of file simul_clk.v.
The documentation for this Module was generated from the following files:
- simulation_modules/simul_clk.v
