sim_clk_div Module Reference

Inheritance diagram for sim_clk_div:

Static Public Member Functions

Always Constructs
ALWAYS_405	( clk_in )

Public Attributes

Inputs
clk_in
en

Outputs
clk_out

Parameters
DIVISOR	5

Signals
integer	cntr
reg	clk_out_r

Detailed Description

Definition at line 41 of file sim_clk_div.v.

Member Function Documentation

ALWAYS_405 (   clk_in   )

Always Construct

Definition at line 51 of file sim_clk_div.v.

Member Data Documentation

DIVISOR 5

Parameter

Definition at line 42 of file sim_clk_div.v.

clk_in

Input

Definition at line 44 of file sim_clk_div.v.

en

Input

Definition at line 45 of file sim_clk_div.v.

clk_out

Output

Definition at line 46 of file sim_clk_div.v.

cntr

Signal

Definition at line 48 of file sim_clk_div.v.

clk_out_r

Signal

Definition at line 49 of file sim_clk_div.v.

---

The documentation for this Module was generated from the following files:

• simulation_modules/sim_clk_div.v