simul_axi_master_wraddr Module Reference

Inheritance diagram for simul_axi_master_wraddr:

Collaboration diagram for simul_axi_master_wraddr:

Public Attributes

Inputs
clk
reset
awid_in	[ID_WIDTH - 1 : 0 ]
awaddr_in	[ADDRESS_WIDTH - 1 : 0 ]
awlen_in	[ 3 : 0 ]
awsize_in	[ 1 : 0 ]
awburst_in	[ 1 : 0 ]
awcache_in	[ 3 : 0 ]
awprot_in	[ 2 : 0 ]
awready
set_cmd

Outputs
awid	[ID_WIDTH - 1 : 0 ]
awaddr	[ADDRESS_WIDTH - 1 : 0 ]
awlen	[ 3 : 0 ]
awsize	[ 1 : 0 ]
awburst	[ 1 : 0 ]
awcache	[ 3 : 0 ]
awprot	[ 2 : 0 ]
awvalid
ready

Parameters
ID_WIDTH	integer 12
ADDRESS_WIDTH	integer 32
LATENCY	integer 0
DEPTH	integer 8
DATA_DELAY	3 . 5
VALID_DELAY	4 . 0

Signals
wire[ID_WIDTH - 1 : 0 ]	awid_out
wire[ADDRESS_WIDTH - 1 : 0 ]	awaddr_out
wire[ 3 : 0 ]	awlen_out
wire[ 1 : 0 ]	awsize_out
wire[ 1 : 0 ]	awburst_out
wire[ 3 : 0 ]	awcache_out
wire[ 2 : 0 ]	awprot_out
wire	awvalid_out

Module Instances
simul_axi_fifo::simul_axi_fifo_i	Module simul_axi_fifo

Detailed Description

Definition at line 41 of file simul_axi_master_wraddr.v.

Member Data Documentation

ID_WIDTH 12

Parameter

Definition at line 43 of file simul_axi_master_wraddr.v.

ADDRESS_WIDTH 32

Parameter

Definition at line 44 of file simul_axi_master_wraddr.v.

LATENCY 0

Parameter

Definition at line 45 of file simul_axi_master_wraddr.v.

DEPTH 8

Parameter

Definition at line 46 of file simul_axi_master_wraddr.v.

DATA_DELAY 3 . 5

Parameter

Definition at line 47 of file simul_axi_master_wraddr.v.

VALID_DELAY 4 . 0

Parameter

Definition at line 48 of file simul_axi_master_wraddr.v.

clk

Input

Definition at line 50 of file simul_axi_master_wraddr.v.

reset

Input

Definition at line 51 of file simul_axi_master_wraddr.v.

awid_in [ID_WIDTH - 1 : 0 ]

Input

Definition at line 52 of file simul_axi_master_wraddr.v.

awaddr_in [ADDRESS_WIDTH - 1 : 0 ]

Input

Definition at line 53 of file simul_axi_master_wraddr.v.

awlen_in [ 3 : 0 ]

Input

Definition at line 54 of file simul_axi_master_wraddr.v.

awsize_in [ 1 : 0 ]

Input

Definition at line 55 of file simul_axi_master_wraddr.v.

awburst_in [ 1 : 0 ]

Input

Definition at line 56 of file simul_axi_master_wraddr.v.

awcache_in [ 3 : 0 ]

Input

Definition at line 57 of file simul_axi_master_wraddr.v.

awprot_in [ 2 : 0 ]

Input

Definition at line 58 of file simul_axi_master_wraddr.v.

awid [ID_WIDTH - 1 : 0 ]

Output

Definition at line 60 of file simul_axi_master_wraddr.v.

awaddr [ADDRESS_WIDTH - 1 : 0 ]

Output

Definition at line 61 of file simul_axi_master_wraddr.v.

awlen [ 3 : 0 ]

Output

Definition at line 62 of file simul_axi_master_wraddr.v.

awsize [ 1 : 0 ]

Output

Definition at line 63 of file simul_axi_master_wraddr.v.

awburst [ 1 : 0 ]

Output

Definition at line 64 of file simul_axi_master_wraddr.v.

awcache [ 3 : 0 ]

Output

Definition at line 65 of file simul_axi_master_wraddr.v.

awprot [ 2 : 0 ]

Output

Definition at line 66 of file simul_axi_master_wraddr.v.

awvalid

Output

Definition at line 67 of file simul_axi_master_wraddr.v.

awready

Input

Definition at line 68 of file simul_axi_master_wraddr.v.

set_cmd

Input

Definition at line 70 of file simul_axi_master_wraddr.v.

ready

Output

Definition at line 71 of file simul_axi_master_wraddr.v.

awid_out

Signal

Definition at line 73 of file simul_axi_master_wraddr.v.

awaddr_out

Signal

Definition at line 74 of file simul_axi_master_wraddr.v.

awlen_out

Signal

Definition at line 75 of file simul_axi_master_wraddr.v.

awsize_out

Signal

Definition at line 76 of file simul_axi_master_wraddr.v.

awburst_out

Signal

Definition at line 77 of file simul_axi_master_wraddr.v.

awcache_out

Signal

Definition at line 78 of file simul_axi_master_wraddr.v.

awprot_out

Signal

Definition at line 79 of file simul_axi_master_wraddr.v.

awvalid_out

Signal

Definition at line 80 of file simul_axi_master_wraddr.v.

simul_axi_fifo simul_axi_fifo_i

Module Instance

Definition at line 91 of file simul_axi_master_wraddr.v.

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The documentation for this Module was generated from the following files:

• simulation_modules/simul_axi_master_wraddr.v