simul_axi_fifo Module Reference

Inheritance diagram for simul_axi_fifo:

Static Public Member Functions

Always Constructs
ALWAYS_410	( clk or reset )
ALWAYS_411	( clk )

Public Attributes

Inputs
clk
reset
data_in	[WIDTH - 1 : 0 ]
load
ready

Outputs
input_ready
data_out	[WIDTH - 1 : 0 ]
valid

Parameters
WIDTH	integer 64
LATENCY	integer 0
DEPTH	integer 8
FIFO_DEPTH	integer LATENCY +DEPTH + 1

Signals
reg[WIDTH - 1 : 0 ]	fifo [ 0 :FIFO_DEPTH - 1 ]
integer	in_address
integer	out_address
integer	in_count
integer	out_count
reg[LATENCY : 0 ]	latency_delay_r
wire	out_inc
wire	input_ready_w
wire	load_and_ready
wire[LATENCY + 1 : 0 ]	latency_delay

Detailed Description

Definition at line 42 of file simul_axi_fifo_out.v.

Member Function Documentation

ALWAYS_410 (   clk or reset   )

Always Construct

Definition at line 78 of file simul_axi_fifo_out.v.

ALWAYS_411 (   clk   )

Always Construct

Definition at line 96 of file simul_axi_fifo_out.v.

Member Data Documentation

WIDTH 64

Parameter

Definition at line 44 of file simul_axi_fifo_out.v.

LATENCY 0

Parameter

Definition at line 45 of file simul_axi_fifo_out.v.

DEPTH 8

Parameter

Definition at line 46 of file simul_axi_fifo_out.v.

FIFO_DEPTH LATENCY +DEPTH + 1

Parameter

Definition at line 48 of file simul_axi_fifo_out.v.

clk

Input

Definition at line 51 of file simul_axi_fifo_out.v.

reset

Input

Definition at line 52 of file simul_axi_fifo_out.v.

data_in [WIDTH - 1 : 0 ]

Input

Definition at line 53 of file simul_axi_fifo_out.v.

load

Input

Definition at line 54 of file simul_axi_fifo_out.v.

input_ready

Output

Definition at line 55 of file simul_axi_fifo_out.v.

data_out [WIDTH - 1 : 0 ]

Output

Definition at line 56 of file simul_axi_fifo_out.v.

valid

Output

Definition at line 57 of file simul_axi_fifo_out.v.

ready

Input

Definition at line 58 of file simul_axi_fifo_out.v.

fifo [ 0 :FIFO_DEPTH - 1 ]

Signal

Definition at line 60 of file simul_axi_fifo_out.v.

in_address

Signal

Definition at line 61 of file simul_axi_fifo_out.v.

out_address

Signal

Definition at line 62 of file simul_axi_fifo_out.v.

in_count

Signal

Definition at line 63 of file simul_axi_fifo_out.v.

out_count

Signal

Definition at line 64 of file simul_axi_fifo_out.v.

latency_delay_r

Signal

Definition at line 65 of file simul_axi_fifo_out.v.

out_inc

Signal

Definition at line 67 of file simul_axi_fifo_out.v.

input_ready_w

Signal

Definition at line 68 of file simul_axi_fifo_out.v.

load_and_ready

Signal

Definition at line 69 of file simul_axi_fifo_out.v.

latency_delay

Signal

Definition at line 70 of file simul_axi_fifo_out.v.

---

The documentation for this Module was generated from the following files:

• simulation_modules/simul_axi_fifo_out.v