simul_axi_slow_ready Module Reference

Inheritance diagram for simul_axi_slow_ready:

Static Public Member Functions

Always Constructs
ALWAYS_424	( clk or reset )

Public Attributes

Inputs
clk
reset
delay	[ 3 : 0 ]
valid

Outputs
ready

Signals
reg[ 14 : 0 ]	rdy_reg

Detailed Description

Definition at line 41 of file simul_axi_slow_ready.v.

Member Function Documentation

ALWAYS_424 (   clk or reset   )

Always Construct

Definition at line 50 of file simul_axi_slow_ready.v.

Member Data Documentation

clk

Input

Definition at line 42 of file simul_axi_slow_ready.v.

reset

Input

Definition at line 43 of file simul_axi_slow_ready.v.

delay [ 3 : 0 ]

Input

Definition at line 44 of file simul_axi_slow_ready.v.

valid

Input

Definition at line 45 of file simul_axi_slow_ready.v.

ready

Output

Definition at line 46 of file simul_axi_slow_ready.v.

rdy_reg

Signal

Definition at line 48 of file simul_axi_slow_ready.v.

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The documentation for this Module was generated from the following files:

• simulation_modules/simul_axi_slow_ready.v