simul_axi_hp_wr Module Reference

Inheritance diagram for simul_axi_hp_wr:

Collaboration diagram for simul_axi_hp_wr:

Static Public Member Functions

Always Constructs
ALWAYS_415	( aclk or rst )
ALWAYS_416	( rst or aclk )
ALWAYS_417	( rst or aclk )
ALWAYS_418	( rst or aclk )
ALWAYS_419	( aclk )
ALWAYS_420	( aclk or rst )
ALWAYS_421	( rst or aclk )

Public Attributes

Inputs
rst
aclk
awaddr	[ 31 : 0 ]
awvalid
awid	[ 5 : 0 ]
awlock	[ 1 : 0 ]
awcache	[ 3 : 0 ]
awprot	[ 2 : 0 ]
awlen	[ 3 : 0 ]
awsize	[ 1 : 0 ]
awburst	[ 1 : 0 ]
awqos	[ 3 : 0 ]
wdata	[ 63 : 0 ]
wvalid
wid	[ 5 : 0 ]
wlast
wstrb	[ 7 : 0 ]
bready
wrissuecap1en
sim_wr_ready
sim_bresp_latency	[ 3 : 0 ]
reg_addr	[ 31 : 0 ]
reg_wr
reg_rd
reg_din	[ 31 : 0 ]

Outputs
aresetn
awready
wready
bvalid
bid	[ 5 : 0 ]
bresp	[ 1 : 0 ]
wcount	[ 7 : 0 ]
wacount	[ 5 : 0 ]
sim_wr_address	[ 31 : 0 ]
sim_wid	[ 5 : 0 ]
sim_wr_valid
sim_wr_data	[ 63 : 0 ]
sim_wr_stb	[ 7 : 0 ]
sim_wr_cap	[ 2 : 0 ]
sim_wr_qos	[ 3 : 0 ]
reg_dout	[ 31 : 0 ]
reg_dvalid

Parameters
HP_PORT	[ 1 : 0 ] 0
AFI_BASECTRL	32 'hf8008000+ (HP_PORT << 12
AFI_WRCHAN_CTRL	AFI_BASECTRL + 'h14
AFI_WRCHAN_ISSUINGCAP	AFI_BASECTRL + 'h18
AFI_WRQOS	AFI_BASECTRL + 'h1c
AFI_WRDATAFIFO_LEVEL	AFI_BASECTRL + 'h20
AFI_WRDEBUG	AFI_BASECTRL + 'h24
VALID_AWLOCK	2 'b0
VALID_AWCACHE	4 'b0011
VALID_AWPROT	3 'b000
VALID_AWLOCK_MASK	2 'b11
VALID_AWCACHE_MASK	4 'b0011
VALID_AWPROT_MASK	3 'b010

Signals
reg[ 3 : 0 ]	WrDataThreshold
reg[ 1 : 0 ]	WrCmdReleaseMode
reg	wrQosHeadOfCmdQEn
reg	wrFabricOutCmdEn
reg	wrFabricQosEn
reg	wr32BitEn
reg[ 2 : 0 ]	wrIssueCap1
reg[ 2 : 0 ]	wrIssueCap0
reg[ 3 : 0 ]	staticQos
wire[ 3 : 0 ]	wr_qos_in
wire[ 3 : 0 ]	wr_qos_out
wire	aw_nempty
wire	w_nempty
wire	enough_data
wire[ 11 : 3 ]	next_wr_address
reg[ 31 : 0 ]	write_address
reg[ 5 : 0 ]	awid_r
wire	fifo_wd_rd
wire	last_confirmed_write
wire[ 5 : 0 ]	awid_out
wire[ 1 : 0 ]	awburst_out
wire[ 1 : 0 ]	awsize_out
wire[ 3 : 0 ]	awlen_out
wire[ 31 : 0 ]	awaddr_out
wire[ 5 : 0 ]	wid_out
wire	wlast_out
wire[ 7 : 0 ]	wstrb_out
wire[ 63 : 0 ]	wdata_out
reg	fifo_data_we_d
reg	fifo_addr_we_d
reg[ 3 : 0 ]	write_left
reg[ 1 : 0 ]	wburst
reg[ 3 : 0 ]	wlen
wire	start_write_burst_w
reg	start_write_burst_r
wire	write_in_progress_w
reg	write_in_progress
wire[ 5 : 0 ]	wresp_num_in_fifo
reg	was_wresp_re
wire	wresp_re
reg[ 7 : 0 ]	num_full_data
wire	inc_num_full_data
wire[ 1 : 0 ]	bresp_value
wire[ 1 : 0 ]	bresp_in
wire	fifo_wd_rd_dly
wire[ 5 : 0 ]	bid_in

Module Instances
fifo_same_clock_fill::waddr_i	Module fifo_same_clock_fill
fifo_same_clock_fill::wdata_i	Module fifo_same_clock_fill
dly_16::bresp_dly_16_i	Module dly_16
fifo_same_clock_fill::wresp_ext_i	Module fifo_same_clock_fill
fifo_same_clock_fill::wresp_i	Module fifo_same_clock_fill

Detailed Description

Definition at line 41 of file simul_axi_hp_wr.v.

Member Function Documentation

ALWAYS_415 (   aclk or rst   )

Always Construct

Definition at line 188 of file simul_axi_hp_wr.v.

ALWAYS_416 (   rst or aclk   )

Always Construct

Definition at line 220 of file simul_axi_hp_wr.v.

ALWAYS_417 (   rst or aclk   )

Always Construct

Definition at line 225 of file simul_axi_hp_wr.v.

ALWAYS_418 (   rst or aclk   )

Always Construct

Definition at line 231 of file simul_axi_hp_wr.v.

ALWAYS_419 (   aclk   )

Always Construct

Definition at line 260 of file simul_axi_hp_wr.v.

ALWAYS_420 (   aclk or rst   )

Always Construct

Definition at line 292 of file simul_axi_hp_wr.v.

ALWAYS_421 (   rst or aclk   )

Always Construct

Definition at line 394 of file simul_axi_hp_wr.v.

Member Data Documentation

HP_PORT 0

Parameter

Definition at line 42 of file simul_axi_hp_wr.v.

rst

Input

Definition at line 44 of file simul_axi_hp_wr.v.

aclk

Input

Definition at line 46 of file simul_axi_hp_wr.v.

aresetn

Output

Definition at line 47 of file simul_axi_hp_wr.v.

awaddr [ 31 : 0 ]

Input

Definition at line 49 of file simul_axi_hp_wr.v.

awvalid

Input

Definition at line 50 of file simul_axi_hp_wr.v.

awready

Output

Definition at line 51 of file simul_axi_hp_wr.v.

awid [ 5 : 0 ]

Input

Definition at line 52 of file simul_axi_hp_wr.v.

awlock [ 1 : 0 ]

Input

Definition at line 53 of file simul_axi_hp_wr.v.

awcache [ 3 : 0 ]

Input

Definition at line 54 of file simul_axi_hp_wr.v.

awprot [ 2 : 0 ]

Input

Definition at line 55 of file simul_axi_hp_wr.v.

awlen [ 3 : 0 ]

Input

Definition at line 56 of file simul_axi_hp_wr.v.

awsize [ 1 : 0 ]

Input

Definition at line 57 of file simul_axi_hp_wr.v.

awburst [ 1 : 0 ]

Input

Definition at line 58 of file simul_axi_hp_wr.v.

awqos [ 3 : 0 ]

Input

Definition at line 59 of file simul_axi_hp_wr.v.

wdata [ 63 : 0 ]

Input

Definition at line 61 of file simul_axi_hp_wr.v.

wvalid

Input

Definition at line 62 of file simul_axi_hp_wr.v.

wready

Output

Definition at line 63 of file simul_axi_hp_wr.v.

wid [ 5 : 0 ]

Input

Definition at line 64 of file simul_axi_hp_wr.v.

wlast

Input

Definition at line 65 of file simul_axi_hp_wr.v.

wstrb [ 7 : 0 ]

Input

Definition at line 66 of file simul_axi_hp_wr.v.

bvalid

Output

Definition at line 68 of file simul_axi_hp_wr.v.

bready

Input

Definition at line 69 of file simul_axi_hp_wr.v.

bid [ 5 : 0 ]

Output

Definition at line 70 of file simul_axi_hp_wr.v.

bresp [ 1 : 0 ]

Output

Definition at line 71 of file simul_axi_hp_wr.v.

wcount [ 7 : 0 ]

Output

Definition at line 73 of file simul_axi_hp_wr.v.

wacount [ 5 : 0 ]

Output

Definition at line 74 of file simul_axi_hp_wr.v.

wrissuecap1en

Input

Definition at line 75 of file simul_axi_hp_wr.v.

sim_wr_address [ 31 : 0 ]

Output

Definition at line 77 of file simul_axi_hp_wr.v.

sim_wid [ 5 : 0 ]

Output

Definition at line 78 of file simul_axi_hp_wr.v.

sim_wr_valid

Output

Definition at line 79 of file simul_axi_hp_wr.v.

sim_wr_ready

Input

Definition at line 80 of file simul_axi_hp_wr.v.

sim_wr_data [ 63 : 0 ]

Output

Definition at line 81 of file simul_axi_hp_wr.v.

sim_wr_stb [ 7 : 0 ]

Output

Definition at line 82 of file simul_axi_hp_wr.v.

sim_bresp_latency [ 3 : 0 ]

Input

Definition at line 83 of file simul_axi_hp_wr.v.

sim_wr_cap [ 2 : 0 ]

Output

Definition at line 84 of file simul_axi_hp_wr.v.

sim_wr_qos [ 3 : 0 ]

Output

Definition at line 85 of file simul_axi_hp_wr.v.

reg_addr [ 31 : 0 ]

Input

Definition at line 86 of file simul_axi_hp_wr.v.

reg_wr

Input

Definition at line 87 of file simul_axi_hp_wr.v.

reg_rd

Input

Definition at line 88 of file simul_axi_hp_wr.v.

reg_din [ 31 : 0 ]

Input

Definition at line 89 of file simul_axi_hp_wr.v.

reg_dout [ 31 : 0 ]

Output

Definition at line 90 of file simul_axi_hp_wr.v.

reg_dvalid

Output

Definition at line 91 of file simul_axi_hp_wr.v.

AFI_BASECTRL 32 'hf8008000+ (HP_PORT << 12

Parameter

Definition at line 94 of file simul_axi_hp_wr.v.

AFI_WRCHAN_CTRL AFI_BASECTRL + 'h14

Parameter

Definition at line 95 of file simul_axi_hp_wr.v.

AFI_WRCHAN_ISSUINGCAP AFI_BASECTRL + 'h18

Parameter

Definition at line 96 of file simul_axi_hp_wr.v.

AFI_WRQOS AFI_BASECTRL + 'h1c

Parameter

Definition at line 97 of file simul_axi_hp_wr.v.

AFI_WRDATAFIFO_LEVEL AFI_BASECTRL + 'h20

Parameter

Definition at line 98 of file simul_axi_hp_wr.v.

AFI_WRDEBUG AFI_BASECTRL + 'h24

Parameter

Definition at line 99 of file simul_axi_hp_wr.v.

VALID_AWLOCK 2 'b0

Parameter

Definition at line 101 of file simul_axi_hp_wr.v.

VALID_AWCACHE 4 'b0011

Parameter

Definition at line 102 of file simul_axi_hp_wr.v.

VALID_AWPROT 3 'b000

Parameter

Definition at line 103 of file simul_axi_hp_wr.v.

VALID_AWLOCK_MASK 2 'b11

Parameter

Definition at line 104 of file simul_axi_hp_wr.v.

VALID_AWCACHE_MASK 4 'b0011

Parameter

Definition at line 105 of file simul_axi_hp_wr.v.

VALID_AWPROT_MASK 3 'b010

Parameter

Definition at line 106 of file simul_axi_hp_wr.v.

WrDataThreshold

Signal

Definition at line 117 of file simul_axi_hp_wr.v.

WrCmdReleaseMode

Signal

Definition at line 118 of file simul_axi_hp_wr.v.

wrQosHeadOfCmdQEn

Signal

Definition at line 119 of file simul_axi_hp_wr.v.

wrFabricOutCmdEn

Signal

Definition at line 120 of file simul_axi_hp_wr.v.

wrFabricQosEn

Signal

Definition at line 121 of file simul_axi_hp_wr.v.

wr32BitEn

Signal

Definition at line 122 of file simul_axi_hp_wr.v.

wrIssueCap1

Signal

Definition at line 123 of file simul_axi_hp_wr.v.

wrIssueCap0

Signal

Definition at line 124 of file simul_axi_hp_wr.v.

staticQos

Signal

Definition at line 125 of file simul_axi_hp_wr.v.

wr_qos_in

Signal

Definition at line 127 of file simul_axi_hp_wr.v.

wr_qos_out

Signal

Definition at line 128 of file simul_axi_hp_wr.v.

aw_nempty

Signal

Definition at line 130 of file simul_axi_hp_wr.v.

w_nempty

Signal

Definition at line 131 of file simul_axi_hp_wr.v.

enough_data

Signal

Definition at line 132 of file simul_axi_hp_wr.v.

next_wr_address

Signal

Definition at line 133 of file simul_axi_hp_wr.v.

write_address

Signal

Definition at line 134 of file simul_axi_hp_wr.v.

awid_r

Signal

Definition at line 135 of file simul_axi_hp_wr.v.

fifo_wd_rd

Signal

Definition at line 136 of file simul_axi_hp_wr.v.

last_confirmed_write

Signal

Definition at line 137 of file simul_axi_hp_wr.v.

awid_out

Signal

Definition at line 140 of file simul_axi_hp_wr.v.

awburst_out

Signal

Definition at line 141 of file simul_axi_hp_wr.v.

awsize_out

Signal

Definition at line 142 of file simul_axi_hp_wr.v.

awlen_out

Signal

Definition at line 143 of file simul_axi_hp_wr.v.

awaddr_out

Signal

Definition at line 144 of file simul_axi_hp_wr.v.

wid_out

Signal

Definition at line 145 of file simul_axi_hp_wr.v.

wlast_out

Signal

Definition at line 146 of file simul_axi_hp_wr.v.

wstrb_out

Signal

Definition at line 147 of file simul_axi_hp_wr.v.

wdata_out

Signal

Definition at line 148 of file simul_axi_hp_wr.v.

fifo_data_we_d

Signal

Definition at line 150 of file simul_axi_hp_wr.v.

fifo_addr_we_d

Signal

Definition at line 151 of file simul_axi_hp_wr.v.

write_left

Signal

Definition at line 152 of file simul_axi_hp_wr.v.

wburst

Signal

Definition at line 153 of file simul_axi_hp_wr.v.

wlen

Signal

Definition at line 154 of file simul_axi_hp_wr.v.

start_write_burst_w

Signal

Definition at line 155 of file simul_axi_hp_wr.v.

start_write_burst_r

Signal

Definition at line 156 of file simul_axi_hp_wr.v.

write_in_progress_w

Signal

Definition at line 157 of file simul_axi_hp_wr.v.

write_in_progress

Signal

Definition at line 158 of file simul_axi_hp_wr.v.

wresp_num_in_fifo

Signal

Definition at line 160 of file simul_axi_hp_wr.v.

was_wresp_re

Signal

Definition at line 161 of file simul_axi_hp_wr.v.

wresp_re

Signal

Definition at line 162 of file simul_axi_hp_wr.v.

num_full_data

Signal

Definition at line 164 of file simul_axi_hp_wr.v.

inc_num_full_data

Signal

Definition at line 165 of file simul_axi_hp_wr.v.

bresp_value

Signal

Definition at line 354 of file simul_axi_hp_wr.v.

bresp_in

Signal

Definition at line 355 of file simul_axi_hp_wr.v.

fifo_wd_rd_dly

Signal

Definition at line 357 of file simul_axi_hp_wr.v.

bid_in

Signal

Definition at line 358 of file simul_axi_hp_wr.v.

dly_16 bresp_dly_16_i

Module Instance

Definition at line 362 of file simul_axi_hp_wr.v.

fifo_same_clock_fill waddr_i

Module Instance

Definition at line 317 of file simul_axi_hp_wr.v.

fifo_same_clock_fill wdata_i

Module Instance

Definition at line 335 of file simul_axi_hp_wr.v.

fifo_same_clock_fill wresp_ext_i

Module Instance

Definition at line 374 of file simul_axi_hp_wr.v.

fifo_same_clock_fill wresp_i

Module Instance

Definition at line 400 of file simul_axi_hp_wr.v.

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The documentation for this Module was generated from the following files:

• simulation_modules/simul_axi_hp_wr.v