49 parameter MULT_SAXI_BSLOG0 =
4,
// number of bits to represent burst size (4 - b.s. = 16, 0 - b.s = 1) 53 parameter MULT_SAXI_MASK =
'h7f8,
// 4 address/length pairs. In bytes, but lower bits are set to 0? 56 parameter MULT_SAXI_ADV_WR =
4,
// number of clock cycles before end of write to genearte adv_wr_done 57 parameter MULT_SAXI_ADV_RD =
3 // number of clock cycles before end of write to genearte adv_wr_done 60 // input rst, // global reset 61 input mclk,
// system clock 62 input aclk,
// global clock to run s_axi (@150MHz?) 63 input mrst,
// @mclk sync reset 64 input arst,
// @aclk sync reset 66 input [
7:
0]
cmd_ad,
// byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 67 input cmd_stb,
// strobe (with first byte) for the command a/d 68 output [
7:
0]
status_ad,
// status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25] 69 output status_rq,
// input request to send status downstream 70 input status_start,
// Acknowledge of the first status packet byte (address) 72 output en_chn0,
// @mclk enable channel 0 input FIFO ( 0 - reset) 73 input has_burst0,
// channel has at least 1 burst (should go down immediately after read_burst0 if no more data) 74 output read_burst0,
// request to read a burst of data from channel 0 75 input [
31:
0]
data_in_chn0,
// data read from channel 0 (with some latency) 78 output en_chn1,
// @mclk enable channel 1 input FIFO ( 0 - reset) 79 input has_burst1,
// channel has at least 1 burst (should go down immediately after read_burst0 if no more data) 80 output read_burst1,
// request to read a burst of data from channel 0 81 input [
31:
0]
data_in_chn1,
// data read from channel 0 (with some latency) 84 output en_chn2,
// @mclk enable channel 2 input FIFO ( 0 - reset) 85 input has_burst2,
// channel has at least 1 burst (should go down immediately after read_burst0 if no more data) 86 output read_burst2,
// request to read a burst of data from channel 0 87 input [
31:
0]
data_in_chn2,
// data read from channel 0 (with some latency) 90 output en_chn3,
// @mclk enable channel 3 input FIFO ( 0 - reset) 91 input has_burst3,
// channel has at least 1 burst (should go down immediately after read_burst0 if no more data) 92 output read_burst3,
// request to read a burst of data from channel 0 93 input [
31:
0]
data_in_chn3,
// data read from channel 0 (with some latency) 96 // S_AXI inerface w/o read channel 98 output [
31:
0]
saxi_awaddr,
// AXI PS Slave GP0 AWADDR[31:0], input 101 output [
5:
0]
saxi_awid,
// AXI PS Slave GP0 AWID[5:0], input 105 output [
3:
0]
saxi_awlen,
// AXI PS Slave GP0 AWLEN[3:0], input 108 output [
3:
0]
saxi_awqos,
// AXI PS Slave GP0 AWQOS[3:0], input 110 output [
31:
0]
saxi_wdata,
// AXI PS Slave GP0 WDATA[31:0], input 113 output [
5:
0]
saxi_wid,
// AXI PS Slave GP0 WID[5:0], input 115 output [
3:
0]
saxi_wstrb,
// AXI PS Slave GP0 WSTRB[3:0], input 116 // write response Not used - may add guaranteed address (as for the histogram)? 117 input saxi_bvalid,
// AXI PS Slave GP0 BVALID, output // @SuppressThisWarning VEditor unused 119 input [
5:
0]
saxi_bid,
// AXI PS Slave GP0 BID[5:0], output //TODO: Update range !!! // @SuppressThisWarning VEditor unused 120 input [
1:
0]
saxi_bresp // AXI PS Slave GP0 BRESP[1:0], output // @SuppressThisWarning VEditor unused 122 // parameter MULT_SAXI_BSLOG0 = 4, // number of bits to represent burst size (4 - b.s. = 16, 0 - b.s = 1) 124 // localparam BURSTS_CAP0= (MULT_SAXI_HALF_BRAM ? 'h400 : 'h800 ) / MULT_SAXI_BURST0 / 4; 137 wire [
3:
0]
adv_wr_done;
// outputs grant_wr for short bursts, or several clocks before end of wr 149 reg [
31:
0]
buf_wd;
// multiplexed buffer write data 150 reg buf_we;
// multiplexed buffer write enable 159 reg [
2:
0]
buf_re;
// multiplexed buffer write enable 162 wire fifo_nempty;
// output FIFO saxi_wdata is not empty (can read) 163 wire [
3:
0]
wdata_busy_chn;
// output data busy (ends early to start next arbitration) 164 wire [
3:
0]
first_re;
// reading first word in a burst from the buffer 165 wire [
3:
0]
last_re;
// reading first word in a burst from the buffer 189 // Arbiter requests on copying from one of the input channels to the internal buffer 197 )
mult_saxi_wr_sub0_i (
222 )
mult_saxi_wr_sub1_i (
247 )
mult_saxi_wr_sub2_i (
272 )
mult_saxi_wr_sub3_i (
294 .
FIXED_PRIORITY (
0),
// 0 - round-robin, 1 - fixed channel priority (0 - highest) 295 .
BITS (
2)
// number of bits to encode channel number (1 << BITS) - number of inputs 296 )
round_robin_mclk_i (
298 .
srst (!
en_mclk),
// input sync. reset - needed to reset current channel output 300 .
en (
en_we_arb),
// input enable to grant highest priority request (should be reset by grant out) 303 .
grant_chn (
grant_wr)
// output[3:0] 1-hot grant output per-channel, single-clock pulse 306 // multiplex channel data to a common buffer 312 // Use advanced 'valid' signal (from the input channel external buffers) to copy we_cur_chn 313 // to chn_wr - that allows to start arbitration (that will result in modification of the we_cur_chn) 314 // early, before write operation to the buffer (using channel for multiplexing and address MSB) 321 // multiplex address and data 324 // early re-enable arbitration (en_we_arb) 330 // Buffer output to S_AXI (will need a smaller FIFO 334 reg [
1:
0]
is_last_rd;
// [1] accompanies last inter_buf_data in a burst (to generate wlast) 336 // wire is_last_fifo_out; // last data word out from fifo (for wlast) 346 // in parallel - read channel parameters (address, length, pointer) 353 .
FIXED_PRIORITY (
0),
// 0 - round-robin, 1 - fixed channel priority (0 - highest) 354 .
BITS (
2)
// number of bits to encode channel number (1 << BITS) - number of inputs 355 )
round_robin_aclk_i (
357 .
srst (!
en_aclk),
// input sync. reset - needed to reset current channel output 359 .
en (
en_out_arb),
// input enable to grant highest priority request (should be reset by grant out) 362 .
grant_chn (
grant_rd)
// output[3:0] 1-hot grant output per-channel, single-clock pulse 365 // Process address, length and current pointers (all in 32-bit words). Pointers are updated once per burst (parameter defined per each channel) 372 assign saxi_awlock=
2'h0;
// AXI PS Slave GP0 AWLOCK[1:0], input 374 assign saxi_awprot=
3'h0;
// AXI PS Slave GP0 AWPROT[2:0], input 375 assign saxi_awsize=
2'h2;
// 4 bytes; AXI PS Slave GP0 AWSIZE[1:0], input 376 assign saxi_awburst=
2'h1;
// Increment address bursts AXI PS Slave GP0 AWBURST[1:0], input 377 assign saxi_awqos=
4'h0;
// AXI PS Slave GP0 AWQOS[3:0], input 381 wire [
29:
0]
pntr_wd;
// @aclk, re-clock and write to status 390 )
mult_saxi_wr_pointers_i (
399 .
busy (
axi_ptr_busy),
// output OR this busy with write data channel busy for en_out_arb 400 .
axi_addr (
axi_addr),
// output[29:0] reg valid 2 cycles after start of grant_rd_any 407 // interface axi_aw channel 410 // wire aw_busy; // use to control en_out_arb = !(aw_busy || <data_channel_busy>); 422 // assign aw_busy = axi_ptr_busy | awvalid; 429 // s_axi write channel 430 // Small extra FIFO to tolerate ram_var_w_var_r latency 431 // assign fifo_re= saxi_wvalid && saxi_wready; 442 )
fifo_same_clock_i (
443 .
rst (
1'b0),
// rst), // input 461 )
ram_var_w_var_r_i (
470 .
web (
4'hf),
// input[7:0] 479 )
ram_var_w_var_r_i (
488 .
web (
8'hff),
// input[7:0] 503 )
cmd_deser_sens_i2c_i (
504 .
rst (
1'b0),
//rst), // input 514 // now - converting all to parallel (TODO: use RAM for multi-word status data) 538 .
REGISTER_STATUS (
1),
541 )
status_generate_i (
542 .
rst (
1'b0),
//rst), // input
[DATA_WIDTH-1:0] 10430data_in
876status_datawire[128:0]
[1 << LOG2WIDTH_WR-1:0] 11872data_in
cmd_deser_sens_i2c_i cmd_deser
826ra_chnwire[4*CHN_A_WDTH-1:0]
[14-LOG2WIDTH_WR:0] 11869waddr
842inter_buf_datawire[31:0]
[MULT_SAXI_HALF_BRAM?6:7:0] 721wa
[1 << LOG2WIDTH_WR-1:0] 11597data_in
mult_saxi_wr_sub3_i mult_saxi_wr_chn
[1 << LOG2WIDTH_RD-1:0] 11592data_out
[13-LOG2WIDTH_RD:0] 11589raddr
[ADDR_MASK2!=0?2:ADDR_MASK1!=0?1:0:0] 9935we
823wa_chnwire[4*CHN_A_WDTH-1:0]
status_generate_i status_generate
[1 << LOG2WIDTH_RD-1:0] 11867data_out
752MULT_SAXI_STATUS_REG'h34
[DATA_WIDTH-1:0] 9934data
834buf_wareg[BRAM_A_WDTH-1:0]
reg [1 << BITS -1:0] 10757grant_chn
841buf_rareg[BRAM_A_WDTH-1:0]
[14-LOG2WIDTH_RD:0] 11864raddr
[DATA_WIDTH-1:0] 10431data_out
846wdata_busy_chnwire[3:0]
[ADDR_WIDTH-1:0] 9933addr
[13-LOG2WIDTH_WR:0] 11594waddr
751MULT_SAXI_CNTRL_ADDR'h738
mult_saxi_wr_pointers_i mult_saxi_wr_pointers
ram_var_w_var_r_i ram_var_w_var_r[generate]
813BRAM_A_WDTHMULT_SAXI_HALF_BRAM?9:10
[MULT_SAXI_HALF_BRAM?6:7:0] 726ra
[ALL_BITS-1:0] 10777status
759MULT_SAXI_CNTRL_MASK'h7fe
ram_var_w_var_r_i ram18_var_w_var_r[generate]
status_wr_i pulse_cross_clock
round_robin_aclk_i round_robin
fifo_same_clock_i fifo_same_clock
814CHN_A_WDTHBRAM_A_WDTH - 2