mult_saxi_wr_chn Module Reference

Inheritance diagram for mult_saxi_wr_chn:

Collaboration diagram for mult_saxi_wr_chn:

Static Public Member Functions

Always Constructs
ALWAYS_30	( mclk )
ALWAYS_31	( aclk )

Public Attributes

Inputs
mclk
aclk
en
has_burst
valid
grant_wr
grant_out
fifo_half_full

Outputs
rq_wr
wa	[MULT_SAXI_HALF_BRAM?6: 7 : 0 ]
adv_wr_done	reg
rq_out	reg
ra	[MULT_SAXI_HALF_BRAM?6: 7 : 0 ]
pre_re
first_re	reg
last_re	reg
wdata_busy	reg

Parameters
MULT_SAXI_HALF_BRAM	1
MULT_SAXI_BSLOG	4
MULT_SAXI_ADV_WR	4
MULT_SAXI_ADV_RD	3
BURSTS_BITS	(MULT_SAXI_HALF_BRAM ? 9 : 10 ) - MULT_SAXI_BSLOG - 2
ADV_WR_COUNT	( 1 << MULT_SAXI_BSLOG ) - MULT_SAXI_ADV_WR
ADV_RD_COUNT	( 1 << MULT_SAXI_BSLOG ) - MULT_SAXI_ADV_RD

Signals
reg[BURSTS_BITS - 1 : 0 ]	wr_burst
reg[MULT_SAXI_BSLOG - 1 : 0 ]	wr_word
reg[BURSTS_BITS : 0 ]	wr_num_burst
reg[BURSTS_BITS - 1 : 0 ]	rd_burst
reg[MULT_SAXI_BSLOG - 1 : 0 ]	rd_word
reg[BURSTS_BITS : 0 ]	rd_num_burst
reg	rq_wr_r
reg	rq_wr_busy
wire	write_last_in_burst
wire	burst_written_aclk
wire	grant_out_mclk
reg	en_aclk
wire	last_word_busy
reg	pre_re_r
reg	out_busy
reg	early_busy

Module Instances
pulse_cross_clock::grant_out_mclk_i	Module pulse_cross_clock
pulse_cross_clock::write_last_in_burst_i	Module pulse_cross_clock

Detailed Description

Definition at line 41 of file mul_saxi_wr_chn.v.

Member Function Documentation

ALWAYS_30 (   mclk   )

Always Construct

Definition at line 108 of file mul_saxi_wr_chn.v.

ALWAYS_31 (   aclk   )

Always Construct

Definition at line 133 of file mul_saxi_wr_chn.v.

Member Data Documentation

MULT_SAXI_HALF_BRAM 1

Parameter

Definition at line 42 of file mul_saxi_wr_chn.v.

MULT_SAXI_BSLOG 4

Parameter

Definition at line 43 of file mul_saxi_wr_chn.v.

MULT_SAXI_ADV_WR 4

Parameter

Definition at line 44 of file mul_saxi_wr_chn.v.

MULT_SAXI_ADV_RD 3

Parameter

Definition at line 45 of file mul_saxi_wr_chn.v.

mclk

Input

Definition at line 47 of file mul_saxi_wr_chn.v.

aclk

Input

Definition at line 48 of file mul_saxi_wr_chn.v.

en

Input

Definition at line 49 of file mul_saxi_wr_chn.v.

has_burst

Input

Definition at line 50 of file mul_saxi_wr_chn.v.

valid

Input

Definition at line 53 of file mul_saxi_wr_chn.v.

rq_wr

Output

Definition at line 54 of file mul_saxi_wr_chn.v.

grant_wr

Input

Definition at line 55 of file mul_saxi_wr_chn.v.

wa [MULT_SAXI_HALF_BRAM?6: 7 : 0 ]

Output

Definition at line 56 of file mul_saxi_wr_chn.v.

adv_wr_done reg

Output

Definition at line 57 of file mul_saxi_wr_chn.v.

rq_out reg

Output

Definition at line 59 of file mul_saxi_wr_chn.v.

grant_out

Input

Definition at line 60 of file mul_saxi_wr_chn.v.

fifo_half_full

Input

Definition at line 61 of file mul_saxi_wr_chn.v.

ra [MULT_SAXI_HALF_BRAM?6: 7 : 0 ]

Output

Definition at line 62 of file mul_saxi_wr_chn.v.

pre_re

Output

Definition at line 63 of file mul_saxi_wr_chn.v.

first_re reg

Output

Definition at line 64 of file mul_saxi_wr_chn.v.

last_re reg

Output

Definition at line 65 of file mul_saxi_wr_chn.v.

wdata_busy reg

Output

Definition at line 67 of file mul_saxi_wr_chn.v.

BURSTS_BITS (MULT_SAXI_HALF_BRAM ? 9 : 10 ) - MULT_SAXI_BSLOG - 2

Parameter

Definition at line 70 of file mul_saxi_wr_chn.v.

wr_burst

Signal

Definition at line 72 of file mul_saxi_wr_chn.v.

wr_word

Signal

Definition at line 73 of file mul_saxi_wr_chn.v.

wr_num_burst

Signal

Definition at line 74 of file mul_saxi_wr_chn.v.

rd_burst

Signal

Definition at line 76 of file mul_saxi_wr_chn.v.

rd_word

Signal

Definition at line 77 of file mul_saxi_wr_chn.v.

rd_num_burst

Signal

Definition at line 78 of file mul_saxi_wr_chn.v.

rq_wr_r

Signal

Definition at line 79 of file mul_saxi_wr_chn.v.

rq_wr_busy

Signal

Definition at line 80 of file mul_saxi_wr_chn.v.

write_last_in_burst

Signal

Definition at line 85 of file mul_saxi_wr_chn.v.

burst_written_aclk

Signal

Definition at line 86 of file mul_saxi_wr_chn.v.

grant_out_mclk

Signal

Definition at line 89 of file mul_saxi_wr_chn.v.

en_aclk

Signal

Definition at line 90 of file mul_saxi_wr_chn.v.

last_word_busy

Signal

Definition at line 91 of file mul_saxi_wr_chn.v.

pre_re_r

Signal

Definition at line 92 of file mul_saxi_wr_chn.v.

out_busy

Signal

Definition at line 93 of file mul_saxi_wr_chn.v.

ADV_WR_COUNT ( 1 << MULT_SAXI_BSLOG ) - MULT_SAXI_ADV_WR

Parameter

Definition at line 104 of file mul_saxi_wr_chn.v.

ADV_RD_COUNT ( 1 << MULT_SAXI_BSLOG ) - MULT_SAXI_ADV_RD

Parameter

Definition at line 105 of file mul_saxi_wr_chn.v.

early_busy

Signal

Definition at line 131 of file mul_saxi_wr_chn.v.

pulse_cross_clock grant_out_mclk_i

Module Instance

Definition at line 169 of file mul_saxi_wr_chn.v.

pulse_cross_clock write_last_in_burst_i

Module Instance

Definition at line 177 of file mul_saxi_wr_chn.v.

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The documentation for this Module was generated from the following files:

• axi/mul_saxi_wr_chn.v