2462
[1 << LOG2WIDTH_WR-1:0] 11872data_in
[1 << LOG2WIDTH_WR-1:0] 11917data_in
[1 << LOG2WIDTH_RD-1:0] 11940data_out
[14-LOG2WIDTH_WR:0] 11869waddr
[1 << LOG2WIDTH_RD-1:0] 11893data_out
11901WIDTH_WR1 << LOG2WIDTH_WR
ramp_dummy_i ram_dummy[generate]
integer 11861LOG2WIDTH_RD6
integer 11860LOG2WIDTH_WR6
[14-LOG2WIDTH_WR:0] 11914waddr
[14-LOG2WIDTH_RD:0] 11926raddr
11900PWIDTH_RD(LOG2WIDTH_RD > 2)? (9 << (LOG2WIDTH_RD - 3)): (1 << LOG2WIDTH_RD
integer 11887LOG2WIDTH_WR5
[14-LOG2WIDTH_WR:0] 11895waddr
[14-LOG2WIDTH_RD:0] 11890raddr
11902WIDTH_RD1 << LOG2WIDTH_RD
11918PWIDTH_WR(LOG2WIDTH_WR > 2)? (9 << (LOG2WIDTH_WR - 3)): (1 << LOG2WIDTH_WR
ram_i ram_64w_lt64r[generate]
11903data_out32wire[31:0]
11938data_out32wire[31:0]
11904data_in_extwire[WIDTH_WR+31:0]
[1 << LOG2WIDTH_RD-1:0] 11867data_out
ram_i ram_64w_64r[generate]
[14-LOG2WIDTH_RD:0] 11864raddr
integer 11939LOG2WIDTH_RD5
11920WIDTH_WR1 << LOG2WIDTH_WR
ram_i ram_lt64w_lt64r[generate]
11937WIDTH_RD1 << LOG2WIDTH_RD
ram_i ram_lt64w_64r[generate]
11899PWIDTH_WR(LOG2WIDTH_WR > 2)? (9 << (LOG2WIDTH_WR - 3)): (1 << LOG2WIDTH_WR
[1 << LOG2WIDTH_RD-1:0] 11929data_out
[1 << LOG2WIDTH_WR-1:0] 11898data_in
11936PWIDTH_RD(LOG2WIDTH_RD > 2)? (9 << (LOG2WIDTH_RD - 3)): (1 << LOG2WIDTH_RD
11921data_in_extwire[WIDTH_WR+31:0]