Static Public Member Functions

Always Constructs
ALWAYS_32	( mclk )
ALWAYS_33	( mclk )
ALWAYS_34	( aclk )
ALWAYS_35	( aclk )
ALWAYS_36	( aclk )
ALWAYS_37	( mclk )

Public Attributes

Inputs
mclk
aclk
mrst
arst
cmd_ad	[ 7 : 0 ]
cmd_stb
status_start
has_burst0
data_in_chn0	[ 31 : 0 ]
pre_valid_chn0
has_burst1
data_in_chn1	[ 31 : 0 ]
pre_valid_chn1
has_burst2
data_in_chn2	[ 31 : 0 ]
pre_valid_chn2
has_burst3
data_in_chn3	[ 31 : 0 ]
pre_valid_chn3
saxi_awready
saxi_wready
saxi_bvalid
saxi_bid	[ 5 : 0 ]
saxi_bresp	[ 1 : 0 ]

Outputs
status_ad	[ 7 : 0 ]
status_rq
en_chn0
read_burst0
en_chn1
read_burst1
en_chn2
read_burst2
en_chn3
read_burst3
saxi_awaddr	[ 31 : 0 ]
saxi_awvalid
saxi_awid	[ 5 : 0 ]
saxi_awlock	[ 1 : 0 ]
saxi_awcache	[ 3 : 0 ]
saxi_awprot	[ 2 : 0 ]
saxi_awlen	[ 3 : 0 ]
saxi_awsize	[ 1 : 0 ]
saxi_awburst	[ 1 : 0 ]
saxi_awqos	[ 3 : 0 ]
saxi_wdata	[ 31 : 0 ]
saxi_wvalid
saxi_wid	[ 5 : 0 ]
saxi_wlast
saxi_wstrb	[ 3 : 0 ]
saxi_bready

Parameters
MULT_SAXI_ADDR	'h730
MULT_SAXI_CNTRL_ADDR	'h738
MULT_SAXI_STATUS_REG	'h34
MULT_SAXI_HALF_BRAM	1
MULT_SAXI_BSLOG0	4
MULT_SAXI_BSLOG1	4
MULT_SAXI_BSLOG2	4
MULT_SAXI_BSLOG3	4
MULT_SAXI_MASK	'h7f8
MULT_SAXI_CNTRL_MASK	'h7fe
MULT_SAXI_AWCACHE	4 'h3
MULT_SAXI_ADV_WR	4
MULT_SAXI_ADV_RD	3
BRAM_A_WDTH	MULT_SAXI_HALF_BRAM?9: 10
CHN_A_WDTH	BRAM_A_WDTH - 2

GENERATE
GENERATE [454]

Signals
wire[ 3 : 0 ]	en_chn_mclk
wire[ 3 : 0 ]	run_chn_mclk
reg[ 7 : 0 ]	mode_reg
wire	en_mclk
reg[ 3 : 0 ]	en_chn_aclk
wire	en_aclk
wire[ 3 : 0 ]	rq_wr
wire[ 3 : 0 ]	grant_wr
wire[ 4 CHN_A_WDTH* - 1 : 0 ]**	wa_chn
wire[ 3 : 0 ]	adv_wr_done
wire[ 3 : 0 ]	rq_out_chn
wire[ 4 CHN_A_WDTH* - 1 : 0 ]**	ra_chn
wire[ 3 : 0 ]	pre_re
reg	en_we_arb
wire	we_grant
wire[ 1 : 0 ]	we_cur_chn
wire[ 127 : 0 ]	data_in
wire[ 3 : 0 ]	pre_valid
reg[ 3 : 0 ]	valid
reg[BRAM_A_WDTH - 1 : 0 ]	buf_wa
reg[ 31 : 0 ]	buf_wd
reg	buf_we
wire[ 3 : 0 ]	grant_rd
wire	grant_rd_any
wire	en_out_arb
wire[ 1 : 0 ]	re_cur_chn
reg[BRAM_A_WDTH - 1 : 0 ]	buf_ra
wire[ 31 : 0 ]	inter_buf_data
reg[ 2 : 0 ]	buf_re
wire	fifo_half_full
wire	fifo_nempty
wire[ 3 : 0 ]	wdata_busy_chn
wire[ 3 : 0 ]	first_re
wire[ 3 : 0 ]	last_re
wire[ 3 : 0 ]	cmd_a
wire[ 31 : 0 ]	cmd_data
wire	we_ctrl
wire	cmd_we_sa_len
wire	pre_pre_buf_we
reg	pre_buf_we
reg[ 1 : 0 ]	chn_wr
reg[ 1 : 0 ]	chn_rd
reg[ 1 : 0 ]	chn_rd_data
reg	pre_first_rd_valid
reg[ 1 : 0 ]	is_last_rd
wire[ 1 : 0 ]	chn_fifo_out
wire	axi_ptr_busy
wire[ 29 : 0 ]	axi_addr
wire[ 3 : 0 ]	axi_len
wire[ 29 : 0 ]	pntr_wd
wire[ 1 : 0 ]	pntr_wa
wire	pntr_we
reg	awvalid
reg[ 2 : 0 ]	aw_seq
reg[ 1 : 0 ]	chn_out
wire	fifo_re
reg[ 29 : 0 ]	status_pntr0
reg[ 29 : 0 ]	status_pntr1
reg[ 29 : 0 ]	status_pntr2
reg[ 29 : 0 ]	status_pntr3
wire	pntr_we_mclk
wire[ 128 : 0 ]	status_data
reg	status_tgl

Module Instances
mult_saxi_wr_chn::mult_saxi_wr_sub0_i	Module mult_saxi_wr_chn
mult_saxi_wr_chn::mult_saxi_wr_sub1_i	Module mult_saxi_wr_chn
mult_saxi_wr_chn::mult_saxi_wr_sub2_i	Module mult_saxi_wr_chn
mult_saxi_wr_chn::mult_saxi_wr_sub3_i	Module mult_saxi_wr_chn
round_robin::round_robin_mclk_i	Module round_robin
round_robin::round_robin_aclk_i	Module round_robin
mult_saxi_wr_pointers::mult_saxi_wr_pointers_i	Module mult_saxi_wr_pointers
fifo_same_clock::fifo_same_clock_i	Module fifo_same_clock
ram18_var_w_var_r::ram_var_w_var_r_i	Module ram18_var_w_var_r [generate]
ram_var_w_var_r::ram_var_w_var_r_i	Module ram_var_w_var_r [generate]
cmd_deser::cmd_deser_sens_i2c_i	Module cmd_deser
pulse_cross_clock::status_wr_i	Module pulse_cross_clock
status_generate::status_generate_i	Module status_generate