43 parameter MULT_SAXI_BSLOG =
4,
// number of bits to represent burst size (4 - b.s. = 16, 0 - b.s = 1) 44 parameter MULT_SAXI_ADV_WR =
4,
// number of clock cycles before end of write to genearte adv_wr_done 45 parameter MULT_SAXI_ADV_RD =
3 // number of clock cycles before end of read to genearte wdata_busy (if !fifo_half_full) 47 input mclk,
// system clock 48 input aclk,
// global clock to run s_axi (@150MHz?) 49 input en,
// enable this channle ( 0 - reset) 50 input has_burst,
// channel has at least 1 burst (should go down immediately after read_burst if no more data) 51 // use grant_wr to request reading external data 52 // output read_burst, // request to read a burst of data from the channel 53 input valid,
// data valid (same latency) 54 output rq_wr,
// request to write to the buffer FIFO 57 output reg adv_wr_done,
// outputs grant_wr for short bursts, or several clocks before end of wr 58 // output pre_we, // will be registered after mux - use valid 61 input fifo_half_full,
// output fifo is half full - use it to suspend readout 63 output pre_re,
// will be registerd after the MUX 64 output reg first_re,
// reading first word (next cycle after corresponding pre_re) 65 output reg last_re,
// reading lastt word (next cycle after corresponding pre_re) 81 // reg early_wr_done; // single-cycle pulse several clock before end of write busy 83 // wire grant_wr_sngl; 84 // wire grant_wr_aclk; 88 // wire grant_out_sngl; 92 reg pre_re_r;
// may be interrupted if fifo_half_full 98 // assign grant_wr_sngl = grant_wr && !grant_wr_r; 99 // assign grant_out_sngl = grant_out && ~grant_out_r; 100 assign last_word_busy = &
wr_word ;
// make it earlier, use BURSTS_BITS selection (& (word | (1 <<???))) 117 // Number of bursts in fifo as seen from the input 135 // Number of bursts in fifo as seen from the output
736rd_wordreg[MULT_SAXI_BSLOG-1:0]
[MULT_SAXI_HALF_BRAM?6:7:0] 721wa
732wr_burstreg[BURSTS_BITS-1:0]
734wr_num_burstreg[BURSTS_BITS:0]
740write_last_in_burstwire
write_last_in_burst_i pulse_cross_clock
735rd_burstreg[BURSTS_BITS-1:0]
747ADV_WR_COUNT(1 << MULT_SAXI_BSLOG) - MULT_SAXI_ADV_WR
737rd_num_burstreg[BURSTS_BITS:0]
731BURSTS_BITS(MULT_SAXI_HALF_BRAM ? 9 : 10 ) - MULT_SAXI_BSLOG - 2
733wr_wordreg[MULT_SAXI_BSLOG-1:0]
748ADV_RD_COUNT(1 << MULT_SAXI_BSLOG) - MULT_SAXI_ADV_RD
[MULT_SAXI_HALF_BRAM?6:7:0] 726ra
741burst_written_aclkwire