par12_hispi_psp4l Member List

This is the complete list of members for par12_hispi_psp4l, including all inherited members.

EXTRA_DLY	pulse_cross_clock	Parameter
rst	pulse_cross_clock	Input
src_clk	pulse_cross_clock	Input
dst_clk	pulse_cross_clock	Input
in_pulse	pulse_cross_clock	Input
out_pulse	pulse_cross_clock	Output
busy	pulse_cross_clock	Output
EXTRA_DLY_SAFE	pulse_cross_clock	Parameter
in_reg	pulse_cross_clock	Signal
out_reg	pulse_cross_clock	Signal
busy_r	pulse_cross_clock	Signal
FULL_HEIGHT	par12_hispi_psp4l
CLOCK_MPY	par12_hispi_psp4l
CLOCK_DIV	par12_hispi_psp4l
LANE0_DLY	par12_hispi_psp4l
LANE1_DLY	par12_hispi_psp4l
LANE2_DLY	par12_hispi_psp4l
LANE3_DLY	par12_hispi_psp4l
CLK_DLY	par12_hispi_psp4l
EMBED_LINES	par12_hispi_psp4l
MSB_FIRST	par12_hispi_psp4l
FIFO_LOGDEPTH	par12_hispi_psp4l
pclk	par12_hispi_psp4l
rst	par12_hispi_psp4l
pxd	par12_hispi_psp4l
vact	par12_hispi_psp4l
hact_in	par12_hispi_psp4l
lane_p	par12_hispi_psp4l
lane_n	par12_hispi_psp4l
clk_p	par12_hispi_psp4l
clk_n	par12_hispi_psp4l
FIFO_DEPTH	par12_hispi_psp4l
SYNC_SOF	par12_hispi_psp4l
SYNC_SOL	par12_hispi_psp4l
SYNC_EOF	par12_hispi_psp4l
SYNC_EOL	par12_hispi_psp4l
lines_left	par12_hispi_psp4l
pre_lines	par12_hispi_psp4l
lane_pcntr	par12_hispi_psp4l
hact	par12_hispi_psp4l
image_lines	par12_hispi_psp4l
vact_d	par12_hispi_psp4l
pxd_d	par12_hispi_psp4l
fifo_di	par12_hispi_psp4l
fifo_we	par12_hispi_psp4l
hact_d	par12_hispi_psp4l
next_sof	par12_hispi_psp4l
next_line_pclk	par12_hispi_psp4l
next_frame_pclk	par12_hispi_psp4l
pre_fifo_we_eof_w	par12_hispi_psp4l
pre_fifo_we_sof_sol_w	par12_hispi_psp4l
pre_fifo_we_data_w	par12_hispi_psp4l
pre_fifo_we_w	par12_hispi_psp4l
fifo_ram	par12_hispi_psp4l
fifo_wa	par12_hispi_psp4l
oclk	par12_hispi_psp4l
next_line_oclk	par12_hispi_psp4l
next_frame_oclk	par12_hispi_psp4l
orst_r	par12_hispi_psp4l
orst	par12_hispi_psp4l
rdy	par12_hispi_psp4l
sdata	par12_hispi_psp4l
sdata_dly	par12_hispi_psp4l
fifo_ra	par12_hispi_psp4l
fifo_out	par12_hispi_psp4l
fifo_dav	par12_hispi_psp4l
sof_sol_sent	par12_hispi_psp4l
lines_available	par12_hispi_psp4l
line_available	par12_hispi_psp4l
frames_open	par12_hispi_psp4l
eof_sent	par12_hispi_psp4l
clk_pn	par12_hispi_psp4l
clk_pn_dly	par12_hispi_psp4l
SYNC_SOF	par12_hispi_psp4l_lane	Parameter
SYNC_SOL	par12_hispi_psp4l_lane	Parameter
SYNC_EOF	par12_hispi_psp4l_lane	Parameter
SYNC_EOL	par12_hispi_psp4l_lane	Parameter
IDL	par12_hispi_psp4l_lane	Parameter
MSB_FIRST	par12_hispi_psp4l_lane	Parameter
clk	par12_hispi_psp4l_lane	Input
rst	par12_hispi_psp4l_lane	Input
din	par12_hispi_psp4l_lane	Input
dav	par12_hispi_psp4l_lane	Input
next_line	par12_hispi_psp4l_lane	Input
sof_sol_sent	par12_hispi_psp4l_lane	Output
rdy	par12_hispi_psp4l_lane	Output
sout	par12_hispi_psp4l_lane	Output
sr	par12_hispi_psp4l_lane	Signal
sr_in	par12_hispi_psp4l_lane	Signal
sr_in_av	par12_hispi_psp4l_lane	Signal
bcntr	par12_hispi_psp4l_lane	Signal
seq_sof	par12_hispi_psp4l_lane	Signal
seq_eof	par12_hispi_psp4l_lane	Signal
seq_eol_sol	par12_hispi_psp4l_lane	Signal
embed	par12_hispi_psp4l_lane	Signal
dav_rdy	par12_hispi_psp4l_lane	Signal
is_sync	par12_hispi_psp4l_lane	Signal
din_filt	par12_hispi_psp4l_lane	Signal
pause	par12_hispi_psp4l_lane	Signal
FRAC_DELAY	sim_frac_clk_delay	Parameter
SKIP_FIRST	sim_frac_clk_delay	Parameter
clk	sim_frac_clk_delay	Input
din	sim_frac_clk_delay	Input
dout	sim_frac_clk_delay	Output
INT_DELAY	sim_frac_clk_delay	Parameter
HALF_DELAY	sim_frac_clk_delay	Parameter
RDELAY	sim_frac_clk_delay	Parameter
num_period	sim_frac_clk_delay	Signal
en	sim_frac_clk_delay	Signal
phase	sim_frac_clk_delay	Signal
prev_phase	sim_frac_clk_delay	Signal
frac_period	sim_frac_clk_delay	Signal
sr	sim_frac_clk_delay	Signal
sr_fract	sim_frac_clk_delay	Signal
taps	sim_frac_clk_delay	Signal
taps_fract	sim_frac_clk_delay	Signal
dly_half	sim_frac_clk_delay	Signal
MULTIPLIER	simul_clk_mult_div	Parameter
DIVISOR	simul_clk_mult_div	Parameter
SKIP_FIRST	simul_clk_mult_div	Parameter
clk_in	simul_clk_mult_div	Input
en	simul_clk_mult_div	Input
clk_out	simul_clk_mult_div	Output
clk_int	simul_clk_mult_div	Signal
ALWAYS_398 pclk	par12_hispi_psp4l	Always Construct
ALWAYS_399 pclk	par12_hispi_psp4l	Always Construct
ALWAYS_400 pclk	par12_hispi_psp4l	Always Construct
ALWAYS_401 oclk	par12_hispi_psp4l	Always Construct
ALWAYS_402 oclk	par12_hispi_psp4l	Always Construct
ALWAYS_403 oclk	par12_hispi_psp4l	Always Construct
ALWAYS_404 clk	par12_hispi_psp4l_lane	Always Construct
ALWAYS_406 clk	sim_frac_clk_delay	Always Construct
ALWAYS_407 clk	sim_frac_clk_delay	Always Construct
ALWAYS_408 clk	sim_frac_clk_delay	Always Construct
ALWAYS_532 src_clk or rst	pulse_cross_clock	Always Construct
ALWAYS_533 dst_clk	pulse_cross_clock	Always Construct
GENERATE [191]	par12_hispi_psp4l
GENERATE [51]	simul_clk_mult_div	GENERATE
GENERATE [64]	simul_clk_mult_div	GENERATE
par12_hispi_psp4l_lane	par12_hispi_psp4l
pulse_cross_clock	par12_hispi_psp4l
pulse_cross_clock	par12_hispi_psp4l
sim_clk_div	simul_clk_mult_div	Module Instance
sim_frac_clk_delay	par12_hispi_psp4l
sim_frac_clk_delay	par12_hispi_psp4l
sim_frac_clk_delay	par12_hispi_psp4l
sim_frac_clk_delay	par12_hispi_psp4l
sim_frac_clk_delay	par12_hispi_psp4l
simul_clk_mult	simul_clk_mult_div	Module Instance
simul_clk_mult_div	par12_hispi_psp4l