x393
1.0
FPGAcodeforElphelNC393camera
Design Unit List
Here is a list of all design unit members with links to the Modules they belong to:
[detail level
1
2
]
►
N
socket_command
C
SocketCommand
C
x393Client
►
N
x393_cocotb_server
C
X393_cocotb_server
►
N
x393interfaces
C
MAXIGPReadError
C
PSBus
C
SAXIRdSim
C
SAXIWrSim
C
action_decoder
C
ahci_ctrl_stat
C
ahci_dma
C
ahci_dma_rd_fifo
C
ahci_dma_rd_stuff
C
ahci_dma_wr_fifo
C
ahci_fis_receive
C
ahci_fis_transmit
C
ahci_fsm
C
ahci_sata_layers
C
ahci_top
C
axi_ahci_regs
C
axi_hp_abort
C
axi_hp_clk
C
axibram_read
C
axibram_write
C
bit_stuffer_27_32
C
bit_stuffer_escape
C
bit_stuffer_metadata
C
buf_xclk_mclk16_393
C
byte_lane
C
camsync393
C
clk_to_clk2x
C
clock_divider
C
clock_inverter
C
clocks393
C
clocks393m
C
cmd_addr
C
cmd_deser
C
cmd_deser_dual
C
cmd_deser_multi
C
cmd_deser_single
C
cmd_encod_4mux
C
cmd_encod_linear_mux
C
cmd_encod_linear_rd
C
cmd_encod_linear_rw
C
cmd_encod_linear_wr
C
cmd_encod_tiled_32_rd
C
cmd_encod_tiled_32_rw
C
cmd_encod_tiled_32_wr
C
cmd_encod_tiled_mux
C
cmd_encod_tiled_rd
C
cmd_encod_tiled_rw
C
cmd_encod_tiled_wr
C
cmd_frame_sequencer
C
cmd_mux
C
cmd_readback
C
cmd_seq_mux
C
cmda_single
C
cmprs_afi_mux
C
cmprs_afi_mux_ptr
C
cmprs_afi_mux_ptr_wresp
C
cmprs_afi_mux_status
C
cmprs_buf_average
C
cmprs_cmd_decode
C
cmprs_frame_sync
C
cmprs_macroblock_buf_iface
C
cmprs_out_fifo
C
cmprs_out_fifo32
C
cmprs_pixel_buf_iface
C
cmprs_status
C
cmprs_tile_mode2_decode
C
cmprs_tile_mode_decode
C
compressor393
C
condition_mux
C
crc
C
csconvert
C
csconvert18a
C
csconvert_jp4
C
csconvert_jp4diff
C
csconvert_mono
C
datascope_incoming
C
datascope_incoming_raw
C
datascope_timing
C
dcc_sync393
C
dci_reset
C
dct1d_chen
C
dct1d_chen_reorder_in
C
dct1d_chen_reorder_out
C
dct2d8x8_chen
C
dct_chen_transpose
C
ddr3_wrap
C
ddr_refresh
C
debug_master
C
debug_slave
C
dly01_16
C
dly_16
C
dm_single
C
dq_single
C
dqs_single
C
dqs_single_nofine
C
drp_other_registers
C
dsp_addsub_simd
C
dsp_ma
C
dsp_ma_preadd
C
dual_clock_source
C
elastic1632
C
elastic_cross_clock
C
encoderDCAC393
C
event_logger
C
fifo_1cycle
C
fifo_2regs
C
fifo_cross_clocks
C
fifo_same_clock
C
fifo_same_clock_fill
C
fifo_sameclock_control
C
focus_sharp393
C
frame_num_sync
C
freq_meter
C
gpio393
C
gpio_bit
C
gtx_10x8dec
C
gtx_8x10enc
C
gtx_comma_align
C
gtx_elastic
C
gtx_wrap
C
gtxe2_channel_wrapper
C
gtxe2_chnl
C
gtxe2_chnl_clocking
C
gtxe2_chnl_cpll
C
gtxe2_chnl_cpll_inmux
C
gtxe2_chnl_outclk_mux
C
gtxe2_chnl_rx
C
gtxe2_chnl_rx_10x8dec
C
gtxe2_chnl_rx_align
C
gtxe2_chnl_rx_dataiface
C
gtxe2_chnl_rx_des
C
gtxe2_chnl_rx_oob
C
gtxe2_chnl_tx
C
gtxe2_chnl_tx_8x10enc
C
gtxe2_chnl_tx_dataiface
C
gtxe2_chnl_tx_oob
C
gtxe2_chnl_tx_ser
C
GTXE2_GPL
C
histogram_saxi
C
huff_fifo393
C
huffman393
C
huffman_merge_code_literal
C
huffman_snglclk
C
huffman_stuffer_meta
C
ibuf_ibufg
C
ibufds_ibufgds
C
ibufds_ibufgds_50
C
IBUFG
C
ibufg
C
IBUFGDS
C
ibufgds
C
idelay_ctrl
C
idelay_fine_pipe
C
idelay_nofine
C
imu_exttime393
C
imu_message393
C
imu_spi393
C
imu_timestamps393
C
index_max_16
C
iobuf
C
iserdes_mem
C
jp_channel
C
latch_g_ce
C
lens_flat393
C
lens_flat393_line
C
level_cross_clocks
C
level_cross_clocks_ff_bit
C
level_cross_clocks_single_bit
C
level_cross_clocks_sync_bit
C
link
C
logger_arbiter393
C
masked_max_reg
C
mcntrl393
C
mcntrl393_test01
C
mcntrl_1kx32r
C
mcntrl_1kx32w
C
mcntrl_buf_rd
C
mcntrl_buf_wr
C
mcntrl_linear_rw
C
mcntrl_ps_pio
C
mcntrl_tiled_rw
C
mcont_common_chnbuf_reg
C
mcont_from_chnbuf_reg
C
mcont_to_chnbuf_reg
C
mcontr_sequencer
C
membridge
C
memctrl16
C
mmcm_adv
C
mmcm_phase_cntr
C
mpullup
C
mult_saxi_wr
C
mult_saxi_wr_chn
C
mult_saxi_wr_inbuf
C
mult_saxi_wr_pointers
C
multipulse_cross_clock
C
nmea_decoder393
C
obuf
C
obufds
C
oddr
C
oddr_ds
C
oddr_ss
C
odelay_fine_pipe
C
odelay_pipe
C
oob
C
oob_ctrl
C
oob_dev
C
oserdes_mem
C
par12_hispi_psp4l
C
par12_hispi_psp4l_lane
C
phy_cmd
C
phy_top
C
pll_base
C
pri1hot16
C
pulse_cross_clock
C
pxd_clock
C
pxd_single
C
quantizer393
C
ram18_32w_32r
C
ram18_32w_lt32r
C
ram18_dummy
C
ram18_lt32w_32r
C
ram18_lt32w_lt32r
C
ram18_var_w_var_r
C
ram18p_32w_32r
C
ram18p_32w_lt32r
C
ram18p_dummy
C
ram18p_lt32w_32r
C
ram18p_lt32w_lt32r
C
ram18p_var_w_var_r
C
ram18t_var_w_var_r
C
ram18tp_var_w_var_r
C
ram_1kx32_1kx32
C
ram_1kx32w_512x64r
C
ram_512x64w_1kx32r
C
ram_64w_64r
C
ram_64w_lt64r
C
ram_dummy
C
ram_lt64w_64r
C
ram_lt64w_lt64r
C
ram_var_w_var_r
C
ramp_64w_64r
C
ramp_64w_lt64r
C
ramp_dummy
C
ramp_lt64w_64r
C
ramp_lt64w_lt64r
C
ramp_var_w_var_r
C
ramt_var_w_var_r
C
ramt_var_wb_var_r
C
ramtp_var_w_var_r
C
resync_data
C
resync_fifo_nonsynt
C
round_robin
C
rs232_rcv393
C
rtc393
C
sata_ahci_top
C
sata_phy
C
sata_phy_dev
C
scheduler16
C
scrambler
C
select_clk_buf
C
sens_10398
C
sens_gamma
C
sens_hispi12l4
C
sens_hispi_clock
C
sens_hispi_din
C
sens_hispi_fifo
C
sens_hispi_lane
C
sens_hist_ram_double
C
sens_hist_ram_nobuff
C
sens_hist_ram_single
C
sens_hist_ram_snglclk_18
C
sens_hist_ram_snglclk_32
C
sens_histogram
C
sens_histogram_dummy
C
sens_histogram_mux
C
sens_histogram_snglclk
C
sens_histogram_snglclk_dummy
C
sens_parallel12
C
sens_sync
C
sensor_channel
C
sensor_fifo
C
sensor_i2c
C
sensor_i2c_io
C
sensor_i2c_prot
C
sensor_i2c_scl_sda
C
sensor_membuf
C
sensors393
C
sim_clk_div
C
sim_frac_clk_delay
C
sim_soc_interrupts
C
simul_axi_fifo
C
simul_axi_hp_rd
C
simul_axi_hp_wr
C
simul_axi_master_rdaddr
C
simul_axi_master_wdata
C
simul_axi_master_wraddr
C
simul_axi_read
C
simul_axi_slow_ready
C
simul_clk
C
simul_clk_div_mult
C
simul_clk_mult
C
simul_clk_mult_div
C
simul_clk_single
C
simul_fifo
C
simul_saxi_gp_wr
C
simul_sensor12bits
C
status_generate
C
status_generate_extra
C
status_generate_only
C
status_read
C
status_router16
C
status_router2
C
status_router4
C
status_router8
C
stuffer393
C
sync_resets
C
table_ad_receive
C
table_ad_transmit
C
timestamp_fifo
C
timestamp_snapshot
C
timestamp_to_parallel
C
timestamp_to_serial
C
timing393
C
varlen_encode393
C
varlen_encode_snglclk
C
x393
C
x393_dut
C
zigzag393
Generated by
1.8.12
1.8.12 1.8.12