- n -

• n000 : csconvert , csconvert18a , jp_channel , quantizer393
• n000_r : csconvert18a
• n255 : csconvert , csconvert18a , jp_channel , quantizer393
• n255_r : csconvert18a
• n_block_rows_m1 : cmprs_cmd_decode , cmprs_macroblock_buf_iface , jp_channel
• n_blocks_in_row_m1 : cmprs_cmd_decode , cmprs_macroblock_buf_iface , jp_channel
• n_chn : scheduler16
• n_xfpgatdo : sens_parallel12
• name : PSBus , SAXIRdSim , SAXIWrSim
• NB_ND : condition_mux
• NB_ND_D2HR_PIO : condition_mux
• nbpf : simul_sensor12bits
• ncols : simul_sensor12bits
• ndq : oddr_ds
• ndqs : byte_lane , dqs_single , dqs_single_nofine
• NDQSL : ddr3_wrap , mcntrl393 , mcontr_sequencer , memctrl16 , phy_cmd
• ndqsl : phy_top
• NDQSL : x393 , x393_dut
• NDQSL_D : ddr3_wrap
• NDQSL_DH1 : ddr3_wrap
• NDQSL_DH2 : ddr3_wrap
• NDQSL_DH3 : ddr3_wrap
• NDQSL_H1 : ddr3_wrap
• NDQSL_H2 : ddr3_wrap
• NDQSL_H3 : ddr3_wrap
• NDQSU : ddr3_wrap , mcntrl393 , mcontr_sequencer , memctrl16 , phy_cmd
• ndqsu : phy_top
• NDQSU : x393 , x393_dut
• NDQSU_D : ddr3_wrap
• NDQSU_DH1 : ddr3_wrap
• NDQSU_DH2 : ddr3_wrap
• NDQSU_DH3 : ddr3_wrap
• NDQSU_H1 : ddr3_wrap
• NDQSU_H2 : ddr3_wrap
• NDQSU_H3 : ddr3_wrap
• need : ddr_refresh , memctrl16 , scheduler16
• need_conf : scheduler16
• need_corr_max : focus_sharp393
• need_dly : index_max_16
• need_fifo : ahci_dma_wr_fifo
• need_in : index_max_16
• need_out : index_max_16
• need_r : mcntrl_linear_rw , mcntrl_tiled_rw , scheduler16
• need_r2 : scheduler16
• need_reset : gtxe2_chnl_rx_dataiface , gtxe2_chnl_rx_des
• need_rq : mcntrl_ps_pio , memctrl16 , scheduler16
• need_rq0 : mcntrl393 , memctrl16
• need_rq1 : mcntrl393 , memctrl16
• need_rq10 : memctrl16
• need_rq11 : memctrl16
• need_rq12 : memctrl16
• need_rq13 : memctrl16
• need_rq14 : memctrl16
• need_rq15 : memctrl16
• need_rq2 : mcntrl393 , memctrl16
• need_rq3 : mcntrl393 , memctrl16
• need_rq4 : mcntrl393 , memctrl16
• need_rq5 : memctrl16
• need_rq6 : memctrl16
• need_rq7 : memctrl16
• need_rq8 : memctrl16
• need_rq9 : memctrl16
• need_set : scheduler16
• need_some : scheduler16
• need_to_bother : cmprs_afi_mux , cmprs_afi_mux_ptr
• need_to_send : status_generate_extra , status_generate_only
• need_want_conf : scheduler16
• need_want_conf_d : scheduler16
• need_want_conf_w : scheduler16
• needed_page : cmprs_macroblock_buf_iface
• neg_m : dsp_ma , dsp_ma_preadd
• neg_r : clock_inverter
• nempty : fifo_1cycle , fifo_cross_clocks , fifo_same_clock , fifo_same_clock_fill , fifo_sameclock_control , huff_fifo393 , sensor_fifo
• nempty_r : huff_fifo393
• new_bayer : simul_sensor12bits
• new_bit : crc
• newline : lens_flat393
• next : lens_flat393_line , scrambler
• next_ac : focus_sharp393
• next_acc : rtc393
• next_addr : status_generate_extra
• next_bank_w : cmd_encod_tiled_32_rd , cmd_encod_tiled_32_wr , cmd_encod_tiled_rd , cmd_encod_tiled_wr
• next_byte_wr : sensor_i2c_prot
• next_chn : round_robin , status_router2
• next_cmd : sensor_i2c_prot
• next_cmd_d : sensor_i2c_prot
• next_d : lens_flat393_line
• next_disparity : gtxe2_chnl_tx , gtxe2_chnl_tx_8x10enc
• next_do : focus_sharp393
• next_fill : fifo_1cycle , fifo_same_clock_fill
• next_frame_oclk : par12_hispi_psp4l
• next_frame_pclk : par12_hispi_psp4l
• next_frame_rq : cmd_frame_sequencer
• next_frame_start_addr : mcntrl_linear_rw , mcntrl_tiled_rw
• next_invalid : cmprs_macroblock_buf_iface
• next_line : par12_hispi_psp4l_lane
• next_line_oclk : par12_hispi_psp4l
• next_line_pclk : par12_hispi_psp4l
• next_mask : status_generate_extra
• next_need_conf : scheduler16
• next_or_empty : ahci_dma_rd_stuff
• next_page : compressor393 , mcntrl_linear_rw , mcntrl_tiled_rw , membridge
• next_page_chn : cmprs_macroblock_buf_iface , jp_channel , membridge
• next_page_chn1 : mcntrl393 , mcntrl393_test01 , x393
• next_page_chn1_r : mcntrl393_test01
• next_page_chn2 : mcntrl393 , mcntrl393_test01 , x393
• next_page_chn2_r : mcntrl393_test01
• next_page_chn3 : mcntrl393 , mcntrl393_test01 , x393
• next_page_chn3_r : mcntrl393_test01
• next_page_chn4 : mcntrl393 , mcntrl393_test01 , x393
• next_page_chn4_r : mcntrl393_test01
• next_page_rd : membridge
• next_page_rd_w : membridge
• next_page_wr : membridge
• next_page_wr_w : membridge
• next_prim_loaded : gtx_elastic
• next_rd_address : simul_axi_hp_rd
• next_rd_address_w : axibram_read
• next_rowcol_w : cmd_encod_tiled_32_rd , cmd_encod_tiled_32_wr , cmd_encod_tiled_rd , cmd_encod_tiled_wr
• next_sof : par12_hispi_psp4l
• next_valid : cmprs_macroblock_buf_iface
• next_want_conf : scheduler16
• next_wcntr : ahci_dma_wr_fifo
• next_will_be_data : link
• next_with_requested : simul_axi_hp_rd
• next_wr_address : simul_axi_hp_wr
• next_wr_address_w : axibram_write , simul_saxi_gp_wr
• next_y : mcntrl_linear_rw , mcntrl_tiled_rw
• next_zero_w : cmd_encod_linear_wr
• nfp : ahci_dma_wr_fifo
• ngp1 : simul_sensor12bits
• nhrst_r : sata_ahci_top
• nibble : nmea_decoder393
• nibble_count : nmea_decoder393
• nibble_pre : nmea_decoder393
• nibble_stb : nmea_decoder393
• nmea_data : event_logger
• nmea_decoder393 : event_logger
• nmea_sent_start : event_logger , nmea_decoder393
• nmrst : cmprs_macroblock_buf_iface
• NMRST : simul_sensor12bits
• no_disp_word : gtxe2_chnl_rx_10x8dec
• no_new_data_r : ahci_dma_rd_stuff
• no_new_data_w : ahci_dma_rd_stuff
• NO_WRITE_ADDR : cmd_encod_linear_wr
• nocomwake : oob_dev
• nocomwake_timer : oob_dev
• not_in_table : datascope_incoming , datascope_incoming_raw
• notintable : gtx_10x8dec
• notintable_in : elastic1632 , gtx_elastic
• notintable_in_r : elastic1632
• notintable_out : elastic1632 , gtx_elastic
• now : scrambler
• NPCMD_FRE : condition_mux
• NPD : condition_mux
• NPD_NCA : condition_mux
• nreset : histogram_saxi
• nreset_aclk : histogram_saxi
• nreset_page_fifo : mcntrl_ps_pio
• nreset_page_fifo_neg : mcntrl_ps_pio
• nrowa : simul_sensor12bits
• nrowb : simul_sensor12bits
• nrows : simul_sensor12bits
• NST_D2HR : condition_mux
• num128 : cmd_encod_linear_mux , cmd_encod_linear_rd , cmd_encod_linear_wr
• num128_1 : cmd_encod_linear_mux
• num128_10 : cmd_encod_linear_mux
• num128_11 : cmd_encod_linear_mux
• num128_3 : cmd_encod_linear_mux
• num128_8 : cmd_encod_linear_mux
• num128_9 : cmd_encod_linear_mux
• num128_in : cmd_encod_linear_rd , cmd_encod_linear_rw , cmd_encod_linear_wr
• num128_r : cmd_encod_linear_mux
• num128_w : cmd_encod_linear_mux
• num_addr_saxi : histogram_saxi
• num_bursts_in_buf : histogram_saxi
• num_bursts_pending : histogram_saxi
• NUM_BYTES : status_generate_extra , status_generate_only
• num_bytes_send : sensor_i2c_prot
• NUM_CHANNELS : table_ad_transmit
• NUM_CHN : table_ad_receive
• num_cols : cmd_encod_tiled_mux
• num_cols12 : cmd_encod_tiled_mux
• num_cols128_m1 : cmd_encod_tiled_32_wr , cmd_encod_tiled_rd , cmd_encod_tiled_wr
• num_cols128_m2 : cmd_encod_tiled_32_rd
• num_cols13 : cmd_encod_tiled_mux
• num_cols14 : cmd_encod_tiled_mux
• num_cols15 : cmd_encod_tiled_mux
• num_cols2 : cmd_encod_tiled_mux
• num_cols4 : cmd_encod_tiled_mux
• num_cols_in_m1 : cmd_encod_tiled_32_rd , cmd_encod_tiled_32_rw , cmd_encod_tiled_32_wr , cmd_encod_tiled_rd , cmd_encod_tiled_rw , cmd_encod_tiled_wr
• num_cols_m1 : mcntrl_tiled_rw
• num_cols_m1_w : mcntrl_tiled_rw
• num_cols_r : cmd_encod_tiled_mux , mcntrl_tiled_rw
• num_cols_w : cmd_encod_tiled_mux
• NUM_CON_ALIGNS : oob
• NUM_CYCLES : cmd_deser , cmd_deser_multi
• NUM_CYCLES_00 : cmd_mux
• NUM_CYCLES_01 : cmd_mux
• NUM_CYCLES_02 : cmd_mux
• NUM_CYCLES_03 : cmd_mux
• NUM_CYCLES_04 : cmd_mux
• NUM_CYCLES_05 : cmd_mux
• NUM_CYCLES_06 : cmd_mux
• NUM_CYCLES_07 : cmd_mux
• NUM_CYCLES_08 : cmd_mux
• NUM_CYCLES_09 : cmd_mux
• NUM_CYCLES_10 : cmd_mux
• NUM_CYCLES_11 : cmd_mux
• NUM_CYCLES_12 : cmd_mux
• NUM_CYCLES_13 : cmd_mux
• NUM_CYCLES_14 : cmd_mux
• NUM_CYCLES_15 : cmd_mux
• NUM_CYCLES_16 : cmd_mux
• NUM_CYCLES_17 : cmd_mux
• NUM_CYCLES_18 : cmd_mux
• NUM_CYCLES_19 : cmd_mux
• NUM_CYCLES_20 : cmd_mux
• NUM_CYCLES_21 : cmd_mux
• NUM_CYCLES_22 : cmd_mux
• NUM_CYCLES_23 : cmd_mux
• NUM_CYCLES_24 : cmd_mux
• NUM_CYCLES_25 : cmd_mux
• NUM_CYCLES_26 : cmd_mux
• NUM_CYCLES_27 : cmd_mux
• NUM_CYCLES_28 : cmd_mux
• NUM_CYCLES_29 : cmd_mux
• NUM_CYCLES_30 : cmd_mux
• NUM_CYCLES_31 : cmd_mux
• NUM_CYCLES_LOW_BIT : cmd_mux
• NUM_DATA : dsp_addsub_simd
• num_data_saxi : histogram_saxi
• num_first_zeros : sens_hispi_lane
• NUM_FRAME_BITS : cmprs_status , frame_num_sync , sensor_channel , sensor_i2c , sensor_i2c_io , sensors393
• num_full_data : simul_axi_hp_wr , simul_saxi_gp_wr
• NUM_INTERRUPTS : sim_soc_interrupts
• num_lead_0_w : sens_hispi_lane
• num_lead_1_w : sens_hispi_lane
• NUM_MSG : status_generate_extra
• NUM_NIBBLES : datascope_incoming
• num_out_bursts : mult_saxi_wr_inbuf
• num_period : sim_frac_clk_delay , simul_clk_mult
• num_pulses : multipulse_cross_clock
• NUM_RC_BURST_BITS : mcntrl_linear_rw , mcntrl_tiled_rw
• num_rows : cmd_encod_tiled_mux
• num_rows12 : cmd_encod_tiled_mux
• num_rows13 : cmd_encod_tiled_mux
• num_rows14 : cmd_encod_tiled_mux
• num_rows15 : cmd_encod_tiled_mux
• num_rows2 : cmd_encod_tiled_mux
• num_rows4 : cmd_encod_tiled_mux
• num_rows_in_m1 : cmd_encod_tiled_32_rd , cmd_encod_tiled_32_rw , cmd_encod_tiled_32_wr , cmd_encod_tiled_rd , cmd_encod_tiled_rw , cmd_encod_tiled_wr
• num_rows_m1 : cmd_encod_tiled_32_rd , cmd_encod_tiled_32_wr , cmd_encod_tiled_rd , cmd_encod_tiled_wr , mcntrl_tiled_rw
• num_rows_m1_w : mcntrl_tiled_rw
• num_rows_r : cmd_encod_tiled_mux
• num_rows_w : cmd_encod_tiled_mux
• num_running_ones : sens_hispi_lane
• num_running_zeros : sens_hispi_lane
• num_running_zeros_w : sens_hispi_lane
• num_trail_0_w : sens_hispi_lane
• num_trail_1_w : sens_hispi_lane
• NUM_XFER_BITS : cmd_encod_linear_rd , cmd_encod_linear_rw , cmd_encod_linear_wr , mcntrl393 , mcntrl_linear_rw
• num_zeros_w : bit_stuffer_escape
• nVLO : simul_sensor12bits
• nxt : logger_arbiter393
• nxtline : csconvert18a