- r -

• r : simul_sensor12bits
• r0 : sens_histogram_snglclk
• r0_sel : sens_histogram_snglclk
• r1 : sens_histogram_snglclk
• r1_sat : sens_histogram_snglclk
• r2 : sens_histogram_snglclk
• r3 : sens_histogram_snglclk
• r_clk : clk_to_clk2x
• r_clk2x : clk_to_clk2x
• r_count : axi_hp_abort
• R_ERR : action_decoder
• R_ERR_PRIM : datascope_incoming
• R_IP_PRIM : datascope_incoming
• r_load : sens_histogram_snglclk
• r_nclk2x : clk_to_clk2x
• r_nempty : simul_axi_hp_rd
• R_OK : action_decoder
• R_OK_PRIM : datascope_incoming
• R_RDY_PRIM : datascope_incoming
• ra : buf_xclk_mclk16_393 , fifo_1cycle , fifo_same_clock , fifo_same_clock_fill , imu_timestamps393 , mult_saxi_wr_chn , sens_hispi_fifo
• ra_chn : mult_saxi_wr
• ra_next : buf_xclk_mclk16_393
• ra_r : huff_fifo393
• racount : simul_axi_hp_rd
• raddr : ahci_dma_rd_fifo , ahci_dma_wr_fifo , cmprs_buf_average , cmprs_out_fifo , cmprs_out_fifo32 , dct1d_chen_reorder_in , dct1d_chen_reorder_out , dct_chen_transpose , fifo_cross_clocks , imu_exttime393 , imu_message393 , imu_spi393 , mcntrl_1kx32w , mcntrl_buf_wr , mult_saxi_wr_inbuf , nmea_decoder393 , ram18_32w_32r , ram18_32w_lt32r , ram18_lt32w_32r , ram18_lt32w_lt32r , ram18_var_w_var_r , ram18p_32w_32r , ram18p_32w_lt32r , ram18p_lt32w_32r , ram18p_lt32w_lt32r , ram18p_var_w_var_r , ram_1kx32_1kx32 , ram_1kx32w_512x64r , ram_512x64w_1kx32r , ram_64w_64r , ram_64w_lt64r , ram_lt64w_64r , ram_lt64w_lt64r , ram_var_w_var_r , ramp_64w_64r , ramp_64w_lt64r , ramp_lt64w_64r , ramp_lt64w_lt64r , ramp_var_w_var_r , resync_data , simul_axi_read
• raddr_ct_pend : ahci_dma
• raddr_ct_rq : ahci_dma
• raddr_data_pend : ahci_dma
• raddr_data_rq : ahci_dma
• raddr_fifo : simul_axi_read
• raddr_gray : fifo_cross_clocks
• raddr_gray_top3 : fifo_cross_clocks
• raddr_gray_top3_wclk : fifo_cross_clocks
• raddr_lastInBlock : cmprs_buf_average
• raddr_plus1 : fifo_cross_clocks
• raddr_plus1_gray_top3 : fifo_cross_clocks
• raddr_prd_pend : ahci_dma
• raddr_prd_rq : ahci_dma
• raddr_r : ahci_dma_rd_fifo , elastic1632
• raddr_top3_wclk : fifo_cross_clocks
• raddr_updateBlock : cmprs_buf_average
• raddr_w : ahci_dma_rd_fifo , elastic1632
• ram : cmd_readback , fifo_1cycle , fifo_cross_clocks , fifo_same_clock , fifo_same_clock_fill , gtx_elastic , resync_data , status_read
• ram18_32w_32r : ram18_var_w_var_r
• ram18_32w_lt32r : ram18_var_w_var_r
• ram18_declare_init.vh : ram18_32w_32r , ram18_32w_lt32r , ram18_lt32w_32r , ram18_lt32w_lt32r , ram18_var_w_var_r , ram18p_32w_32r , ram18p_32w_lt32r , ram18p_lt32w_32r , ram18p_lt32w_lt32r , ram18p_var_w_var_r , ram18t_var_w_var_r , ram18tp_var_w_var_r
• ram18_dummy : ram18_var_w_var_r
• ram18_lt32w_32r : ram18_var_w_var_r
• ram18_lt32w_lt32r : ram18_var_w_var_r
• ram18_pass_init.vh : ram18_32w_32r , ram18_32w_lt32r , ram18_lt32w_32r , ram18_lt32w_lt32r , ram18_var_w_var_r , ram18p_32w_32r , ram18p_32w_lt32r , ram18p_lt32w_32r , ram18p_lt32w_lt32r , ram18p_var_w_var_r , ram18t_var_w_var_r , ram18tp_var_w_var_r
• ram18_var_w_var_r : cmd_frame_sequencer , focus_sharp393 , huff_fifo393 , huffman393 , huffman_snglclk , mult_saxi_wr , mult_saxi_wr_inbuf , quantizer393 , sensor_i2c_prot
• ram18p_32w_32r : ram18p_var_w_var_r
• ram18p_32w_lt32r : ram18p_var_w_var_r
• ram18p_dummy : ram18p_var_w_var_r
• ram18p_lt32w_32r : ram18p_var_w_var_r
• ram18p_lt32w_lt32r : ram18p_var_w_var_r
• ram18p_var_w_var_r : ahci_fsm , ahci_sata_layers , cmprs_buf_average
• ram18tp_var_w_var_r : sens_hist_ram_snglclk_18
• ram36_declare_init.vh : ram_64w_64r , ram_64w_lt64r , ram_lt64w_64r , ram_lt64w_lt64r , ram_var_w_var_r , ramp_64w_64r , ramp_64w_lt64r , ramp_lt64w_64r , ramp_lt64w_lt64r , ramp_var_w_var_r , ramt_var_w_var_r , ramt_var_wb_var_r , ramtp_var_w_var_r
• ram36_pass_init.vh : ram_64w_64r , ram_64w_lt64r , ram_lt64w_64r , ram_lt64w_lt64r , ram_var_w_var_r , ramp_64w_64r , ramp_64w_lt64r , ramp_lt64w_64r , ramp_lt64w_lt64r , ramp_var_w_var_r , ramt_var_w_var_r , ramt_var_wb_var_r , ramtp_var_w_var_r
• ram4 : focus_sharp393
• ram_1kx32_1kx32 : mcontr_sequencer
• ram_1kx32w_512x64r : mcntrl_1kx32w
• ram_512x64w_1kx32r : mcntrl_1kx32r
• ram_64w_64r : ram_var_w_var_r
• ram_64w_lt64r : ram_var_w_var_r
• ram_chn : sens_gamma
• ram_chn_d : sens_gamma
• ram_chn_d2 : sens_gamma
• ram_dummy : ram_var_w_var_r
• ram_lt64w_64r : ram_var_w_var_r
• ram_lt64w_lt64r : ram_var_w_var_r
• ram_nempty : fifo_same_clock , fifo_same_clock_fill
• ram_reg : dct_chen_transpose
• ram_reg2 : dct_chen_transpose
• ram_var_w_var_r : axi_ahci_regs , cmd_frame_sequencer , cmprs_out_fifo , cmprs_out_fifo32 , histogram_saxi , mcntrl_buf_rd , mcntrl_buf_wr , mult_saxi_wr , mult_saxi_wr_inbuf , sensor_i2c
• RAMB18E1 : ram18_32w_32r , ram18_32w_lt32r , ram18_lt32w_32r , ram18_lt32w_lt32r , ram18p_32w_32r , ram18p_32w_lt32r , ram18p_lt32w_32r , ram18p_lt32w_lt32r , ram18t_var_w_var_r , ram18tp_var_w_var_r
• RAMB36E1 : ram_1kx32_1kx32 , ram_1kx32w_512x64r , ram_512x64w_1kx32r , ram_64w_64r , ram_64w_lt64r , ram_lt64w_64r , ram_lt64w_lt64r , ramp_64w_64r , ramp_64w_lt64r , ramp_lt64w_64r , ramp_lt64w_lt64r , ramt_var_w_var_r , ramt_var_wb_var_r , ramtp_var_w_var_r
• ramo_full : fifo_sameclock_control
• ramp : simul_sensor12bits
• ramp_64w_64r : ramp_var_w_var_r
• ramp_64w_lt64r : ramp_var_w_var_r
• ramp_dummy : ramp_var_w_var_r
• ramp_lt64w_64r : ramp_var_w_var_r
• ramp_lt64w_lt64r : ramp_var_w_var_r
• ramp_var_w_var_r : sens_gamma
• ramt_var_w_var_r : gtx_10x8dec , gtx_8x10enc , sens_hist_ram_double , sens_hist_ram_nobuff , sens_hist_ram_snglclk_32
• ramt_var_wb_var_r : axi_ahci_regs
• ramtp_var_w_var_r : sens_hist_ram_single
• rburst : axibram_read , simul_axi_hp_rd
• rclk : cmprs_out_fifo , cmprs_out_fifo32 , elastic1632 , fifo_cross_clocks , gtx_elastic , mcntrl_1kx32w , mcntrl_buf_wr , ram18_32w_32r , ram18_32w_lt32r , ram18_lt32w_32r , ram18_lt32w_lt32r , ram18_var_w_var_r , ram18p_32w_32r , ram18p_32w_lt32r , ram18p_lt32w_32r , ram18p_lt32w_lt32r , ram18p_var_w_var_r , ram_1kx32_1kx32 , ram_1kx32w_512x64r , ram_512x64w_1kx32r , ram_64w_64r , ram_64w_lt64r , ram_lt64w_64r , ram_lt64w_lt64r , ram_var_w_var_r , ramp_64w_64r , ramp_64w_lt64r , ramp_lt64w_64r , ramp_lt64w_lt64r , ramp_var_w_var_r , resync_data , timestamp_fifo
• rcmd : simul_axi_read
• rcntr : dct_chen_transpose
• rcount : fifo_same_clock_fill , simul_axi_hp_rd
• rcv : sensor_i2c_scl_sda , timestamp_fifo
• rcv_done : camsync393
• rcv_done_mclk : camsync393
• rcv_done_rq : camsync393
• rcv_done_rq_d : camsync393
• rcv_error : camsync393
• rcv_junk : link
• rcv_last : imu_timestamps393
• rcv_r : sensor_i2c_scl_sda
• rcv_rest_r : status_router2
• rcv_run : camsync393
• rcv_run_d : camsync393
• rcv_run_or_deaf : camsync393
• rcvd_dword : link
• rcvd_dword0 : link
• rd : cmd_readback , fifo_2regs , fifo_sameclock_control , mcntrl_1kx32w , mcntrl_buf_wr , status_read
• rd32BitEn : simul_axi_hp_rd
• rd_addr : gtx_elastic
• rd_addr_gr : gtx_elastic
• rd_addr_gr_r : gtx_elastic
• rd_addr_gr_rr : gtx_elastic
• rd_addr_r : gtx_elastic
• rd_burst : mult_saxi_wr_chn
• rd_data : debug_slave
• rd_id : membridge
• rd_line : sens_hispi12l4
• rd_line_r : sens_hispi12l4
• rd_next_addr : gtx_elastic
• rd_num_burst : mult_saxi_wr_chn
• rd_qos_in : simul_axi_hp_rd
• rd_qos_out : simul_axi_hp_rd
• rd_run : sens_hispi12l4
• rd_run_d : sens_hispi12l4
• rd_sa : sensor_i2c_prot
• rd_start : imu_exttime393 , membridge
• rd_start_mclk : imu_exttime393
• rd_stb : imu_exttime393 , imu_message393 , imu_spi393 , nmea_decoder393
• rd_stb_r : imu_exttime393
• rd_word : mult_saxi_wr_chn
• rdata : ahci_top , axi_ahci_regs , axibram_read , cmprs_out_fifo , cmprs_out_fifo32 , imu_exttime393 , imu_message393 , imu_spi393 , nmea_decoder393
• RDATA : sata_ahci_top
• rdata : sensor_i2c_prot , simul_axi_hp_rd
• rdata_r : elastic1632 , membridge
• RDELAY : sim_frac_clk_delay
• rdFabricOutCmdEn : simul_axi_hp_rd
• rdFabricQosEn : simul_axi_hp_rd
• rdIssueCap0 : simul_axi_hp_rd
• rdIssueCap1 : simul_axi_hp_rd
• rdissuecap1en : simul_axi_hp_rd
• rdQosHeadOfCmdQEn : simul_axi_hp_rd
• rdStaticQos : simul_axi_hp_rd
• rdwr_en : membridge
• rdwr_en_mclk : membridge
• rdwr_reset_addr : membridge
• rdwr_reset_addr_mclk : membridge
• rdwr_start : membridge
• rdy : huffman393 , idelay_ctrl , imu_exttime393 , imu_message393 , imu_spi393 , logger_arbiter393 , nmea_decoder393 , par12_hispi_psp4l , par12_hispi_psp4l_lane , stuffer393
• rdy_r : imu_message393 , imu_spi393 , nmea_decoder393
• rdy_reg : simul_axi_slow_ready
• rdy_rega : stuffer393
• rdy_regb : stuffer393
• rdy_regc : stuffer393
• rdy_regd : stuffer393
• rdy_w : bit_stuffer_escape
• re : fifo_1cycle , fifo_cross_clocks , fifo_same_clock , fifo_same_clock_fill , gtx_elastic , huff_fifo393 , resync_data , sens_hispi_fifo , sensor_fifo
• re_aligned : oob_ctrl , sata_phy
• re_b : sens_hist_ram_double , sens_hist_ram_nobuff , sens_hist_ram_single
• re_cur_chn : mult_saxi_wr
• re_even : sens_hist_ram_snglclk_18 , sens_hist_ram_snglclk_32
• re_even_d : sens_hist_ram_snglclk_18 , sens_hist_ram_snglclk_32
• re_last_word : mult_saxi_wr_inbuf
• re_odd : sens_hist_ram_snglclk_18 , sens_hist_ram_snglclk_32
• re_odd_d : sens_hist_ram_snglclk_18 , sens_hist_ram_snglclk_32
• re_r : dct1d_chen_reorder_in , dct_chen_transpose
• read_address : axibram_read , simul_axi_hp_rd
• read_address_bytes : sensor_i2c_prot
• read_align : gtx_elastic
• read_burst : mult_saxi_wr_inbuf
• read_burst0 : mult_saxi_wr
• read_burst1 : mult_saxi_wr
• read_burst2 : mult_saxi_wr
• read_burst3 : mult_saxi_wr
• read_busy : cmd_frame_sequencer , membridge
• READ_CT_LATENCY : ahci_fis_transmit , ahci_top
• read_data_bytes : sensor_i2c_prot
• read_format_byte : nmea_decoder393
• read_format_length : nmea_decoder393
• read_in_progress : axibram_read , simul_axi_hp_rd
• read_in_progress_d : axibram_read
• read_in_progress_d_w : axibram_read
• read_in_progress_or : axibram_read
• read_in_progress_w : axibram_read , simul_axi_hp_rd
• read_left : axibram_read , simul_axi_hp_rd
• read_next : huffman393
• read_no_more : membridge
• read_over : membridge
• read_page : membridge
• read_pages_ready : membridge
• READ_REG_LATENCY : ahci_fis_transmit , ahci_top
• read_started : membridge
• READ_WIDTH : debug_slave
• readback_rdata : x393
• readback_selected : x393
• readback_selected_regen : x393
• readback_selected_ren : x393
• readID : X393_cocotb_server
• readIDMask : X393_cocotb_server
• reading_frame : cmprs_frame_sync , cmprs_status , jp_channel
• reading_frame_r : cmprs_frame_sync
• ready : dci_reset , sensor_i2c_scl_sda , simul_axi_fifo , simul_axi_master_rdaddr , simul_axi_master_wdata , simul_axi_master_wraddr , simul_axi_slow_ready , simul_fifo
• ready_to_flush : huffman393 , huffman_snglclk
• ready_to_start : cmprs_afi_mux
• realign : datascope_incoming_raw , gtx_comma_align , gtx_wrap , gtxe2_chnl_rx_dataiface
• recal_tx_done : oob , oob_ctrl , oob_dev , sata_phy , sata_phy_dev
• recal_tx_done_r : sata_phy
• recalc_r : mcntrl_linear_rw , mcntrl_tiled_rw
• receiving_byte : rs232_rcv393
• ref_clk : gtxe2_chnl_cpll , mcntrl393 , mcontr_sequencer , memctrl16 , phy_cmd , phy_top , sensors393 , x393
• REF_JITTER1 : mcntrl393 , mcontr_sequencer , memctrl16 , mmcm_adv , mmcm_phase_cntr , phy_cmd , phy_top , pll_base
• REF_JITTER2 : mmcm_adv , mmcm_phase_cntr
• refclk : idelay_ctrl , rtc393 , timing393
• refclk2x_mclk : rtc393
• REFCLK_FREQUENCY : byte_lane , cmd_addr , cmda_single , dm_single , dq_single , dqs_single , dqs_single_nofine , idelay_fine_pipe , idelay_nofine , mcntrl393 , mcontr_sequencer , memctrl16 , odelay_fine_pipe , odelay_pipe , phy_cmd , phy_top , pxd_clock , pxd_single , sens_10398 , sens_hispi12l4 , sens_hispi_clock , sens_hispi_din
• refclk_mclk : rtc393
• refresh_addr : memctrl16
• refresh_due : ddr_refresh
• refresh_en : memctrl16
• refresh_grant : memctrl16
• refresh_need : memctrl16
• refresh_period : ddr_refresh , memctrl16
• refresh_want : memctrl16
• reg_addr : ahci_fis_receive , ahci_fis_transmit , simul_axi_hp_rd , simul_axi_hp_wr
• reg_addr_r : ahci_fis_receive
• reg_ah : sensor_i2c_prot
• reg_d2h : ahci_fis_receive
• reg_data : ahci_fis_receive
• reg_din : simul_axi_hp_rd , simul_axi_hp_wr
• reg_dout : simul_axi_hp_rd , simul_axi_hp_wr
• reg_ds : ahci_fis_receive
• reg_dvalid : simul_axi_hp_rd , simul_axi_hp_wr
• reg_in : fifo_2regs
• reg_out : fifo_2regs
• reg_ps : ahci_fis_receive
• reg_rd : simul_axi_hp_rd , simul_axi_hp_wr
• reg_rdata : ahci_fis_transmit
• reg_re : ahci_fis_transmit
• reg_re_r : ahci_fis_transmit
• reg_re_w : ahci_fis_transmit
• reg_sdb : ahci_fis_receive
• reg_seq_number : imu_spi393
• reg_we : ahci_fis_receive
• reg_we_w : ahci_fis_receive
• reg_wr : simul_axi_hp_rd , simul_axi_hp_wr
• regbit_type : axi_ahci_regs
• regen : cmd_readback , cmprs_out_fifo , cmprs_out_fifo32 , mcntrl_1kx32w , mcntrl_buf_wr , ram18_32w_32r , ram18_32w_lt32r , ram18_lt32w_32r , ram18_lt32w_lt32r , ram18_var_w_var_r , ram18p_32w_32r , ram18p_32w_lt32r , ram18p_lt32w_32r , ram18p_lt32w_lt32r , ram18p_var_w_var_r , ram_1kx32_1kx32 , ram_1kx32w_512x64r , ram_512x64w_1kx32r , ram_64w_64r , ram_64w_lt64r , ram_lt64w_64r , ram_lt64w_lt64r , ram_var_w_var_r , ramp_64w_64r , ramp_64w_lt64r , ramp_lt64w_64r , ramp_lt64w_lt64r , ramp_var_w_var_r , status_read
• regen_a : ram18t_var_w_var_r , ram18tp_var_w_var_r , ramt_var_w_var_r , ramt_var_wb_var_r , ramtp_var_w_var_r , sens_hist_ram_double , sens_hist_ram_nobuff , sens_hist_ram_single
• regen_a_even : sens_hist_ram_snglclk_18 , sens_hist_ram_snglclk_32
• regen_a_odd : sens_hist_ram_snglclk_18 , sens_hist_ram_snglclk_32
• regen_b : ram18t_var_w_var_r , ram18tp_var_w_var_r , ramt_var_w_var_r , ramt_var_wb_var_r , ramtp_var_w_var_r , sens_hist_ram_double , sens_hist_ram_nobuff , sens_hist_ram_single
• regen_even : sens_histogram_snglclk
• regen_odd : sens_histogram_snglclk
• regen_r : dct_chen_transpose
• REGISTER : level_cross_clocks , level_cross_clocks_single_bit , sync_resets
• REGISTER_STATUS : status_generate , status_generate_extra , status_generate_only
• registered : condition_mux
• REGISTERS : ram18_32w_lt32r , ram18_lt32w_32r , ram18_lt32w_lt32r , ram18_var_w_var_r , ram18p_32w_lt32r , ram18p_lt32w_32r , ram18p_lt32w_lt32r , ram18p_var_w_var_r , ram_1kx32_1kx32 , ram_1kx32w_512x64r , ram_512x64w_1kx32r , ram_64w_lt64r , ram_lt64w_64r , ram_lt64w_lt64r , ram_var_w_var_r , ramp_64w_lt64r , ramp_lt64w_64r , ramp_lt64w_lt64r , ramp_var_w_var_r
• registers2log_ram : imu_spi393
• REGISTERS_A : ram18t_var_w_var_r , ram18tp_var_w_var_r , ramt_var_w_var_r , ramt_var_wb_var_r , ramtp_var_w_var_r
• REGISTERS_B : ram18t_var_w_var_r , ram18tp_var_w_var_r , ramt_var_w_var_r , ramt_var_wb_var_r , ramtp_var_w_var_r
• regs : level_cross_clocks_single_bit
• regs_addr : ahci_ctrl_stat , ahci_top
• regs_changed : ahci_ctrl_stat
• regs_din : ahci_ctrl_stat , ahci_top
• regs_din_from_acs : ahci_top
• regs_din_from_freceive : ahci_top
• regs_dout : ahci_top
• regs_next : level_cross_clocks_single_bit
• regs_raddr : ahci_top
• regs_re : ahci_top
• regs_re_ftransmit : ahci_top
• regs_saddr : ahci_top
• regs_waddr : ahci_top
• regs_we : ahci_ctrl_stat , ahci_top
• regs_we_acs : ahci_top
• regs_we_freceive : ahci_top
• reject : memctrl16
• reject0 : mcntrl393 , memctrl16
• reject1 : mcntrl393 , memctrl16
• reject10 : memctrl16
• reject11 : memctrl16
• reject12 : memctrl16
• reject13 : memctrl16
• reject14 : memctrl16
• reject15 : memctrl16
• reject2 : mcntrl393 , memctrl16
• reject3 : mcntrl393 , memctrl16
• reject4 : mcntrl393 , memctrl16
• reject8 : memctrl16
• reject9 : memctrl16
• reject_r : memctrl16
• rel_addr64 : membridge
• reliable_clk : ahci_sata_layers , sata_ahci_top , sata_phy
• rem : fifo_same_clock , fifo_same_clock_fill
• remainder_in_xfer : mcntrl_linear_rw
• remainder_tile_width : mcntrl_tiled_rw
• ren : cmd_frame_sequencer , cmprs_out_fifo , cmprs_out_fifo32 , quantizer393 , ram18_32w_32r , ram18_32w_lt32r , ram18_lt32w_32r , ram18_lt32w_lt32r , ram18_var_w_var_r , ram18p_32w_32r , ram18p_32w_lt32r , ram18p_lt32w_32r , ram18p_lt32w_lt32r , ram18p_var_w_var_r , ram_1kx32_1kx32 , ram_1kx32w_512x64r , ram_512x64w_1kx32r , ram_64w_64r , ram_64w_lt64r , ram_lt64w_64r , ram_lt64w_lt64r , ram_var_w_var_r , ramp_64w_64r , ramp_64w_lt64r , ramp_lt64w_64r , ramp_lt64w_lt64r , ramp_var_w_var_r
• ren0 : mcontr_sequencer
• ren1 : mcontr_sequencer
• ren_suspend_flush : cmprs_afi_mux
• reord_buf_ram : dct1d_chen_reorder_out
• rep_en : camsync393
• REPEAT_ADDR : cmd_encod_linear_rd , cmd_encod_linear_wr
• repeat_frames : mcntrl_linear_rw , mcntrl_tiled_rw
• repeat_period : camsync393
• repet_mode : sens_gamma
• REPLICATE_IN_STAGE1 : dct2d8x8_chen
• REPLICATE_IN_STAGE2 : dct2d8x8_chen
• req_clr : sensor_i2c
• RESERVED : X393_cocotb_server
• reset : dci_reset , gtxe2_chnl , gtxe2_chnl_cpll , gtxe2_chnl_rx , gtxe2_chnl_rx_dataiface , gtxe2_chnl_rx_des , gtxe2_chnl_rx_oob , gtxe2_chnl_tx , gtxe2_chnl_tx_dataiface , gtxe2_chnl_tx_oob , gtxe2_chnl_tx_ser , GTXE2_GPL , simul_axi_fifo , simul_axi_master_rdaddr , simul_axi_master_wdata , simul_axi_master_wraddr , simul_axi_read , simul_axi_slow_ready , simul_fifo
• reset_bit_duration : rs232_rcv393
• reset_clk : clocks393 , clocks393m
• reset_cmd : cmd_frame_sequencer , sensor_i2c
• reset_counters : axi_hp_abort
• reset_extended : mmcm_phase_cntr
• reset_on : cmd_frame_sequencer , sensor_i2c
• reset_or_GTRXRESET : GTXE2_GPL
• reset_out : x393_dut
• reset_page_rd : cmprs_macroblock_buf_iface , membridge
• reset_page_wr : membridge
• reset_pointers : cmprs_afi_mux , cmprs_afi_mux_ptr , cmprs_afi_mux_ptr_wresp
• reset_rq : cmprs_afi_mux_ptr , cmprs_afi_mux_ptr_wresp , mult_saxi_wr_pointers
• reset_rq_enc : cmprs_afi_mux_ptr , cmprs_afi_mux_ptr_wresp , mult_saxi_wr_pointers
• reset_rq_pri : cmprs_afi_mux_ptr , cmprs_afi_mux_ptr_wresp , mult_saxi_wr_pointers
• reset_seq_done : cmd_frame_sequencer
• reset_timer : GTXE2_GPL
• RESET_TO_FIRST_ACCESS : ahci_top , axi_ahci_regs , sata_ahci_top
• reset_wait_pause : rs232_rcv393
• RESETOVRD : gtxe2_channel_wrapper , GTXE2_GPL
• resetting : cmprs_afi_mux_ptr , cmprs_afi_mux_ptr_wresp , mult_saxi_wr_pointers
• restart : camsync393 , dct1d_chen_reorder_in , freq_meter , nmea_decoder393 , rs232_rcv393
• restart_cntr : camsync393
• restart_cntr_run : camsync393
• resync : gtxe2_chnl_rx_dataiface
• resync_data : gtx_wrap
• resync_fifo_nonsynt : gtxe2_chnl_rx_dataiface , gtxe2_chnl_rx_des , gtxe2_chnl_tx_dataiface , gtxe2_chnl_tx_ser
• RESYNC_FIFO_NOSYNT_V : gtxe2_chnl_clocking
• retry_interval_elapsed : oob_dev
• retry_timer : oob_dev
• rfifo_fill : fifo_same_clock_fill
• RFIS32 : ahci_fis_receive
• RFIS32_LENM1 : ahci_fis_receive
• rid : ahci_top , axi_ahci_regs , axibram_read
• RID : sata_ahci_top
• rid : simul_axi_hp_rd
• rlast : ahci_top , axi_ahci_regs , axibram_read
• RLAST : sata_ahci_top
• rlast : simul_axi_hp_rd
• rlen : axibram_read , simul_axi_hp_rd , simul_axi_read
• rlen_fifo : simul_axi_read
• rll : huffman393 , huffman_snglclk
• rll1 : huffman393
• rll2 : huffman393
• rll_cntr : encoderDCAC393
• rll_late : huffman_snglclk
• rll_out : encoderDCAC393
• rmv1_req_wclk : gtx_elastic
• rmv2_req_wclk : gtx_elastic
• rmv_ack_rclk : gtx_elastic
• rnum_in_fifo : fifo_same_clock_fill
• rnw : sensor_i2c_prot
• rollover : membridge
• rollover_limited_w : cmprs_afi_mux
• rollover_r : cmprs_afi_mux_ptr
• rollover_w : cmprs_afi_mux_ptr
• rom_a : zigzag393
• rom_cmd : cmd_encod_linear_rd , cmd_encod_linear_wr , cmd_encod_tiled_32_rd , cmd_encod_tiled_32_wr , cmd_encod_tiled_rd , cmd_encod_tiled_wr
• ROM_DEPTH : cmd_encod_linear_rd , cmd_encod_linear_wr , cmd_encod_tiled_32_rd , cmd_encod_tiled_32_wr , cmd_encod_tiled_rd , cmd_encod_tiled_wr
• rom_q : zigzag393
• rom_r : cmd_encod_linear_rd , cmd_encod_linear_wr , cmd_encod_tiled_32_rd , cmd_encod_tiled_32_wr , cmd_encod_tiled_rd , cmd_encod_tiled_wr
• rom_skip : cmd_encod_linear_rd , cmd_encod_linear_wr , cmd_encod_tiled_32_rd , cmd_encod_tiled_32_wr , cmd_encod_tiled_rd , cmd_encod_tiled_wr
• ROM_WIDTH : cmd_encod_linear_rd , cmd_encod_linear_wr , cmd_encod_tiled_32_rd , cmd_encod_tiled_32_wr , cmd_encod_tiled_rd , cmd_encod_tiled_wr
• room_for1 : ahci_dma_rd_stuff
• room_for2 : ahci_dma_rd_stuff
• ROUND_OUT : dct1d_chen
• round_robin : mult_saxi_wr
• ROUND_STAGE1 : dct2d8x8_chen
• ROUND_STAGE2 : dct2d8x8_chen
• row : cmd_encod_linear_mux , cmd_encod_linear_rd , cmd_encod_linear_wr , cmd_encod_tiled_32_rd , cmd_encod_tiled_32_wr , cmd_encod_tiled_mux , cmd_encod_tiled_rd , cmd_encod_tiled_wr , simul_sensor12bits
• row1 : cmd_encod_linear_mux
• row10 : cmd_encod_linear_mux
• row11 : cmd_encod_linear_mux
• row12 : cmd_encod_tiled_mux
• row13 : cmd_encod_tiled_mux
• row14 : cmd_encod_tiled_mux
• row15 : cmd_encod_tiled_mux
• row2 : cmd_encod_tiled_mux
• row3 : cmd_encod_linear_mux
• row4 : cmd_encod_tiled_mux
• row8 : cmd_encod_linear_mux
• row9 : cmd_encod_linear_mux
• row_col_bank : cmd_encod_tiled_32_rd , cmd_encod_tiled_32_wr , cmd_encod_tiled_rd , cmd_encod_tiled_wr
• row_col_bank_next_w : cmd_encod_tiled_32_rd , cmd_encod_tiled_32_wr , cmd_encod_tiled_rd , cmd_encod_tiled_wr
• row_col_r : mcntrl_linear_rw , mcntrl_tiled_rw
• row_in : cmd_encod_linear_rd , cmd_encod_linear_rw , cmd_encod_linear_wr
• row_index : simul_sensor12bits
• row_left : mcntrl_linear_rw , mcntrl_tiled_rw
• row_r : cmd_encod_linear_mux , cmd_encod_tiled_mux
• row_sa : cmprs_pixel_buf_iface
• row_w : cmd_encod_linear_mux , cmd_encod_tiled_mux
• rowcol_inc : cmd_encod_tiled_32_rd , cmd_encod_tiled_32_wr , cmd_encod_tiled_mux , cmd_encod_tiled_rd , cmd_encod_tiled_wr , mcntrl_tiled_rw
• rowcol_inc12 : cmd_encod_tiled_mux
• rowcol_inc13 : cmd_encod_tiled_mux
• rowcol_inc14 : cmd_encod_tiled_mux
• rowcol_inc15 : cmd_encod_tiled_mux
• rowcol_inc2 : cmd_encod_tiled_mux
• rowcol_inc4 : cmd_encod_tiled_mux
• rowcol_inc_in : cmd_encod_tiled_32_rd , cmd_encod_tiled_32_rw , cmd_encod_tiled_32_wr , cmd_encod_tiled_rd , cmd_encod_tiled_rw , cmd_encod_tiled_wr
• rowcol_inc_r : cmd_encod_tiled_mux
• rowcol_inc_w : cmd_encod_tiled_mux
• rowd : simul_sensor12bits
• rows_left : cmprs_pixel_buf_iface
• rpage : cmprs_buf_average , quantizer393
• rpage_in : mcntrl_1kx32w , mcntrl_buf_wr
• rpage_next : sensor_membuf , sensors393
• rpage_nxt : mcont_from_chnbuf_reg
• rpage_nxt_chn1 : mcntrl393 , x393
• rpage_nxt_chn2 : mcntrl393
• rpage_nxt_chn3 : mcntrl393
• rpage_nxt_chn4 : mcntrl393
• rpage_set : mcntrl_1kx32w , mcntrl_buf_wr , sensor_membuf , sensors393
• rpntr : timestamp_fifo
• rpointer : cmd_frame_sequencer , sensor_i2c
• rq : cmprs_afi_mux_status , round_robin , sens_histogram_mux , status_generate , status_generate_extra , status_generate_only , status_read
• rq0 : sens_histogram_mux
• rq1 : sens_histogram_mux
• rq2 : sens_histogram_mux
• rq3 : sens_histogram_mux
• rq_any : cmd_seq_mux
• rq_enc : imu_timestamps393
• rq_in : histogram_saxi , sens_histogram_mux , status_router2
• rq_in0 : status_router16 , status_router2 , status_router4 , status_router8
• rq_in1 : status_router16 , status_router2 , status_router4 , status_router8
• rq_in10 : status_router16
• rq_in11 : status_router16
• rq_in12 : status_router16
• rq_in13 : status_router16
• rq_in14 : status_router16
• rq_in15 : status_router16
• rq_in2 : status_router16 , status_router4 , status_router8
• rq_in3 : status_router16 , status_router4 , status_router8
• rq_in4 : status_router16 , status_router8
• rq_in5 : status_router16 , status_router8
• rq_in6 : status_router16 , status_router8
• rq_in7 : status_router16 , status_router8
• rq_in8 : status_router16
• rq_in9 : status_router16
• rq_int : status_router16 , status_router4 , status_router8
• rq_not_zero : logger_arbiter393
• rq_out : mult_saxi_wr_chn , sens_histogram_mux , status_router16 , status_router2 , status_router4 , status_router8
• rq_out_chn : mult_saxi_wr
• rq_pri : imu_timestamps393
• rq_r : status_generate_extra , status_generate_only , status_read
• rq_wr : mult_saxi_wr , mult_saxi_wr_chn
• rq_wr_busy : mult_saxi_wr_chn
• rq_wr_r : mult_saxi_wr_chn
• rready : ahci_top , axi_ahci_regs , axibram_read
• RREADY : sata_ahci_top
• rready : simul_axi_hp_rd
• rreg_full : fifo_sameclock_control
• rresp : ahci_top , axi_ahci_regs , axibram_read
• RRESP : sata_ahci_top
• rresp : simul_axi_hp_rd
• rrst : cmprs_out_fifo , cmprs_out_fifo32 , fifo_cross_clocks , resync_data , timestamp_fifo
• rs232_rcv393 : event_logger
• rs232_start : event_logger
• rs232_wait_pause : event_logger , nmea_decoder393
• RSEL : cmd_encod_linear_rd , cmd_encod_linear_rw , cmd_encod_tiled_32_rd , cmd_encod_tiled_32_rw , cmd_encod_tiled_rd , cmd_encod_tiled_rw , mcntrl393
• rst : ahci_dma_rd_stuff , ahci_sata_layers , axi_hp_clk , bit_stuffer_27_32 , bit_stuffer_escape , buf_xclk_mclk16_393 , byte_lane , clock_inverter , cmd_addr , cmd_deser , cmd_deser_dual , cmd_deser_multi , cmd_deser_single , cmda_single , crc
• RST : csconvert18a
• rst : datascope_timing , dct1d_chen , dct1d_chen_reorder_in , dct1d_chen_reorder_out , dct2d8x8_chen , dct_chen_transpose , dly01_16 , dly_16 , dm_single , dq_single , dqs_single , dqs_single_nofine , dsp_addsub_simd , dsp_ma , dsp_ma_preadd , dual_clock_source , elastic_cross_clock , fifo_1cycle , fifo_cross_clocks , fifo_same_clock , fifo_same_clock_fill , fifo_sameclock_control , freq_meter , gtx_10x8dec , gtx_8x10enc , gtx_comma_align , gtx_elastic , gtxe2_chnl_rx_10x8dec , gtxe2_chnl_rx_align , huffman_snglclk , idelay_ctrl , idelay_fine_pipe , idelay_nofine , imu_timestamps393 , iserdes_mem , latch_g_ce , link , logger_arbiter393 , mcont_common_chnbuf_reg , mcont_from_chnbuf_reg , mcont_to_chnbuf_reg , mmcm_adv , mmcm_phase_cntr , mult_saxi_wr_pointers , multipulse_cross_clock , oddr , oddr_ds , oddr_ss , odelay_fine_pipe , odelay_pipe , oob , oob_ctrl , oob_dev , oserdes_mem , par12_hispi_psp4l , par12_hispi_psp4l_lane , phy_top , pll_base , pulse_cross_clock , pxd_clock , sata_phy , sata_phy_dev , scrambler , sensor_i2c_scl_sda , sim_soc_interrupts , simul_axi_hp_rd , simul_axi_hp_wr , simul_clk , simul_clk_single , simul_saxi_gp_wr , status_generate , status_generate_extra , status_generate_only , status_router16 , status_router2 , status_router4 , status_router8 , sync_resets
• RST : x393_dut
• rst_aclk : mult_saxi_wr_pointers
• rst_clk_div : phy_cmd
• rst_early_master : sync_resets
• rst_early_master_w : sync_resets
• rst_fifo : cmprs_out_fifo , cmprs_out_fifo32
• rst_frame_num_r : mcntrl_linear_rw , mcntrl_tiled_rw
• rst_frame_num_w : mcntrl_linear_rw , mcntrl_tiled_rw
• rst_hba : ahci_ctrl_stat
• rst_in : mcntrl393 , mcontr_sequencer , memctrl16 , phy_cmd , phy_top
• rst_mclk : buf_xclk_mclk16_393 , cmprs_afi_mux
• rst_mmcm : sens_10398 , sens_hispi12l4 , sens_hispi_clock , sens_parallel12
• rst_nclk : mcont_to_chnbuf_reg , stuffer393
• rst_pntr : sensor_membuf
• rst_pntr_aclk : mult_saxi_wr_pointers
• rst_pntr_mclk : mult_saxi_wr_pointers
• rst_por : ahci_ctrl_stat
• rst_port : ahci_ctrl_stat
• rst_r : sata_phy_dev
• rst_rd : resync_fifo_nonsynt
• rst_timer : sata_phy , sata_phy_dev
• RST_TIMER_LIMIT : sata_phy , sata_phy_dev
• rst_w : sync_resets
• rst_wpntr : sensor_membuf
• rst_wr : resync_fifo_nonsynt
• rstb : timestamp_fifo
• rstop_r : dct_chen_transpose
• rtc393 : timing393
• RTC_ADDR : rtc393 , timing393
• RTC_BITC_PREDIV : rtc393 , timing393
• RTC_MASK : rtc393 , timing393
• RTC_MHZ : rtc393 , timing393
• RTC_SEC_USEC_ADDR : rtc393 , timing393
• RTC_SET_CORR : rtc393 , timing393
• RTC_SET_SEC : rtc393 , timing393
• RTC_SET_STATUS : rtc393 , timing393
• RTC_SET_USEC : rtc393 , timing393
• RTC_STATUS_REG_ADDR : rtc393 , timing393
• run : sens_hispi_fifo
• run_addr : mcontr_sequencer
• run_any_d : sensor_i2c_prot
• run_busy : mcontr_sequencer
• run_chn : mcontr_sequencer
• run_chn_d : mcontr_sequencer
• run_chn_mclk : mult_saxi_wr
• run_chn_w_d : mcontr_sequencer
• run_chn_w_d_negedge : mcontr_sequencer
• run_cmd : cmd_frame_sequencer , sensor_i2c
• run_done : mcontr_sequencer
• run_extra_wr : sensor_i2c_prot
• run_extra_wr_d : sensor_i2c_prot
• run_r : datascope_incoming , sens_hispi_fifo
• run_refresh : mcontr_sequencer
• run_refresh_d : mcontr_sequencer
• run_refresh_w_d : mcontr_sequencer
• run_refresh_w_d_negedge : mcontr_sequencer
• run_reg_rd : sensor_i2c_prot
• run_reg_wr : sensor_i2c_prot
• run_seq : mcontr_sequencer
• run_seq_d : mcontr_sequencer
• run_w_d : mcontr_sequencer
• run_w_d_negedge : mcontr_sequencer
• run_xclk : freq_meter
• running : bit_stuffer_metadata , huffman_stuffer_meta , stuffer393
• rvalid : ahci_top , axi_ahci_regs , axibram_read
• RVALID : sata_ahci_top
• rvalid : sensor_i2c_prot , simul_axi_hp_rd
• rw_in_progress : membridge
• rwaddr_rq_r : ahci_dma
• rwen_even : sens_histogram_snglclk
• rwen_odd : sens_histogram_snglclk
• RX8B10BEN : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_rx , gtxe2_chnl_rx_10x8dec , GTXE2_GPL
• RX_BIAS_CFG : gtxe2_channel_wrapper , GTXE2_GPL
• RX_BUFFER_CFG : gtxe2_channel_wrapper , GTXE2_GPL
• RX_CLK25_DIV : gtxe2_channel_wrapper , GTXE2_GPL
• RX_CLKMUX_PD : gtxe2_channel_wrapper , GTXE2_GPL
• rx_clocks_aligned : gtx_wrap
• RX_CM_SEL : gtxe2_channel_wrapper , GTXE2_GPL
• RX_CM_TRIM : gtxe2_channel_wrapper , GTXE2_GPL
• RX_DATA_WIDTH : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_clocking , gtxe2_chnl_rx , GTXE2_GPL
• RX_DDI_SEL : gtxe2_channel_wrapper , GTXE2_GPL
• RX_DEBUG_CFG : gtxe2_channel_wrapper , GTXE2_GPL
• RX_DEFER_RESET_BUF_EN : gtxe2_channel_wrapper , GTXE2_GPL
• RX_DFE_GAIN_CFG : gtxe2_channel_wrapper , GTXE2_GPL
• RX_DFE_H2_CFG : gtxe2_channel_wrapper , GTXE2_GPL
• RX_DFE_H3_CFG : gtxe2_channel_wrapper , GTXE2_GPL
• RX_DFE_H4_CFG : gtxe2_channel_wrapper , GTXE2_GPL
• RX_DFE_H5_CFG : gtxe2_channel_wrapper , GTXE2_GPL
• RX_DFE_KL_CFG : gtxe2_channel_wrapper , GTXE2_GPL
• RX_DFE_KL_CFG2 : gtxe2_channel_wrapper , GTXE2_GPL
• RX_DFE_LPM_CFG : gtxe2_channel_wrapper , GTXE2_GPL
• RX_DFE_LPM_HOLD_DURING_EIDLE : gtxe2_channel_wrapper , GTXE2_GPL
• RX_DFE_UT_CFG : gtxe2_channel_wrapper , GTXE2_GPL
• RX_DFE_VP_CFG : gtxe2_channel_wrapper , GTXE2_GPL
• RX_DFE_XYD_CFG : gtxe2_channel_wrapper , GTXE2_GPL
• RX_DISPERR_SEQ_MATCH : gtxe2_channel_wrapper , GTXE2_GPL
• RX_INT_DATAWIDTH : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_clocking , gtxe2_chnl_rx , GTXE2_GPL
• RX_OS_CFG : gtxe2_channel_wrapper , GTXE2_GPL
• rx_phy_clk : gtxe2_chnl_clocking
• rx_pma_div1_clk : gtxe2_chnl_clocking
• rx_pma_divider1 : gtxe2_chnl_clocking
• rx_pma_divider2 : gtxe2_chnl_clocking
• RX_PRBS_ERR_CNT : GTXE2_GPL
• rx_rst_done : GTXE2_GPL
• rx_serial_clk : gtxe2_chnl , gtxe2_chnl_clocking
• rx_serial_divider : gtxe2_chnl_clocking
• RX_SIG_VALID_DLY : gtxe2_channel_wrapper , GTXE2_GPL
• rx_sipo_clk : gtxe2_chnl_clocking
• RX_XCLK_SEL : gtxe2_channel_wrapper , GTXE2_GPL
• RXBUF_ADDR_MODE : gtxe2_channel_wrapper , GTXE2_GPL
• RXBUF_EIDLE_HI_CNT : gtxe2_channel_wrapper , GTXE2_GPL
• RXBUF_EIDLE_LO_CNT : gtxe2_channel_wrapper , GTXE2_GPL
• RXBUF_EN : gtxe2_channel_wrapper , GTXE2_GPL
• RXBUF_RESET_ON_CB_CHANGE : gtxe2_channel_wrapper , GTXE2_GPL
• RXBUF_RESET_ON_COMMAALIGN : gtxe2_channel_wrapper , GTXE2_GPL
• RXBUF_RESET_ON_EIDLE : gtxe2_channel_wrapper , GTXE2_GPL
• RXBUF_RESET_ON_RATE_CHANGE : gtxe2_channel_wrapper , GTXE2_GPL
• RXBUF_THRESH_OVFLW : gtxe2_channel_wrapper , GTXE2_GPL
• RXBUF_THRESH_OVRD : gtxe2_channel_wrapper , GTXE2_GPL
• RXBUF_THRESH_UNDFLW : gtxe2_channel_wrapper , GTXE2_GPL
• RXBUFRESET : gtxe2_channel_wrapper , GTXE2_GPL
• RXBUFRESET_TIME : gtxe2_channel_wrapper , GTXE2_GPL
• RXBUFSTATUS : gtxe2_channel_wrapper , GTXE2_GPL
• RXBYTEISALIGNED : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_rx , gtxe2_chnl_rx_align , GTXE2_GPL
• rxbyteisaligned : oob_ctrl , sata_phy , sata_phy_dev
• RXBYTEREALIGN : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_rx , gtxe2_chnl_rx_align , GTXE2_GPL
• RXCDR_CFG : gtxe2_channel_wrapper , GTXE2_GPL
• RXCDR_FR_RESET_ON_EIDLE : gtxe2_channel_wrapper , GTXE2_GPL
• RXCDR_HOLD_DURING_EIDLE : gtxe2_channel_wrapper , GTXE2_GPL
• RXCDR_LOCK_CFG : gtxe2_channel_wrapper , GTXE2_GPL
• RXCDR_PH_RESET_ON_EIDLE : gtxe2_channel_wrapper , GTXE2_GPL
• RXCDRFREQRESET : gtxe2_channel_wrapper , GTXE2_GPL
• RXCDRFREQRESET_TIME : gtx_wrap , gtxe2_channel_wrapper , GTXE2_GPL , sata_phy , sata_phy_dev
• RXCDRHOLD : gtxe2_channel_wrapper , GTXE2_GPL
• rxcdrlock : gtx_wrap
• RXCDRLOCK : gtxe2_channel_wrapper , GTXE2_GPL
• rxcdrlock : GTXE2_GPL
• RXCDRLOCK_DELAY : GTXE2_GPL
• RXCDROVRDEN : gtxe2_channel_wrapper , GTXE2_GPL
• RXCDRPHRESET_TIME : gtx_wrap , gtxe2_channel_wrapper , GTXE2_GPL , sata_phy , sata_phy_dev
• RXCDRRESET : gtxe2_channel_wrapper , GTXE2_GPL
• RXCDRRESETRSV : gtxe2_channel_wrapper , GTXE2_GPL
• RXCHANBONDSEQ : gtxe2_channel_wrapper , GTXE2_GPL
• RXCHANISALIGNED : gtxe2_channel_wrapper , GTXE2_GPL
• RXCHANREALIGN : gtxe2_channel_wrapper , GTXE2_GPL
• RXCHARISCOMMA : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_rx
• rxchariscomma : gtxe2_chnl_rx_10x8dec
• RXCHARISCOMMA : GTXE2_GPL
• rxchariscomma : sata_phy_dev
• rxchariscomma_gtx : sata_phy_dev
• RXCHARISK : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_rx
• rxcharisk : gtxe2_chnl_rx_10x8dec
• RXCHARISK : GTXE2_GPL
• rxcharisk : oob , oob_dev , sata_phy , sata_phy_dev
• rxcharisk_dec : gtxe2_chnl_rx_10x8dec
• rxcharisk_dec_out : gtx_wrap
• rxcharisk_gtx : gtx_wrap , sata_phy_dev
• rxcharisk_in : oob , oob_ctrl , oob_dev
• rxcharisk_out : oob , oob_ctrl , sata_phy
• RXCHBONDEN : gtxe2_channel_wrapper , GTXE2_GPL
• RXCHBONDI : gtxe2_channel_wrapper , GTXE2_GPL
• RXCHBONDLEVEL : gtxe2_channel_wrapper , GTXE2_GPL
• RXCHBONDMASTER : gtxe2_channel_wrapper , GTXE2_GPL
• RXCHBONDO : gtxe2_channel_wrapper , GTXE2_GPL
• RXCHBONDSLAVE : gtxe2_channel_wrapper , GTXE2_GPL
• RXCLKCORCNT : gtxe2_channel_wrapper , GTXE2_GPL
• rxcom_timer : oob
• rxcominit_done : oob
• RXCOMINITDET : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_rx , gtxe2_chnl_rx_oob , GTXE2_GPL
• rxcominitdet : oob , oob_dev , sata_phy , sata_phy_dev
• rxcominitdet_clk : gtxe2_chnl_rx_oob
• rxcominitdet_gtx : gtx_wrap
• rxcominitdet_in : oob , oob_ctrl , oob_dev
• rxcominitdet_l : oob
• rxcominitdet_usrclk2 : gtxe2_chnl_rx_oob
• RXCOMMADET : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_rx , gtxe2_chnl_rx_align , GTXE2_GPL
• RXCOMMADETEN : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_rx , gtxe2_chnl_rx_align , GTXE2_GPL
• RXCOMSASDET : gtxe2_channel_wrapper , GTXE2_GPL
• rxcomwake_done : oob
• RXCOMWAKEDET : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_rx , gtxe2_chnl_rx_oob , GTXE2_GPL
• rxcomwakedet : oob , oob_dev , sata_phy , sata_phy_dev
• rxcomwakedet_clk : gtxe2_chnl_rx_oob
• rxcomwakedet_gtx : gtx_wrap
• rxcomwakedet_in : oob , oob_ctrl , oob_dev
• rxcomwakedet_l : oob
• rxcomwakedet_usrclk2 : gtxe2_chnl_rx_oob
• rxdata : datascope_incoming , datascope_incoming_raw
• RXDATA : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_rx , GTXE2_GPL
• rxdata : oob , oob_dev , sata_phy , sata_phy_dev
• rxdata_comma_in : gtx_wrap
• rxdata_comma_in_r : gtx_wrap
• rxdata_comma_out : gtx_wrap
• rxdata_dec_out : gtx_wrap
• rxdata_gtx : gtx_wrap , sata_phy_dev
• rxdata_in : oob , oob_ctrl , oob_dev
• rxdata_out : oob , oob_ctrl , sata_phy
• rxdata_r : datascope_incoming
• RXDATAVALID : gtxe2_channel_wrapper , GTXE2_GPL
• RXDDIEN : gtx_wrap , gtxe2_channel_wrapper , GTXE2_GPL
• RXDFEAGCHOLD : gtxe2_channel_wrapper , GTXE2_GPL
• RXDFEAGCOVRDEN : gtxe2_channel_wrapper , GTXE2_GPL
• RXDFECM1EN : gtxe2_channel_wrapper , GTXE2_GPL
• RXDFELFHOLD : gtxe2_channel_wrapper , GTXE2_GPL
• RXDFELFOVRDEN : gtxe2_channel_wrapper , GTXE2_GPL
• RXDFELPMRESET : gtxe2_channel_wrapper , GTXE2_GPL
• RXDFELPMRESET_TIME : gtx_wrap , gtxe2_channel_wrapper , GTXE2_GPL , sata_phy , sata_phy_dev
• RXDFETAP2HOLD : gtxe2_channel_wrapper , GTXE2_GPL
• RXDFETAP2OVRDEN : gtxe2_channel_wrapper , GTXE2_GPL
• RXDFETAP3HOLD : gtxe2_channel_wrapper , GTXE2_GPL
• RXDFETAP3OVRDEN : gtxe2_channel_wrapper , GTXE2_GPL
• RXDFETAP4HOLD : gtxe2_channel_wrapper , GTXE2_GPL
• RXDFETAP4OVRDEN : gtxe2_channel_wrapper , GTXE2_GPL
• RXDFETAP5HOLD : gtxe2_channel_wrapper , GTXE2_GPL
• RXDFETAP5OVRDEN : gtxe2_channel_wrapper , GTXE2_GPL
• RXDFEUTHOLD : gtxe2_channel_wrapper , GTXE2_GPL
• RXDFEUTOVRDEN : gtxe2_channel_wrapper , GTXE2_GPL
• RXDFEVPHOLD : gtxe2_channel_wrapper , GTXE2_GPL
• RXDFEVPOVRDEN : gtxe2_channel_wrapper , GTXE2_GPL
• RXDFEVSEN : GTXE2_GPL
• RXDFEXYDEN : gtxe2_channel_wrapper , GTXE2_GPL
• RXDFEXYDHOLD : gtxe2_channel_wrapper , GTXE2_GPL
• RXDFEXYDOVRDEN : gtxe2_channel_wrapper , GTXE2_GPL
• RXDISPERR : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_rx
• rxdisperr : gtxe2_chnl_rx_10x8dec
• RXDISPERR : GTXE2_GPL
• rxdisperr : sata_phy , sata_phy_dev
• rxdisperr_dec : gtxe2_chnl_rx_10x8dec
• rxdisperr_dec_out : gtx_wrap
• rxdisperr_gtx : gtx_wrap , sata_phy_dev
• RXDLY_CFG : gtxe2_channel_wrapper , GTXE2_GPL
• RXDLY_LCFG : gtxe2_channel_wrapper , GTXE2_GPL
• RXDLY_TAP_CFG : gtxe2_channel_wrapper , GTXE2_GPL
• RXDLYBYPASS : gtx_wrap , gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_clocking , GTXE2_GPL
• RXDLYEN : gtx_wrap , gtxe2_channel_wrapper , GTXE2_GPL
• RXDLYOVRDEN : gtx_wrap , gtxe2_channel_wrapper , GTXE2_GPL
• rxdlysreset : gtx_wrap
• RXDLYSRESET : gtx_wrap , gtxe2_channel_wrapper , GTXE2_GPL
• RXDLYSRESET_CYCLES : oob
• RXDLYSRESET_MIN_DURATION : GTXE2_GPL
• rxdlysreset_r : oob
• rxdlysresetdone : gtx_wrap
• RXDLYSRESETDONE : gtxe2_channel_wrapper , GTXE2_GPL
• rxdlysresetdone : GTXE2_GPL
• RXDLYSRESETDONE_DELAY : GTXE2_GPL
• RXDLYSRESETDONE_DURATION : GTXE2_GPL
• rxdlysresetdone_r : gtx_wrap
• RXELECIDLE : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_rx
• rxelecidle : gtxe2_chnl_rx_align
• RXELECIDLE : gtxe2_chnl_rx_oob , GTXE2_GPL
• rxelecidle : oob , oob_dev , sata_phy , sata_phy_dev
• rxelecidle_in : oob , oob_ctrl , oob_dev
• rxelecidle_r : oob
• rxelecidle_rr : oob
• RXELECIDLEMODE : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_rx , gtxe2_chnl_rx_oob , GTXE2_GPL
• rxelsempty : ahci_sata_layers , sata_phy
• rxelsfull : ahci_sata_layers , sata_phy
• rxeyereset_cnt : sata_phy , sata_phy_dev
• rxeyereset_done : sata_phy , sata_phy_dev
• RXEYERESET_TIME : sata_phy , sata_phy_dev
• RXGEARBOX_EN : gtxe2_channel_wrapper , GTXE2_GPL
• RXGEARBOXSLIP : gtxe2_channel_wrapper , GTXE2_GPL
• RXHEADER : gtxe2_channel_wrapper , GTXE2_GPL
• RXHEADERVALID : gtxe2_channel_wrapper , GTXE2_GPL
• RXISCANRESET_TIME : gtx_wrap , gtxe2_channel_wrapper , GTXE2_GPL , sata_phy , sata_phy_dev
• RXLPM_HF_CFG : gtxe2_channel_wrapper , GTXE2_GPL
• RXLPM_LF_CFG : gtxe2_channel_wrapper , GTXE2_GPL
• RXLPMEN : gtx_wrap , gtxe2_channel_wrapper , GTXE2_GPL
• RXLPMHFHOLD : gtxe2_channel_wrapper , GTXE2_GPL
• RXLPMHFOVRDEN : gtxe2_channel_wrapper , GTXE2_GPL
• RXLPMLFHOLD : gtxe2_channel_wrapper , GTXE2_GPL
• RXLPMLFKLOVRDEN : gtxe2_channel_wrapper , GTXE2_GPL
• RXMCOMMAALIGNEN : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_rx , gtxe2_chnl_rx_align , GTXE2_GPL
• RXMONITOROUT : gtxe2_channel_wrapper , GTXE2_GPL
• RXMONITORSEL : gtxe2_channel_wrapper , GTXE2_GPL
• RXN : gtxe2_chnl , gtxe2_chnl_rx , gtxe2_chnl_rx_oob , sata_ahci_top
• rxn : sata_phy , sata_phy_dev
• RXN : x393
• rxn_in : ahci_sata_layers , sata_phy , sata_phy_dev
• RXNOTINTABLE : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_rx
• rxnotintable : gtxe2_chnl_rx_10x8dec
• RXNOTINTABLE : GTXE2_GPL
• rxnotintable : sata_phy , sata_phy_dev
• rxnotintable_dec_out : gtx_wrap
• rxnotintable_gtx : sata_phy_dev
• RXOOB_CFG : gtxe2_channel_wrapper , GTXE2_GPL
• RXOOBRESET : gtxe2_channel_wrapper , GTXE2_GPL
• RXOSHOLD : gtxe2_channel_wrapper , GTXE2_GPL
• RXOSOVRDEN : gtxe2_channel_wrapper , GTXE2_GPL
• RXOUT_DIV : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_clocking , gtxe2_chnl_cpll , GTXE2_GPL
• RXOUTCLK : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_clocking , GTXE2_GPL
• RXOUTCLKFABRIC : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_clocking , GTXE2_GPL
• RXOUTCLKPCS : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_clocking , GTXE2_GPL
• RXOUTCLKPMA : gtxe2_chnl , gtxe2_chnl_clocking
• RXOUTCLKSEL : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_clocking , GTXE2_GPL
• RXP : gtxe2_chnl , gtxe2_chnl_rx , gtxe2_chnl_rx_oob , sata_ahci_top
• rxp : sata_phy , sata_phy_dev
• RXP : x393
• rxp_in : ahci_sata_layers , sata_phy , sata_phy_dev
• RXPCOMMAALIGNEN : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_rx , gtxe2_chnl_rx_align , GTXE2_GPL
• RXPCSRESET : gtxe2_channel_wrapper , GTXE2_GPL
• RXPCSRESET_TIME : gtxe2_channel_wrapper , GTXE2_GPL
• RXPD : gtxe2_channel_wrapper , GTXE2_GPL
• RXPH_CFG : gtxe2_channel_wrapper , GTXE2_GPL
• RXPH_MONITOR_SEL : gtxe2_channel_wrapper , GTXE2_GPL
• RXPHALIGN : gtx_wrap , gtxe2_channel_wrapper , GTXE2_GPL
• rxphaligndone : gtx_wrap
• RXPHALIGNDONE : gtxe2_channel_wrapper , GTXE2_GPL
• rxphaligndone : GTXE2_GPL
• rxphaligndone1_r : gtx_wrap
• rxphaligndone2_r : gtx_wrap
• RXPHALIGNDONE_DELAY1 : GTXE2_GPL
• RXPHALIGNDONE_DELAY2 : GTXE2_GPL
• RXPHALIGNDONE_DURATION1 : GTXE2_GPL
• RXPHALIGNEN : gtx_wrap , gtxe2_channel_wrapper , GTXE2_GPL
• RXPHDLY_CFG : gtxe2_channel_wrapper , GTXE2_GPL
• RXPHDLYPD : gtx_wrap , gtxe2_channel_wrapper , GTXE2_GPL
• RXPHDLYRESET : gtx_wrap , gtxe2_channel_wrapper , GTXE2_GPL
• RXPHMONITOR : gtxe2_channel_wrapper , GTXE2_GPL
• RXPHOVRDEN : gtx_wrap , gtxe2_channel_wrapper , GTXE2_GPL
• RXPHSLIPMONITOR : gtxe2_channel_wrapper , GTXE2_GPL
• RXPLLREFCLK_DIV1 : gtxe2_chnl_clocking
• RXPLLREFCLK_DIV2 : gtxe2_chnl_clocking
• RXPMARESET : gtxe2_channel_wrapper , GTXE2_GPL
• RXPMARESET_TIME : gtx_wrap , gtxe2_channel_wrapper , GTXE2_GPL , sata_phy , sata_phy_dev
• RXPOLARITY : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_rx , GTXE2_GPL
• RXPRBS_ERR_LOOPBACK : gtxe2_channel_wrapper , GTXE2_GPL
• RXPRBSCNTRESET : gtxe2_channel_wrapper , GTXE2_GPL
• RXPRBSERR : gtxe2_channel_wrapper , GTXE2_GPL
• RXPRBSSEL : gtxe2_channel_wrapper , GTXE2_GPL
• RXQPIEN : gtxe2_channel_wrapper , GTXE2_GPL
• RXQPISENN : gtxe2_channel_wrapper , GTXE2_GPL
• RXQPISENP : gtxe2_channel_wrapper , GTXE2_GPL
• RXRATE : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_clocking , GTXE2_GPL
• RXRATEDONE : gtxe2_channel_wrapper , GTXE2_GPL
• rxreset : sata_phy , sata_phy_dev
• rxreset_ack : oob , oob_ctrl , sata_phy
• rxreset_f : sata_phy
• rxreset_f_r : sata_phy
• rxreset_f_rr : sata_phy
• rxreset_oob : sata_phy
• rxreset_oob_cnt : sata_phy
• rxreset_oob_stop : sata_phy
• rxreset_req : oob , oob_ctrl , sata_phy
• RXRESETDONE : gtxe2_channel_wrapper , GTXE2_GPL
• rxresetdone : sata_phy , sata_phy_dev
• rxresetdone_gtx : gtx_wrap
• rxresetdone_r : gtx_wrap
• RXSLIDE : gtxe2_channel_wrapper , GTXE2_GPL
• RXSLIDE_AUTO_WAIT : gtxe2_channel_wrapper , GTXE2_GPL
• RXSLIDE_MODE : gtxe2_channel_wrapper , GTXE2_GPL
• RXSTARTOFSEQ : gtxe2_channel_wrapper , GTXE2_GPL
• RXSTATUS : gtxe2_channel_wrapper , GTXE2_GPL
• RXSYSCLKSEL : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_clocking , GTXE2_GPL
• RXUSERRDY : gtxe2_channel_wrapper , GTXE2_GPL
• rxuserrdy : sata_phy , sata_phy_dev
• RXUSRCLK : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_rx , GTXE2_GPL
• rxusrclk : sata_phy_dev
• RXUSRCLK2 : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_rx , GTXE2_GPL
• rxusrclk2 : sata_phy , sata_phy_dev
• RXVALID : gtxe2_channel_wrapper , GTXE2_GPL