Here is a list of all class members with links to the classes they belong to:

- m -

• m2 : csconvert18a
• m3 : csconvert18a
• m_cb : csconvert , csconvert18a , jp_channel
• m_cr : csconvert , csconvert18a , jp_channel
• macroblock_x : cmprs_macroblock_buf_iface , cmprs_pixel_buf_iface , jp_channel
• main_go : sim_soc_interrupts
• many : huff_fifo393
• mask : index_max_16
• mask_a : masked_max_reg
• mask_b : masked_max_reg
• mask_changed : index_max_16
• mask_prev : index_max_16
• masked : condition_mux
• masked_max_reg : index_max_16
• master_chn : camsync393
• match_high : cmd_deser_dual , cmd_deser_multi
• match_low : cmd_deser_dual , cmd_deser_multi , cmd_deser_single
• max : masked_max_reg
• max0001 : index_max_16
• max00010203 : index_max_16
• max0001020304050607 : index_max_16
• max0203 : index_max_16
• max0405 : index_max_16
• max04050607 : index_max_16
• max0607 : index_max_16
• max0809 : index_max_16
• max08091011 : index_max_16
• max0809101112131415 : index_max_16
• max1011 : index_max_16
• max1213 : index_max_16
• max12131415 : index_max_16
• max1415 : index_max_16
• max_inc_ram : cmprs_afi_mux_ptr
• max_inc_ram_wa : cmprs_afi_mux_ptr
• max_inc_ram_we : cmprs_afi_mux_ptr
• max_r : masked_max_reg
• MAX_TILE_HEIGHT : cmd_encod_tiled_mux , mcntrl393 , mcntrl_tiled_rw
• MAX_TILE_WIDTH : cmd_encod_tiled_mux , mcntrl393 , mcntrl_tiled_rw
• max_wlen : cmprs_afi_mux , cmprs_afi_mux_ptr
• max_wlen_r : cmprs_afi_mux_ptr
• max_wlen_same : cmprs_afi_mux_ptr
• maxi0_araddr : x393
• maxi0_arburst : x393
• maxi0_arid : x393
• maxi0_arlen : x393
• maxi0_arready : x393
• maxi0_arsize : x393
• maxi0_arvalid : x393
• maxi0_awaddr : x393
• maxi0_awburst : x393
• maxi0_awid : x393
• maxi0_awlen : x393
• maxi0_awready : x393
• maxi0_awsize : x393
• maxi0_awvalid : x393
• maxi0_bid : x393
• maxi0_bready : x393
• maxi0_bresp : x393
• maxi0_bvalid : x393
• maxi0_rdata : x393
• maxi0_rid : x393
• maxi0_rlast : x393
• maxi0_rready : x393
• maxi0_rresp : x393
• maxi0_rvalid : x393
• maxi0_wdata : x393
• maxi0_wid : x393
• maxi0_wlast : x393
• maxi0_wready : x393
• maxi0_wstb : x393
• maxi0_wvalid : x393
• maxi1_araddr : x393
• maxi1_arburst : x393
• maxi1_arid : x393
• maxi1_arlen : x393
• maxi1_arready : x393
• maxi1_arsize : x393
• maxi1_arvalid : x393
• maxi1_awaddr : x393
• maxi1_awburst : x393
• maxi1_awid : x393
• maxi1_awlen : x393
• maxi1_awready : x393
• maxi1_awsize : x393
• maxi1_awvalid : x393
• maxi1_bid : x393
• maxi1_bready : x393
• maxi1_bresp : x393
• maxi1_bvalid : x393
• maxi1_rdata : x393
• maxi1_rid : x393
• maxi1_rlast : x393
• maxi1_rready : x393
• maxi1_rresp : x393
• maxi1_rvalid : x393
• maxi1_wdata : x393
• maxi1_wid : x393
• maxi1_wlast : x393
• maxi1_wready : x393
• maxi1_wstb : x393
• maxi1_wvalid : x393
• maxigp0 : X393_cocotb_server
• maxigp0aclk : x393_dut
• maxigp0araddr : x393_dut
• maxigp0arburst : x393_dut
• maxigp0arcache : x393_dut
• maxigp0aresetn : x393_dut
• maxigp0arid : x393_dut
• maxigp0arlen : x393_dut
• maxigp0arlock : x393_dut
• maxigp0arprot : x393_dut
• maxigp0arqos : x393_dut
• maxigp0arready : x393_dut
• maxigp0arsize : x393_dut
• maxigp0arvalid : x393_dut
• maxigp0awaddr : x393_dut
• maxigp0awburst : x393_dut
• maxigp0awcache : x393_dut
• maxigp0awid : x393_dut
• maxigp0awlen : x393_dut
• maxigp0awlock : x393_dut
• maxigp0awprot : x393_dut
• maxigp0awqos : x393_dut
• maxigp0awready : x393_dut
• maxigp0awsize : x393_dut
• maxigp0awvalid : x393_dut
• maxigp0bid : x393_dut
• maxigp0bready : x393_dut
• maxigp0bresp : x393_dut
• maxigp0bvalid : x393_dut
• maxigp0rdata : x393_dut
• maxigp0rid : x393_dut
• maxigp0rlast : x393_dut
• maxigp0rready : x393_dut
• maxigp0rresp : x393_dut
• maxigp0rvalid : x393_dut
• maxigp0wdata : x393_dut
• maxigp0wid : x393_dut
• maxigp0wlast : x393_dut
• maxigp0wready : x393_dut
• maxigp0wstrb : x393_dut
• maxigp0wvalid : x393_dut
• mb_col_number : cmprs_pixel_buf_iface
• mb_cols_left : cmprs_macroblock_buf_iface
• mb_data_out : jp_channel
• mb_din : csconvert
• mb_first_in_row : cmprs_macroblock_buf_iface
• mb_h_m1 : cmprs_pixel_buf_iface , cmprs_tile_mode_decode , jp_channel
• mb_hper : cmprs_macroblock_buf_iface , cmprs_tile_mode_decode , jp_channel
• mb_last_in_row : cmprs_macroblock_buf_iface
• mb_last_row : cmprs_macroblock_buf_iface
• mb_pre2_first_out : jp_channel
• mb_pre_end : cmprs_pixel_buf_iface , jp_channel
• mb_pre_end_in : cmprs_macroblock_buf_iface
• mb_pre_end_r : cmprs_pixel_buf_iface
• mb_pre_first_out : jp_channel
• mb_pre_start : cmprs_macroblock_buf_iface , cmprs_pixel_buf_iface , jp_channel
• mb_pre_start4_first : cmprs_macroblock_buf_iface
• mb_pre_start_out : cmprs_macroblock_buf_iface
• mb_pre_start_w : cmprs_macroblock_buf_iface
• mb_release_buf : cmprs_macroblock_buf_iface , cmprs_pixel_buf_iface , jp_channel
• mb_release_buf_r : cmprs_pixel_buf_iface
• mb_rows_left : cmprs_macroblock_buf_iface
• mb_start_addr : cmprs_pixel_buf_iface
• mb_w_m1 : cmprs_macroblock_buf_iface , cmprs_pixel_buf_iface , cmprs_tile_mode_decode , jp_channel
• mbl_x : cmprs_macroblock_buf_iface
• mbl_x_inc_r : cmprs_macroblock_buf_iface
• mbl_x_last_r : cmprs_macroblock_buf_iface
• mbl_x_next_r : cmprs_macroblock_buf_iface
• mbl_x_r : cmprs_macroblock_buf_iface
• mblk_hor : focus_sharp393
• mblk_vert : focus_sharp393
• mclk : ahci_ctrl_stat , ahci_dma , ahci_dma_rd_fifo , ahci_dma_wr_fifo , ahci_fis_receive , ahci_fis_transmit , ahci_fsm , ahci_top , bit_stuffer_metadata , buf_xclk_mclk16_393 , camsync393 , clocks393 , clocks393m , cmd_frame_sequencer , cmd_mux , cmd_readback , cmd_seq_mux , cmprs_afi_mux , cmprs_afi_mux_status , cmprs_cmd_decode , cmprs_frame_sync , cmprs_macroblock_buf_iface , cmprs_status , compressor393 , ddr3_wrap , debug_master , debug_slave , event_logger , focus_sharp393 , frame_num_sync , gpio393 , histogram_saxi , huffman393 , huffman_snglclk , huffman_stuffer_meta , imu_exttime393 , imu_message393 , imu_spi393 , jp_channel , lens_flat393 , mcntrl393 , mcntrl393_test01 , mcntrl_linear_rw , mcntrl_ps_pio , mcntrl_tiled_rw , mcontr_sequencer , membridge , memctrl16 , mult_saxi_wr , mult_saxi_wr_chn , mult_saxi_wr_inbuf , mult_saxi_wr_pointers , nmea_decoder393 , phy_cmd , phy_top , pxd_clock , pxd_single , quantizer393 , rtc393 , sens_10398 , sens_gamma , sens_hispi12l4 , sens_hispi_clock , sens_hispi_din , sens_hist_ram_double , sens_hist_ram_nobuff , sens_hist_ram_single , sens_hist_ram_snglclk_18 , sens_hist_ram_snglclk_32 , sens_histogram , sens_histogram_mux , sens_histogram_snglclk , sens_parallel12 , sens_sync , sensor_channel , sensor_i2c , sensor_i2c_io , sensor_i2c_prot , sensor_i2c_scl_sda , sensor_membuf , sensors393
• MCLK : simul_sensor12bits
• mclk : stuffer393 , timing393 , x393
• MCLK_PHASE : mcntrl393 , mcontr_sequencer , memctrl16 , phy_cmd , phy_top
• mclk_pre : phy_top
• mclk_rst : sens_parallel12
• mcntrl393 : x393
• mcntrl393_test01 : x393
• mcntrl_axird_rdata : x393
• mcntrl_axird_selected : x393
• mcntrl_axird_selected_regen : x393
• mcntrl_axird_selected_ren : x393
• mcntrl_buf_rd : jp_channel , mcntrl393 , mcntrl_ps_pio , membridge
• mcntrl_buf_wr : mcntrl393 , mcntrl_ps_pio , membridge , sensor_membuf
• mcntrl_linear_rw : mcntrl393
• mcntrl_locked : x393
• MCNTRL_PS_ADDR : mcntrl393 , mcntrl_ps_pio
• MCNTRL_PS_CMD : mcntrl393 , mcntrl_ps_pio
• MCNTRL_PS_EN_RST : mcntrl393 , mcntrl_ps_pio
• MCNTRL_PS_MASK : mcntrl393 , mcntrl_ps_pio
• mcntrl_ps_pio : mcntrl393
• MCNTRL_PS_STATUS_CNTRL : mcntrl393 , mcntrl_ps_pio
• MCNTRL_PS_STATUS_REG_ADDR : mcntrl393 , mcntrl_ps_pio
• MCNTRL_SCANLINE_ADDR : mcntrl_linear_rw
• MCNTRL_SCANLINE_CHN1_ADDR : mcntrl393
• MCNTRL_SCANLINE_CHN3_ADDR : mcntrl393
• MCNTRL_SCANLINE_FRAME_FULL_WIDTH : mcntrl393 , mcntrl_linear_rw
• MCNTRL_SCANLINE_FRAME_LAST : mcntrl393 , mcntrl_linear_rw
• MCNTRL_SCANLINE_FRAME_PAGE_RESET : mcntrl393 , mcntrl_linear_rw
• MCNTRL_SCANLINE_FRAME_SIZE : mcntrl393 , mcntrl_linear_rw
• MCNTRL_SCANLINE_MASK : mcntrl393 , mcntrl_linear_rw
• MCNTRL_SCANLINE_MODE : mcntrl393 , mcntrl_linear_rw
• MCNTRL_SCANLINE_PENDING_CNTR_BITS : mcntrl393 , mcntrl_linear_rw
• MCNTRL_SCANLINE_STARTADDR : mcntrl393 , mcntrl_linear_rw
• MCNTRL_SCANLINE_STATUS_CNTRL : mcntrl393 , mcntrl_linear_rw
• MCNTRL_SCANLINE_STATUS_REG_ADDR : mcntrl_linear_rw
• MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR : mcntrl393
• MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR : mcntrl393
• MCNTRL_SCANLINE_WINDOW_STARTXY : mcntrl393 , mcntrl_linear_rw
• MCNTRL_SCANLINE_WINDOW_WH : mcntrl393 , mcntrl_linear_rw
• MCNTRL_SCANLINE_WINDOW_X0Y0 : mcntrl393 , mcntrl_linear_rw
• MCNTRL_TEST01_ADDR : mcntrl393_test01
• MCNTRL_TEST01_CHN1_MODE : mcntrl393_test01
• MCNTRL_TEST01_CHN1_STATUS_CNTRL : mcntrl393_test01
• MCNTRL_TEST01_CHN2_MODE : mcntrl393_test01
• MCNTRL_TEST01_CHN2_STATUS_CNTRL : mcntrl393_test01
• MCNTRL_TEST01_CHN3_MODE : mcntrl393_test01
• MCNTRL_TEST01_CHN3_STATUS_CNTRL : mcntrl393_test01
• MCNTRL_TEST01_CHN4_MODE : mcntrl393_test01
• MCNTRL_TEST01_CHN4_STATUS_CNTRL : mcntrl393_test01
• MCNTRL_TEST01_MASK : mcntrl393_test01
• MCNTRL_TEST01_STATUS_REG_CHN1_ADDR : mcntrl393_test01
• MCNTRL_TEST01_STATUS_REG_CHN2_ADDR : mcntrl393_test01
• MCNTRL_TEST01_STATUS_REG_CHN3_ADDR : mcntrl393_test01
• MCNTRL_TEST01_STATUS_REG_CHN4_ADDR : mcntrl393_test01
• MCNTRL_TILED_ADDR : mcntrl_tiled_rw
• MCNTRL_TILED_CHN2_ADDR : mcntrl393
• MCNTRL_TILED_CHN4_ADDR : mcntrl393
• MCNTRL_TILED_FRAME_FULL_WIDTH : mcntrl393 , mcntrl_tiled_rw
• MCNTRL_TILED_FRAME_LAST : mcntrl393 , mcntrl_tiled_rw
• MCNTRL_TILED_FRAME_PAGE_RESET : mcntrl393 , mcntrl_tiled_rw
• MCNTRL_TILED_FRAME_SIZE : mcntrl393 , mcntrl_tiled_rw
• MCNTRL_TILED_MASK : mcntrl393 , mcntrl_tiled_rw
• MCNTRL_TILED_MODE : mcntrl393 , mcntrl_tiled_rw
• MCNTRL_TILED_PENDING_CNTR_BITS : mcntrl393 , mcntrl_tiled_rw
• mcntrl_tiled_rw : mcntrl393
• MCNTRL_TILED_STARTADDR : mcntrl393 , mcntrl_tiled_rw
• MCNTRL_TILED_STATUS_CNTRL : mcntrl393 , mcntrl_tiled_rw
• MCNTRL_TILED_STATUS_REG_ADDR : mcntrl_tiled_rw
• MCNTRL_TILED_STATUS_REG_CHN2_ADDR : mcntrl393
• MCNTRL_TILED_STATUS_REG_CHN4_ADDR : mcntrl393
• MCNTRL_TILED_TILE_WHS : mcntrl393 , mcntrl_tiled_rw
• MCNTRL_TILED_WINDOW_STARTXY : mcntrl393 , mcntrl_tiled_rw
• MCNTRL_TILED_WINDOW_WH : mcntrl393 , mcntrl_tiled_rw
• MCNTRL_TILED_WINDOW_X0Y0 : mcntrl393 , mcntrl_tiled_rw
• mcomma_match : gtxe2_chnl_rx_align
• mcont_common_chnbuf_reg : memctrl16
• mcont_from_chnbuf_reg : memctrl16
• mcont_to_chnbuf_reg : memctrl16
• mcontr_0bit_addr : memctrl16
• mcontr_0bit_we : memctrl16
• mcontr_16bit_addr : memctrl16
• mcontr_16bit_data : memctrl16
• mcontr_16bit_we : memctrl16
• MCONTR_ARBIT_ADDR : mcntrl393 , memctrl16
• MCONTR_ARBIT_ADDR_MASK : mcntrl393 , memctrl16
• MCONTR_BUF0_RD_ADDR : mcntrl393
• MCONTR_BUF0_WR_ADDR : mcntrl393
• MCONTR_BUF2_RD_ADDR : mcntrl393
• MCONTR_BUF2_WR_ADDR : mcntrl393
• MCONTR_BUF3_RD_ADDR : mcntrl393
• MCONTR_BUF3_WR_ADDR : mcntrl393
• MCONTR_BUF4_RD_ADDR : mcntrl393
• MCONTR_BUF4_WR_ADDR : mcntrl393
• mcontr_chn_en : memctrl16
• MCONTR_CMD_WR_ADDR : mcntrl393
• MCONTR_CMPRS_BASE : mcntrl393
• MCONTR_CMPRS_INC : mcntrl393
• MCONTR_CMPRS_STATUS_BASE : mcntrl393
• MCONTR_CMPRS_STATUS_INC : mcntrl393
• mcontr_en : memctrl16
• mcontr_enabled : memctrl16
• MCONTR_LINTILE_BYTE32 : mcntrl393 , mcntrl_tiled_rw
• MCONTR_LINTILE_DIS_NEED : mcntrl393 , mcntrl_linear_rw , mcntrl_tiled_rw
• MCONTR_LINTILE_EN : mcntrl393 , mcntrl_linear_rw , mcntrl_tiled_rw
• MCONTR_LINTILE_EXTRAPG : mcntrl393 , mcntrl_linear_rw , mcntrl_tiled_rw
• MCONTR_LINTILE_EXTRAPG_BITS : mcntrl393 , mcntrl_linear_rw , mcntrl_tiled_rw
• MCONTR_LINTILE_KEEP_OPEN : mcntrl393 , mcntrl_tiled_rw
• MCONTR_LINTILE_NRESET : mcntrl393 , mcntrl_linear_rw , mcntrl_tiled_rw
• MCONTR_LINTILE_REPEAT : mcntrl393 , mcntrl_linear_rw , mcntrl_tiled_rw
• MCONTR_LINTILE_RST_FRAME : mcntrl393 , mcntrl_linear_rw , mcntrl_tiled_rw
• MCONTR_LINTILE_SINGLE : mcntrl393 , mcntrl_linear_rw , mcntrl_tiled_rw
• MCONTR_LINTILE_SKIP_LATE : mcntrl393 , mcntrl_linear_rw
• MCONTR_LINTILE_WRITE : mcntrl393 , mcntrl_linear_rw , mcntrl_tiled_rw
• MCONTR_PHY_0BIT_ADDR : mcntrl393 , mcontr_sequencer , memctrl16
• MCONTR_PHY_0BIT_ADDR_MASK : mcntrl393 , mcontr_sequencer , memctrl16
• MCONTR_PHY_0BIT_CKE_EN : mcntrl393 , mcontr_sequencer , memctrl16
• MCONTR_PHY_0BIT_CMDA_EN : mcntrl393 , mcontr_sequencer , memctrl16
• MCONTR_PHY_0BIT_DCI_RST : mcntrl393 , mcontr_sequencer , memctrl16
• MCONTR_PHY_0BIT_DLY_RST : mcntrl393 , mcontr_sequencer , memctrl16
• MCONTR_PHY_0BIT_DLY_SET : mcntrl393 , mcontr_sequencer , memctrl16
• MCONTR_PHY_0BIT_SDRST_ACT : mcntrl393 , mcontr_sequencer , memctrl16
• MCONTR_PHY_16BIT_ADDR : mcntrl393 , mcontr_sequencer , memctrl16
• MCONTR_PHY_16BIT_ADDR_MASK : mcntrl393 , mcontr_sequencer , memctrl16
• MCONTR_PHY_16BIT_EXTRA : mcntrl393 , mcontr_sequencer , memctrl16
• MCONTR_PHY_16BIT_PATTERNS : mcntrl393 , mcontr_sequencer , memctrl16
• MCONTR_PHY_16BIT_PATTERNS_TRI : mcntrl393 , mcontr_sequencer , memctrl16
• MCONTR_PHY_16BIT_WBUF_DELAY : mcntrl393 , mcontr_sequencer , memctrl16
• MCONTR_PHY_STATUS_CNTRL : mcntrl393 , mcontr_sequencer , memctrl16
• MCONTR_PHY_STATUS_REG_ADDR : mcntrl393 , mcontr_sequencer , memctrl16
• MCONTR_RD_MASK : mcntrl393
• mcontr_reset : mcontr_sequencer , memctrl16
• MCONTR_SENS_BASE : mcntrl393
• MCONTR_SENS_INC : mcntrl393
• MCONTR_SENS_STATUS_BASE : mcntrl393
• MCONTR_SENS_STATUS_INC : mcntrl393
• mcontr_sequencer : memctrl16
• MCONTR_TOP_0BIT_ADDR : mcntrl393 , memctrl16
• MCONTR_TOP_0BIT_ADDR_MASK : mcntrl393 , memctrl16
• MCONTR_TOP_0BIT_MCONTR_EN : mcntrl393 , memctrl16
• MCONTR_TOP_0BIT_REFRESH_EN : mcntrl393 , memctrl16
• MCONTR_TOP_16BIT_ADDR : mcntrl393 , memctrl16
• MCONTR_TOP_16BIT_ADDR_MASK : mcntrl393 , memctrl16
• MCONTR_TOP_16BIT_CHN_EN : mcntrl393 , memctrl16
• MCONTR_TOP_16BIT_REFRESH_ADDRESS : mcntrl393 , memctrl16
• MCONTR_TOP_16BIT_REFRESH_PERIOD : mcntrl393 , memctrl16
• MCONTR_TOP_16BIT_STATUS_CNTRL : mcntrl393 , memctrl16
• MCONTR_TOP_STATUS_REG_ADDR : mcntrl393 , memctrl16
• MCONTR_WR_MASK : mcntrl393
• mem_page_left : mcntrl_linear_rw , mcntrl_tiled_rw
• mem_ra : fifo_sameclock_control
• mem_re : fifo_sameclock_control , sensor_i2c_prot
• mem_read_mode : mcontr_sequencer
• mem_regen : fifo_sameclock_control
• mem_valid : sensor_i2c_prot
• mem_wa : fifo_sameclock_control
• membridge : x393
• MEMBRIDGE_ADDR : membridge
• MEMBRIDGE_CTRL : membridge
• MEMBRIDGE_LEN64 : membridge
• MEMBRIDGE_LO_ADDR64 : membridge
• MEMBRIDGE_MASK : membridge
• MEMBRIDGE_MODE : membridge
• MEMBRIDGE_SIZE64 : membridge
• MEMBRIDGE_START64 : membridge
• MEMBRIDGE_STATUS_CNTRL : membridge
• MEMBRIDGE_STATUS_REG : membridge
• MEMBRIDGE_WIDTH64 : membridge
• memclk : clocks393 , clocks393m , simul_clk , x393 , x393_dut
• MEMCLK_CAPACITANCE : clocks393 , clocks393m
• MEMCLK_IBUF_LOW_PWR : clocks393 , clocks393m
• MEMCLK_IOSTANDARD : clocks393 , clocks393m
• memclk_pad : clocks393 , clocks393m
• MEMCLK_PERIOD : simul_clk
• memclk_rst : clocks393 , clocks393m
• memctrl16 : mcntrl393
• memen_even : sens_histogram_snglclk
• memen_odd : sens_histogram_snglclk
• memhigh : X393_cocotb_server
• memlow : X393_cocotb_server
• memory_frames_compressor : frame_num_sync
• memory_frames_sensor : frame_num_sync
• mempath : X393_cocotb_server
• message_trig : event_logger
• meta_last : bit_stuffer_metadata
• meta_out : bit_stuffer_metadata
• meta_word : bit_stuffer_metadata
• miso : event_logger , imu_spi393
• miso_reg : imu_spi393
• mm1 : csconvert18a
• mm2 : csconvert18a
• mm3 : csconvert18a
• mmcm_phase_cntr : phy_top , sens_hispi_clock , sens_parallel12
• MMCME2_ADV : mmcm_adv , mmcm_phase_cntr
• mode : focus_sharp393 , histogram_saxi , sens_gamma , sensor_channel , status_generate_extra , status_generate_only
• MODE_16_BITS : table_ad_receive
• mode_data_mclk : cmprs_afi_mux_status
• MODE_DDR : oserdes_mem
• mode_hclk : cmprs_afi_mux_status
• mode_mclk : sens_gamma
• mode_reg : mcntrl_linear_rw , mcntrl_tiled_rw , membridge , mult_saxi_wr
• mode_reg_mclk : membridge
• mode_w : status_generate_extra , status_generate_only
• mode_we : cmprs_afi_mux_status
• mode_we_hclk : cmprs_afi_mux_status
• MODE_WIDTH : cmprs_afi_mux_status
• mono : csconvert18a
• mono16_n000 : csconvert
• mono16_n255 : csconvert
• mono16_pre_first_out : csconvert
• mono16_signed_y : csconvert
• mono16_yaddrw : csconvert
• mono16_ywe : csconvert
• monochrome : sens_histogram
• monochrome_2x : sens_histogram
• monochrome_pclk : sens_histogram
• more_words_avail : ahci_dma_rd_stuff
• mosi : event_logger , imu_spi393
• mosi_reg : imu_spi393
• mpullup : sens_10398 , sens_parallel12 , sensor_i2c_io
• MPY_WIDTH : mcntrl_linear_rw , mcntrl_tiled_rw
• mrst : ahci_ctrl_stat , ahci_dma , ahci_dma_rd_fifo , ahci_dma_wr_fifo , ahci_top , bit_stuffer_metadata , camsync393 , clocks393 , clocks393m , cmd_encod_4mux , cmd_encod_linear_rd , cmd_encod_linear_rw , cmd_encod_linear_wr , cmd_encod_tiled_32_rd , cmd_encod_tiled_32_rw , cmd_encod_tiled_32_wr , cmd_encod_tiled_rd , cmd_encod_tiled_rw , cmd_encod_tiled_wr , cmd_frame_sequencer , cmd_mux , cmd_readback , cmd_seq_mux , cmprs_afi_mux , cmprs_afi_mux_status , cmprs_cmd_decode , cmprs_frame_sync , cmprs_macroblock_buf_iface , cmprs_status , compressor393 , ddr_refresh , debug_master , debug_slave , event_logger , fifo_2regs , frame_num_sync , gpio393 , histogram_saxi , huffman_stuffer_meta , imu_exttime393 , jp_channel , lens_flat393 , mcntrl393 , mcntrl393_test01 , mcntrl_linear_rw , mcntrl_ps_pio , mcntrl_tiled_rw , mcontr_sequencer , membridge , memctrl16 , mult_saxi_wr , phy_cmd , phy_top , pxd_single , rtc393 , scheduler16 , sens_10398 , sens_gamma , sens_hispi12l4 , sens_hispi_clock , sens_hispi_din , sens_histogram , sens_histogram_snglclk , sens_parallel12 , sens_sync , sensor_channel , sensor_i2c , sensor_i2c_io , sensor_i2c_prot , sensor_i2c_scl_sda , sensor_membuf , sensors393
• MRST : simul_sensor12bits
• mrst : status_read , stuffer393 , sync_resets , timing393 , x393
• mrst_hclk : ahci_dma_rd_fifo
• mrstn : membridge
• msb : nmea_decoder393
• MSB_FIRST : iserdes_mem , par12_hispi_psp4l , par12_hispi_psp4l_lane
• msb_in_r : datascope_incoming , elastic1632
• MSB_INDEX : sens_hispi_lane
• msg1hot : status_generate_extra
• msg_data : event_logger
• msg_is_last : status_generate_extra
• msg_is_status : status_generate_extra
• msg_num : status_generate_extra
• msk0001 : index_max_16
• msk00010203 : index_max_16
• msk0001020304050607 : index_max_16
• msk0203 : index_max_16
• msk0405 : index_max_16
• msk04050607 : index_max_16
• msk0607 : index_max_16
• msk0809 : index_max_16
• msk08091011 : index_max_16
• msk0809101112131415 : index_max_16
• msk1011 : index_max_16
• msk1213 : index_max_16
• msk12131415 : index_max_16
• msk1415 : index_max_16
• msw_zero : mcntrl_linear_rw , mcntrl_tiled_rw
• mul1_a : lens_flat393
• mul1_b : lens_flat393
• mul1_p : lens_flat393
• mul2_a : lens_flat393
• mul2_b : lens_flat393
• mul2_p : lens_flat393
• mul_rslt : mcntrl_linear_rw , mcntrl_tiled_rw
• mul_rslt_w : mcntrl_linear_rw , mcntrl_tiled_rw
• mult_a : focus_sharp393
• mult_a_r : focus_sharp393
• mult_b : focus_sharp393
• mult_b_r : focus_sharp393
• mult_clk : gtxe2_chnl_cpll
• mult_dev_clk : gtxe2_chnl_cpll
• mult_first_res : lens_flat393
• mult_first_scaled : lens_flat393
• mult_p : focus_sharp393
• mult_p_r : focus_sharp393
• mult_s : focus_sharp393
• MULT_SAXI_ADDR : mult_saxi_wr
• MULT_SAXI_ADV_RD : mult_saxi_wr , mult_saxi_wr_chn
• MULT_SAXI_ADV_WR : mult_saxi_wr , mult_saxi_wr_chn
• MULT_SAXI_AWCACHE : mult_saxi_wr
• MULT_SAXI_BSLOG : mult_saxi_wr_chn , mult_saxi_wr_inbuf
• MULT_SAXI_BSLOG0 : mult_saxi_wr , mult_saxi_wr_pointers
• MULT_SAXI_BSLOG1 : mult_saxi_wr , mult_saxi_wr_pointers
• MULT_SAXI_BSLOG2 : mult_saxi_wr , mult_saxi_wr_pointers
• MULT_SAXI_BSLOG3 : mult_saxi_wr , mult_saxi_wr_pointers
• MULT_SAXI_CNTRL_ADDR : mult_saxi_wr
• MULT_SAXI_CNTRL_MASK : mult_saxi_wr
• MULT_SAXI_HALF_BRAM : mult_saxi_wr , mult_saxi_wr_chn
• MULT_SAXI_HALF_BRAM_IN : mult_saxi_wr_inbuf
• MULT_SAXI_MASK : mult_saxi_wr
• MULT_SAXI_STATUS_REG : mult_saxi_wr
• MULT_SAXI_WLOG : mult_saxi_wr_inbuf
• mult_saxi_wr : x393
• mult_saxi_wr_chn : mult_saxi_wr
• mult_saxi_wr_inbuf : x393
• mult_saxi_wr_pointers : mult_saxi_wr
• mult_second_res : lens_flat393
• multi_clkfb : clocks393m
• MULTICLK_BUF_AXIHP : clocks393m
• MULTICLK_BUF_DLYREF : clocks393m
• MULTICLK_BUF_SYNC : clocks393m
• MULTICLK_BUF_XCLK : clocks393m
• MULTICLK_DIV_AXIHP : clocks393m
• MULTICLK_DIV_DLYREF : clocks393m
• MULTICLK_DIV_SYNC : clocks393m
• MULTICLK_DIV_XCLK : clocks393m
• MULTICLK_DIVCLK : clocks393m
• MULTICLK_IN_PERIOD : clocks393m
• MULTICLK_MULT : clocks393m
• MULTICLK_PHASE_AXIHP : clocks393m
• MULTICLK_PHASE_DLYREF : clocks393m
• MULTICLK_PHASE_FB : clocks393m
• MULTICLK_PHASE_SYNC : clocks393m
• MULTICLK_PHASE_XCLK : clocks393m
• multiplier : gtxe2_chnl_cpll
• MULTIPLIER : simul_clk_div_mult , simul_clk_mult , simul_clk_mult_div
• multipulse_cross_clock : cmprs_macroblock_buf_iface
• mux_data_final : event_logger
• mux_data_source : event_logger
• mux_data_valid : event_logger
• mux_minus : csconvert_jp4diff
• mux_minus_sel : csconvert_jp4diff
• mux_plus : csconvert_jp4diff
• mux_plus_sel : csconvert_jp4diff
• mux_rdy_source : event_logger
• mux_sel : histogram_saxi , sens_histogram_mux
• mx0 : ahci_dma_wr_fifo
• mx1 : ahci_dma_wr_fifo
• mx2 : ahci_dma_wr_fifo
• mx3 : ahci_dma_wr_fifo