Here is a list of all class members with links to the classes they belong to:

- c -

• c : simul_sensor12bits
• c_out : cmprs_buf_average
• C_ram : lens_flat393
• c_rand : simul_sensor12bits
• c_ren : cmprs_buf_average
• c_ren_r : cmprs_buf_average
• cache_debug : membridge
• caddr : csconvert18a
• caddr_r : csconvert18a
• caddr_r2 : csconvert18a
• caddrw : cmprs_buf_average , csconvert , jp_channel
• calc_idw() : gtxe2_chnl_rx , gtxe2_chnl_tx
• calc_ifdw() : gtxe2_chnl_rx , gtxe2_chnl_tx
• calc_valid : mcntrl_linear_rw , mcntrl_tiled_rw
• camsync393 : timing393
• CAMSYNC_ADDR : camsync393 , timing393
• CAMSYNC_CHN_EN_BIT : camsync393 , timing393
• camsync_clk : x393
• CAMSYNC_EN_BIT : camsync393 , timing393
• CAMSYNC_EXTERNAL_BIT : camsync393 , timing393
• CAMSYNC_MASK : camsync393 , timing393
• CAMSYNC_MASTER_BIT : camsync393 , timing393
• CAMSYNC_MODE : camsync393 , timing393
• CAMSYNC_POST_MAGIC : camsync393 , timing393
• CAMSYNC_PRE_MAGIC : camsync393 , timing393
• CAMSYNC_SNDEN_BIT : camsync393 , timing393
• CAMSYNC_TRIG_DELAY0 : camsync393 , timing393
• CAMSYNC_TRIG_DELAY1 : camsync393 , timing393
• CAMSYNC_TRIG_DELAY2 : camsync393 , timing393
• CAMSYNC_TRIG_DELAY3 : camsync393 , timing393
• CAMSYNC_TRIG_DST : camsync393 , timing393
• CAMSYNC_TRIG_PERIOD : camsync393 , timing393
• CAMSYNC_TRIG_SRC : camsync393 , timing393
• CAMSYNC_TRIGGERED_BIT : camsync393 , timing393
• can_start_w : cmd_mux
• CAPACITANCE : ibuf_ibufg , ibufds_ibufgds , ibufds_ibufgds_50 , ibufg , IBUFG , ibufgds , IBUFGDS , obuf , obufds , oddr_ds
• CBCC_DATA_SOURCE_SEL : gtxe2_channel_wrapper , GTXE2_GPL
• cbcr : csconvert18a
• cbcrmult1 : csconvert18a
• cbcrmult2 : csconvert18a
• cbcrmult2_r : csconvert18a
• cbcrmulto : csconvert18a
• cbcrmultr : csconvert18a
• ccv_out_start : cmprs_buf_average
• ccv_out_start_d : cmprs_buf_average
• cdata : sens_gamma
• ce : condition_mux , latch_g_ce , oddr , oddr_ds , oddr_ss
• cea : dsp_addsub_simd
• cea1 : dsp_ma , dsp_ma_preadd
• cea2 : dsp_ma , dsp_ma_preadd
• cead : dsp_ma_preadd
• ceb : dsp_addsub_simd
• ceb1 : dsp_ma , dsp_ma_preadd
• ceb2 : dsp_ma , dsp_ma_preadd
• ced : dsp_ma , dsp_ma_preadd
• cep : dsp_addsub_simd
• CFGRESET : gtxe2_channel_wrapper , GTXE2_GPL
• cfis_acmd_left_out_r : ahci_fis_transmit
• cfis_acmd_left_r : ahci_fis_transmit
• CFIS_XMIT : action_decoder
• cfis_xmit : ahci_fis_transmit , ahci_fsm
• ch_a : ahci_fis_transmit , ahci_fsm
• ch_a_r : ahci_fis_transmit
• ch_b : ahci_fis_transmit , ahci_fsm
• ch_b_r : ahci_fis_transmit
• ch_c : ahci_fis_transmit , ahci_fsm
• ch_c_r : ahci_fis_transmit
• ch_cfl : ahci_fis_transmit
• ch_cmd_len_r : ahci_fis_transmit
• ch_en : gpio393
• ch_p : ahci_fis_transmit , ahci_fsm
• ch_p_r : ahci_fis_transmit
• ch_prdtl : ahci_fis_transmit
• ch_prdtl_r : ahci_fis_transmit
• ch_r : ahci_fis_transmit , ahci_fsm
• ch_r_r : ahci_fis_transmit
• ch_w : ahci_fis_transmit , ahci_fsm
• ch_w_r : ahci_fis_transmit
• CHAN_BOND_KEEP_ALIGN : gtxe2_channel_wrapper , GTXE2_GPL
• CHAN_BOND_MAX_SKEW : gtxe2_channel_wrapper , GTXE2_GPL
• CHAN_BOND_SEQ_1_1 : gtxe2_channel_wrapper , GTXE2_GPL
• CHAN_BOND_SEQ_1_2 : gtxe2_channel_wrapper , GTXE2_GPL
• CHAN_BOND_SEQ_1_3 : gtxe2_channel_wrapper , GTXE2_GPL
• CHAN_BOND_SEQ_1_4 : gtxe2_channel_wrapper , GTXE2_GPL
• CHAN_BOND_SEQ_1_ENABLE : gtxe2_channel_wrapper , GTXE2_GPL
• CHAN_BOND_SEQ_2_1 : gtxe2_channel_wrapper , GTXE2_GPL
• CHAN_BOND_SEQ_2_2 : gtxe2_channel_wrapper , GTXE2_GPL
• CHAN_BOND_SEQ_2_3 : gtxe2_channel_wrapper , GTXE2_GPL
• CHAN_BOND_SEQ_2_4 : gtxe2_channel_wrapper , GTXE2_GPL
• CHAN_BOND_SEQ_2_ENABLE : gtxe2_channel_wrapper , GTXE2_GPL
• CHAN_BOND_SEQ_2_USE : gtxe2_channel_wrapper , GTXE2_GPL
• CHAN_BOND_SEQ_LEN : gtxe2_channel_wrapper , GTXE2_GPL
• channel : event_logger , logger_arbiter393
• channel_next : event_logger
• channel_pgm_en : mcntrl_ps_pio
• channel_pgm_en0 : mcntrl393 , memctrl16
• channel_pgm_en1 : mcntrl393 , memctrl16
• channel_pgm_en10 : memctrl16
• channel_pgm_en11 : memctrl16
• channel_pgm_en12 : memctrl16
• channel_pgm_en13 : memctrl16
• channel_pgm_en14 : memctrl16
• channel_pgm_en15 : memctrl16
• channel_pgm_en2 : mcntrl393 , memctrl16
• channel_pgm_en3 : mcntrl393 , memctrl16
• channel_pgm_en4 : mcntrl393 , memctrl16
• channel_pgm_en8 : memctrl16
• channel_pgm_en9 : memctrl16
• channel_r : logger_arbiter393
• channel_ready : event_logger
• channels_ready : logger_arbiter393
• charisk : datascope_incoming , datascope_incoming_raw
• charisk_in : elastic1632 , gtx_elastic
• charisk_in_r : elastic1632
• charisk_out : elastic1632 , gtx_elastic
• charisk_r : datascope_incoming
• chead_bsy : ahci_fis_transmit
• chead_bsy_re : ahci_fis_transmit
• chead_done_w : ahci_fis_transmit
• chn : cmprs_afi_mux_ptr_wresp , imu_timestamps393 , mult_saxi_wr_pointers , round_robin , sens_histogram_mux
• chn1hot : imu_exttime393 , imu_timestamps393 , logger_arbiter393
• CHN_A_WDTH : mult_saxi_wr
• chn_en : camsync393 , mcntrl_linear_rw , mcntrl_ps_pio , mcntrl_tiled_rw , scheduler16 , table_ad_transmit
• chn_en_aclk : mult_saxi_wr_pointers
• chn_en_mclk : mult_saxi_wr_pointers
• chn_en_mclk_r : mult_saxi_wr_pointers
• chn_enc_w : imu_exttime393
• chn_fifo_out : mult_saxi_wr
• chn_grant : histogram_saxi , sens_histogram_mux
• CHN_LATENCY : mcont_from_chnbuf_reg
• chn_need_some : memctrl16
• CHN_NUMBER : mcont_common_chnbuf_reg , mcont_from_chnbuf_reg , mcont_to_chnbuf_reg
• chn_out : mult_saxi_wr
• chn_pri_w : imu_exttime393
• chn_r : cmd_seq_mux , mult_saxi_wr_pointers
• chn_rd : mult_saxi_wr
• chn_rd_data : mult_saxi_wr
• chn_rst : mcntrl_linear_rw , mcntrl_ps_pio , mcntrl_tiled_rw
• chn_rst_d : mcntrl_linear_rw , mcntrl_tiled_rw
• chn_sel : histogram_saxi , sens_histogram_mux
• chn_sel_w : status_router2
• chn_servicing : logger_arbiter393
• chn_start : sens_histogram_mux
• chn_want_r : memctrl16
• chn_want_some : memctrl16
• chn_wr : mult_saxi_wr
• chn_wr_mclk : mult_saxi_wr_pointers
• CHNBUF_READ_LATENCY : mcntrl393 , memctrl16
• chunk_addr : cmprs_afi_mux , cmprs_afi_mux_ptr
• chunk_chn_hclk : cmprs_afi_mux_status
• chunk_inc : cmprs_afi_mux_ptr , cmprs_afi_mux_ptr_wresp
• chunk_inc_want_m1 : cmprs_afi_mux_ptr
• chunk_ptr_hclk : cmprs_afi_mux_status
• chunk_ptr_inc : cmprs_afi_mux_ptr , cmprs_afi_mux_ptr_wresp
• chunk_ptr_ra : cmprs_afi_mux , cmprs_afi_mux_ptr , cmprs_afi_mux_ptr_wresp , cmprs_afi_mux_status
• chunk_ptr_rd : cmprs_afi_mux , cmprs_afi_mux_ptr , cmprs_afi_mux_ptr_wresp , cmprs_afi_mux_status
• chunk_ptr_rd01 : cmprs_afi_mux
• chunk_ptr_rovr : cmprs_afi_mux_ptr_wresp
• chunks_to_rollover : cmprs_afi_mux_ptr
• chunks_to_rollover_m1 : cmprs_afi_mux_ptr
• chunks_to_rollover_r : cmprs_afi_mux_ptr
• CHW_DMAA : condition_mux
• cirq : ahci_ctrl_stat
• cirq_PC : ahci_ctrl_stat
• cirq_PRC : ahci_ctrl_stat
• CLB_OFFS32 : ahci_fis_receive , ahci_fis_transmit
• CLEAR_BSY_DRQ : action_decoder
• clear_bsy_drq : ahci_fis_receive , ahci_fsm
• CLEAR_BSY_SET_DRQ : action_decoder
• clear_bsy_set_drq : ahci_fis_receive , ahci_fsm
• CLEAR_CMD_TO_ISSUE : action_decoder
• clear_pisn32 : ahci_fsm
• clear_prdbc : ahci_fis_receive
• clear_xfer_cntr : ahci_fis_receive , ahci_fsm
• clearCmdToIssue : ahci_fis_transmit , ahci_fsm
• cleared_ghc : ahci_ctrl_stat
• clk : action_decoder , ahci_dma_rd_stuff , ahci_sata_layers , byte_lane , clk_to_clk2x , cmd_addr , cmd_deser , cmd_deser_dual , cmd_deser_multi , cmd_deser_single , cmd_encod_4mux , cmd_encod_linear_mux , cmd_encod_linear_rd , cmd_encod_linear_rw , cmd_encod_linear_wr , cmd_encod_tiled_32_rd , cmd_encod_tiled_32_rw , cmd_encod_tiled_32_wr , cmd_encod_tiled_mux , cmd_encod_tiled_rd , cmd_encod_tiled_rw , cmd_encod_tiled_wr , cmda_single , condition_mux , crc
• CLK : csconvert18a
• clk : csconvert_jp4 , csconvert_jp4diff , csconvert_mono , datascope_incoming , datascope_incoming_raw , datascope_timing , dct1d_chen , dct1d_chen_reorder_in , dct1d_chen_reorder_out , dct2d8x8_chen , dct_chen_transpose , ddr_refresh , dly01_16 , dly_16 , dm_single , dq_single , dqs_single , dqs_single_nofine , dsp_addsub_simd , dsp_ma , dsp_ma_preadd , encoderDCAC393 , fifo_1cycle , fifo_2regs , fifo_same_clock , fifo_same_clock_fill , fifo_sameclock_control , focus_sharp393 , freq_meter , gpio_bit , gtx_10x8dec , gtx_8x10enc , gtx_comma_align , gtxe2_chnl_rx_10x8dec , gtxe2_chnl_rx_align , gtxe2_chnl_rx_oob , gtxe2_chnl_tx_oob , huffman_merge_code_literal , idelay_fine_pipe , idelay_nofine , index_max_16 , level_cross_clocks , level_cross_clocks_ff_bit , level_cross_clocks_single_bit , level_cross_clocks_sync_bit , link , masked_max_reg , mcont_common_chnbuf_reg , mcont_from_chnbuf_reg , mcont_to_chnbuf_reg , oddr , oddr_ds , oddr_ss , odelay_fine_pipe , odelay_pipe , oob , oob_ctrl , oob_dev , oserdes_mem , par12_hispi_psp4l_lane , phy_top , quantizer393 , round_robin , sata_phy , sata_phy_dev , scheduler16 , scrambler , sim_frac_clk_delay , sim_soc_interrupts , simul_axi_fifo , simul_axi_master_rdaddr , simul_axi_master_wdata , simul_axi_master_wraddr , simul_axi_read , simul_axi_slow_ready , simul_clk , simul_clk_single , simul_fifo , status_generate , status_generate_extra , status_generate_only , status_read , status_router16 , status_router2 , status_router4 , status_router8 , stuffer393 , sync_resets , table_ad_receive , table_ad_transmit , timestamp_to_parallel , timestamp_to_serial , varlen_encode393 , varlen_encode_snglclk
• CLK : x393_dut
• clk : zigzag393
• clk1x : dual_clock_source
• clk1x_pre : dual_clock_source
• clk2x : clk_to_clk2x , dual_clock_source , focus_sharp393
• clk2x_pre : dual_clock_source
• clk_a : ram18t_var_w_var_r , ram18tp_var_w_var_r , ramt_var_w_var_r , ramt_var_wb_var_r , ramtp_var_w_var_r
• CLK_ADDR : clocks393 , clocks393m
• clk_axihp : axi_hp_clk
• clk_axihp_pre : axi_hp_clk
• clk_b : ram18t_var_w_var_r , ram18tp_var_w_var_r , ramt_var_w_var_r , ramt_var_wb_var_r , ramtp_var_w_var_r
• CLK_CNTRL : clocks393 , clocks393m
• CLK_COR_KEEP_IDLE : gtxe2_channel_wrapper , GTXE2_GPL
• CLK_COR_MAX_LAT : gtxe2_channel_wrapper , GTXE2_GPL
• CLK_COR_MIN_LAT : gtxe2_channel_wrapper , GTXE2_GPL
• CLK_COR_PRECEDENCE : gtxe2_channel_wrapper , GTXE2_GPL
• CLK_COR_REPEAT_WAIT : gtxe2_channel_wrapper , GTXE2_GPL
• CLK_COR_SEQ_1_1 : gtxe2_channel_wrapper , GTXE2_GPL
• CLK_COR_SEQ_1_2 : gtxe2_channel_wrapper , GTXE2_GPL
• CLK_COR_SEQ_1_3 : gtxe2_channel_wrapper , GTXE2_GPL
• CLK_COR_SEQ_1_4 : gtxe2_channel_wrapper , GTXE2_GPL
• CLK_COR_SEQ_1_ENABLE : gtxe2_channel_wrapper , GTXE2_GPL
• CLK_COR_SEQ_2_1 : gtxe2_channel_wrapper , GTXE2_GPL
• CLK_COR_SEQ_2_2 : gtxe2_channel_wrapper , GTXE2_GPL
• CLK_COR_SEQ_2_3 : gtxe2_channel_wrapper , GTXE2_GPL
• CLK_COR_SEQ_2_4 : gtxe2_channel_wrapper , GTXE2_GPL
• CLK_COR_SEQ_2_ENABLE : gtxe2_channel_wrapper , GTXE2_GPL
• CLK_COR_SEQ_2_USE : gtxe2_channel_wrapper , GTXE2_GPL
• CLK_COR_SEQ_LEN : gtxe2_channel_wrapper , GTXE2_GPL
• CLK_CORRECT_USE : gtxe2_channel_wrapper , GTXE2_GPL
• CLK_DELAY : ddr3_wrap
• CLK_DELAY_H : ddr3_wrap
• CLK_DELAY_HSDCLK_D : ddr3_wrap
• CLK_DELAY_HSDCLK_H1 : ddr3_wrap
• CLK_DELAY_HSDCLK_H2 : ddr3_wrap
• CLK_DELAY_HSDCLK_H3 : ddr3_wrap
• CLK_DELAY_HSDNCLK_D : ddr3_wrap
• CLK_DELAY_HSDNCLK_H1 : ddr3_wrap
• CLK_DELAY_HSDNCLK_H2 : ddr3_wrap
• CLK_DELAY_HSDNCLK_H3 : ddr3_wrap
• clk_div : byte_lane , cmd_addr , cmda_single , dm_single , dq_single , dqs_single , dqs_single_nofine , imu_spi393 , oserdes_mem , phy_cmd , phy_top
• CLK_DIV_PHASE : mcntrl393 , mcontr_sequencer , memctrl16 , phy_cmd , phy_top
• clk_div_pre : phy_top
• CLK_DLY : par12_hispi_psp4l
• clk_en : imu_spi393
• clk_fb : phy_top , sens_hispi_clock , sens_parallel12
• clk_flush : huffman393 , huffman_snglclk , huffman_stuffer_meta
• clk_in : axi_hp_clk , clock_divider , clock_inverter , dual_clock_source , mcntrl393 , mcontr_sequencer , memctrl16 , phy_cmd , phy_top , sens_hispi_clock , sim_clk_div , simul_clk_div_mult , simul_clk_mult , simul_clk_mult_div
• clk_int : sens_hispi_clock , simul_clk_div_mult , simul_clk_mult_div
• CLK_MASK : clocks393 , clocks393m
• clk_mux_out : gtxe2_chnl_clocking
• clk_n : par12_hispi_psp4l , sens_hispi_clock
• clk_out : clock_divider , clock_inverter , gtxe2_chnl_cpll , sim_clk_div , simul_clk_div_mult , simul_clk_mult , simul_clk_mult_div
• clk_out_r : sim_clk_div , simul_clk_mult
• clk_p : par12_hispi_psp4l
• CLK_PHASE : mcntrl393 , mcontr_sequencer , memctrl16 , phy_cmd , phy_top
• clk_phase_align_ack : oob , oob_ctrl , sata_phy
• clk_phase_align_req : oob , oob_ctrl , sata_phy
• clk_pn : par12_hispi_psp4l
• clk_pn_dly : par12_hispi_psp4l
• clk_pre : phy_top
• CLK_PWDWN : clocks393 , clocks393m
• clk_r : simul_clk_single
• clk_rd : resync_fifo_nonsynt
• CLK_RESET : clocks393 , clocks393m
• clk_reset : GTXE2_GPL
• CLK_SPEED_GRADE : oob , oob_ctrl , oob_dev
• CLK_STATUS : clocks393 , clocks393m
• CLK_STATUS_REG_ADDR : clocks393 , clocks393m
• clk_sync : clk_to_clk2x
• CLK_TO_TIMER_CONTRIB : oob
• clk_wr : resync_fifo_nonsynt
• clkdiv2 : focus_sharp393
• clkfb : dual_clock_source
• clkfb_axihp : axi_hp_clk
• clkfb_pxd_stopped_mmcm : sens_10398 , sens_hispi12l4 , sens_hispi_clock , sens_parallel12
• clkfb_stopped : mmcm_phase_cntr
• clkfb_stopped_mmcm : phy_top
• clkfbin : mmcm_adv , mmcm_phase_cntr , pll_base
• clkfbout : mmcm_adv , mmcm_phase_cntr , pll_base
• CLKFBOUT_DIV_AXIHP : axi_hp_clk
• CLKFBOUT_MULT : dual_clock_source , mcntrl393 , mcontr_sequencer , memctrl16 , phy_cmd , phy_top , pll_base
• CLKFBOUT_MULT_AXIHP : axi_hp_clk , clocks393
• CLKFBOUT_MULT_F : mmcm_adv , mmcm_phase_cntr
• CLKFBOUT_MULT_PCLK : clocks393 , clocks393m
• CLKFBOUT_MULT_SENSOR : sens_10398 , sens_hispi12l4 , sens_hispi_clock , sens_parallel12 , sensor_channel , sensors393
• CLKFBOUT_MULT_SYNC : clocks393
• CLKFBOUT_MULT_XCLK : clocks393
• CLKFBOUT_PHASE : mcntrl393 , mcontr_sequencer , memctrl16 , mmcm_adv , mmcm_phase_cntr , phy_cmd , phy_top , pll_base
• CLKFBOUT_PHASE_SENSOR : sens_10398 , sens_hispi12l4 , sens_hispi_clock , sens_parallel12 , sensor_channel , sensors393
• CLKFBOUT_USE_FINE_PS : mcntrl393 , mcontr_sequencer , memctrl16 , mmcm_adv , mmcm_phase_cntr , phy_cmd , phy_top
• clkfboutb : mmcm_adv , mmcm_phase_cntr
• clkin : pll_base
• clkin1 : mmcm_adv , mmcm_phase_cntr
• CLKIN1_PERIOD : mmcm_adv
• clkin2 : mmcm_adv , mmcm_phase_cntr
• CLKIN2_PERIOD : mmcm_adv
• CLKIN_PERIOD : axi_hp_clk , dual_clock_source , mcntrl393 , mcontr_sequencer , memctrl16 , mmcm_phase_cntr , phy_cmd , phy_top , pll_base , simul_clk
• CLKIN_PERIOD_AXIHP : clocks393
• CLKIN_PERIOD_PCLK : clocks393 , clocks393m
• CLKIN_PERIOD_SENSOR : sens_10398 , sens_hispi12l4 , sens_hispi_clock , sens_parallel12 , sensor_channel , sensors393
• CLKIN_PERIOD_SYNC : clocks393
• CLKIN_PERIOD_XCLK : clocks393
• clkin_pxd_stopped_mmcm : sens_10398 , sens_hispi12l4 , sens_hispi_clock , sens_parallel12
• clkin_stopped : mmcm_phase_cntr
• clkin_stopped_mmcm : phy_top
• clkinsel : mmcm_adv
• clkout0 : mmcm_adv , mmcm_phase_cntr , pll_base
• CLKOUT0_DIVIDE : pll_base
• CLKOUT0_DIVIDE_F : mmcm_adv , mmcm_phase_cntr
• CLKOUT0_DUTY_CYCLE : mmcm_adv , mmcm_phase_cntr , pll_base
• CLKOUT0_PHASE : mmcm_adv , mmcm_phase_cntr , pll_base
• CLKOUT0_USE_FINE_PS : mmcm_adv , mmcm_phase_cntr
• clkout0b : mmcm_adv , mmcm_phase_cntr
• clkout1 : mmcm_adv , mmcm_phase_cntr , pll_base
• CLKOUT1_DIVIDE : mmcm_adv , mmcm_phase_cntr , pll_base
• CLKOUT1_DUTY_CYCLE : mmcm_adv , mmcm_phase_cntr , pll_base
• CLKOUT1_PHASE : mmcm_adv , mmcm_phase_cntr , pll_base
• CLKOUT1_USE_FINE_PS : mmcm_adv , mmcm_phase_cntr
• clkout1b : mmcm_adv , mmcm_phase_cntr
• clkout2 : mmcm_adv , mmcm_phase_cntr , pll_base
• CLKOUT2_DIVIDE : mmcm_adv , mmcm_phase_cntr , pll_base
• CLKOUT2_DUTY_CYCLE : mmcm_adv , mmcm_phase_cntr , pll_base
• CLKOUT2_PHASE : mmcm_adv , mmcm_phase_cntr , pll_base
• CLKOUT2_USE_FINE_PS : mmcm_adv , mmcm_phase_cntr
• clkout2b : mmcm_adv , mmcm_phase_cntr
• clkout3 : mmcm_adv , mmcm_phase_cntr , pll_base
• CLKOUT3_DIVIDE : mmcm_adv , mmcm_phase_cntr , pll_base
• CLKOUT3_DUTY_CYCLE : mmcm_adv , mmcm_phase_cntr , pll_base
• CLKOUT3_PHASE : mmcm_adv , mmcm_phase_cntr , pll_base
• CLKOUT3_USE_FINE_PS : mmcm_adv , mmcm_phase_cntr
• clkout3b : mmcm_adv , mmcm_phase_cntr
• clkout4 : mmcm_adv , mmcm_phase_cntr , pll_base
• CLKOUT4_CASCADE : mmcm_adv , mmcm_phase_cntr
• CLKOUT4_DIVIDE : mmcm_adv , mmcm_phase_cntr , pll_base
• CLKOUT4_DUTY_CYCLE : mmcm_adv , mmcm_phase_cntr , pll_base
• CLKOUT4_PHASE : mmcm_adv , mmcm_phase_cntr , pll_base
• CLKOUT4_USE_FINE_PS : mmcm_adv , mmcm_phase_cntr
• clkout5 : mmcm_adv , mmcm_phase_cntr , pll_base
• CLKOUT5_DIVIDE : mmcm_adv , mmcm_phase_cntr , pll_base
• CLKOUT5_DUTY_CYCLE : mmcm_adv , mmcm_phase_cntr , pll_base
• CLKOUT5_PHASE : mmcm_adv , mmcm_phase_cntr , pll_base
• CLKOUT5_USE_FINE_PS : mmcm_adv , mmcm_phase_cntr
• clkout6 : mmcm_adv , mmcm_phase_cntr
• CLKOUT6_DIVIDE : mmcm_adv , mmcm_phase_cntr
• CLKOUT6_DUTY_CYCLE : mmcm_adv , mmcm_phase_cntr
• CLKOUT6_PHASE : mmcm_adv , mmcm_phase_cntr
• CLKOUT6_USE_FINE_PS : mmcm_adv , mmcm_phase_cntr
• CLKOUT_DIV_AXIHP : clocks393
• CLKOUT_DIV_CLK1X : dual_clock_source
• CLKOUT_DIV_CLK2X : dual_clock_source
• CLKOUT_DIV_PCLK : clocks393 , clocks393m
• CLKOUT_DIV_SYNC : clocks393
• CLKOUT_DIV_XCLK : clocks393
• CLKRSVD : gtxe2_channel_wrapper , GTXE2_GPL
• CLKSWING_CFG : sata_phy , sata_phy_dev
• clksync : focus_sharp393
• CLOCK_DIV : par12_hispi_psp4l
• clock_divider : gtxe2_chnl_clocking
• CLOCK_DIVIDER_V : gtxe2_chnl_cpll
• CLOCK_MPY : par12_hispi_psp4l
• clocks393m : x393
• clogb2() : gtxe2_chnl_rx_align , status_generate_extra
• clp_p : sens_hispi_clock
• clr : select_clk_buf
• clr_align : link
• clr_aligned : gtx_wrap
• clr_burst : gtxe2_chnl_rx_oob , gtxe2_chnl_tx_oob
• clr_error : oob
• clr_idle : gtxe2_chnl_rx_oob
• clr_nocomm : link
• clr_nocommerr : link
• clr_quiet : gtxe2_chnl_tx_oob
• clr_rcvr_badend : link
• clr_rcvr_data : link
• clr_rcvr_eof : link
• clr_rcvr_goodcrc : link
• clr_rcvr_goodend : link
• clr_rcvr_rdy : link
• clr_rcvr_rhold : link
• clr_rcvr_shold : link
• clr_rcvr_wait : link
• clr_recal_tx : oob
• clr_reset : link
• clr_rmv1_req : gtx_elastic
• clr_rmv2_req : gtx_elastic
• clr_send_ack : gtx_elastic
• clr_send_crc : link
• clr_send_data : link
• clr_send_eof : link
• clr_send_rdy : link
• clr_send_rhold : link
• clr_send_shold : link
• clr_send_sof : link
• clr_skip1_align : gtx_elastic
• clr_skip2_align : gtx_elastic
• clr_sync_esc : link
• clr_triggered : gtx_wrap
• clr_wait : link
• clr_wait1_align : gtx_elastic
• clr_wait2_align : gtx_elastic
• clr_wait_ack : gtx_elastic
• clr_wait_align : oob
• clr_wait_align2 : oob
• clr_wait_clk_align : oob
• clr_wait_cominit : oob
• clr_wait_comwake : oob
• clr_wait_eidle : oob
• clr_wait_linkup : oob
• clr_wait_next_p : gtx_elastic
• clr_wait_rxrst : oob
• clr_wait_synp : oob
• cmd : debug_master , debug_slave , x393Client , X393_cocotb_server
• cmd0_addr : mcontr_sequencer , memctrl16
• cmd0_clk : mcontr_sequencer , memctrl16
• cmd0_data : mcontr_sequencer , memctrl16
• cmd0_we : mcontr_sequencer , memctrl16
• cmd1_addr : mcontr_sequencer
• cmd1_clk : mcontr_sequencer
• cmd1_data : mcontr_sequencer
• cmd1_we : mcontr_sequencer
• cmd_a : camsync393 , clocks393 , clocks393m , cmd_frame_sequencer , cmprs_afi_mux , cmprs_afi_mux_status , debug_master , event_logger , gpio393 , jp_channel , lens_flat393 , mcntrl393_test01 , mcntrl_linear_rw , mcntrl_ps_pio , mcntrl_tiled_rw , membridge , mult_saxi_wr , rtc393 , sens_10398 , sens_gamma , sens_parallel12 , sens_sync
• cmd_a_r : sens_sync
• cmd_abort : ahci_dma
• cmd_abort_hclk : ahci_dma
• CMD_ACTIVATE : cmd_encod_linear_rd , cmd_encod_linear_wr , cmd_encod_tiled_32_rd , cmd_encod_tiled_32_wr , cmd_encod_tiled_rd , cmd_encod_tiled_wr
• cmd_ad : camsync393 , clocks393 , clocks393m , cmd_frame_sequencer , cmd_seq_mux , cmprs_afi_mux , compressor393 , debug_master , event_logger , gpio393 , histogram_saxi , jp_channel , lens_flat393 , mcntrl393 , mcntrl393_test01 , mcntrl_linear_rw , mcntrl_ps_pio , mcntrl_tiled_rw , mcontr_sequencer , membridge , memctrl16 , mult_saxi_wr , rtc393 , sens_10398 , sens_gamma , sens_histogram , sens_histogram_snglclk , sens_parallel12 , sens_sync , sensor_channel , sensor_i2c , sensor_i2c_io , sensors393 , timing393
• cmd_ad_in : sensor_channel , sensors393
• cmd_addr : mcontr_sequencer , phy_top
• cmd_addr_cur : memctrl16
• cmd_addr_start : memctrl16
• cmd_busy : ahci_dma , mcontr_sequencer
• cmd_clocks_ad : x393
• cmd_clocks_stb : x393
• cmd_cmprs_ad : mcntrl393
• cmd_cmprs_stb : mcntrl393
• cmd_compressor_ad : x393
• cmd_compressor_stb : x393
• cmd_data : camsync393 , clocks393 , clocks393m , cmd_frame_sequencer , cmd_seq_mux , cmprs_afi_mux , cmprs_afi_mux_status , debug_master , event_logger , gpio393 , histogram_saxi , jp_channel , lens_flat393 , mcntrl393_test01 , mcntrl_linear_rw , mcntrl_ps_pio , mcntrl_tiled_rw , membridge , mult_saxi_wr , rtc393 , sens_10398 , sens_gamma , sens_parallel12 , sens_sync
• cmd_data_r : event_logger , lens_flat393 , sens_sync
• cmd_debug_ad : x393
• cmd_debug_stb : x393
• cmd_deser : camsync393 , clocks393 , clocks393m , cmd_frame_sequencer , cmd_seq_mux , cmprs_afi_mux , debug_master , event_logger , gpio393 , histogram_saxi , jp_channel , lens_flat393 , mcntrl393_test01 , mcntrl_linear_rw , mcntrl_ps_pio , mcntrl_tiled_rw , mcontr_sequencer , membridge , memctrl16 , mult_saxi_wr , rtc393 , sens_10398 , sens_gamma , sens_histogram , sens_histogram_snglclk , sens_parallel12 , sens_sync , sensor_channel , sensor_i2c
• cmd_deser_dual : cmd_deser
• cmd_deser_multi : cmd_deser
• cmd_deser_single : cmd_deser
• cmd_done : ahci_dma
• CMD_DONE_BIT : cmd_encod_linear_rd , cmd_encod_linear_rw , cmd_encod_linear_wr , cmd_encod_tiled_32_rd , cmd_encod_tiled_32_rw , cmd_encod_tiled_32_wr , cmd_encod_tiled_rd , cmd_encod_tiled_rw , cmd_encod_tiled_wr , mcntrl393 , mcontr_sequencer , memctrl16 , phy_cmd
• cmd_done_hclk : ahci_dma
• cmd_encod_4mux : mcntrl393
• cmd_encod_linear_mux : mcntrl393
• cmd_encod_linear_rd : cmd_encod_linear_rw
• cmd_encod_linear_rw : mcntrl393
• cmd_encod_linear_wr : cmd_encod_linear_rw
• cmd_encod_tiled_32_rd : cmd_encod_tiled_32_rw
• cmd_encod_tiled_32_rw : mcntrl393
• cmd_encod_tiled_32_wr : cmd_encod_tiled_32_rw
• cmd_encod_tiled_mux : mcntrl393
• cmd_encod_tiled_rd : cmd_encod_tiled_rw
• cmd_encod_tiled_rw : mcntrl393
• cmd_encod_tiled_wr : cmd_encod_tiled_rw
• cmd_extra_pages : mcntrl_linear_rw , mcntrl_tiled_rw
• cmd_fetch : mcontr_sequencer
• CMD_FIFO_DEPTH : mcntrl_ps_pio
• cmd_frame_sequencer : x393
• cmd_frame_start_w : mcntrl393_test01
• cmd_gpio_ad : x393
• cmd_gpio_stb : x393
• cmd_half_full : mcntrl_ps_pio
• cmd_logger_ad : x393
• cmd_logger_stb : x393
• cmd_mcontr_ad : mcntrl393 , x393
• cmd_mcontr_stb : mcntrl393 , x393
• cmd_membridge_ad : x393
• cmd_membridge_stb : x393
• cmd_mux : x393
• cmd_need : mcntrl_ps_pio
• cmd_nempty : mcntrl_ps_pio
• cmd_next_page_w : mcntrl393_test01
• CMD_NOP : cmd_encod_linear_rd , cmd_encod_linear_wr , cmd_encod_tiled_32_rd , cmd_encod_tiled_32_wr , cmd_encod_tiled_rd , cmd_encod_tiled_wr
• cmd_out : mcntrl_ps_pio
• cmd_page : mcntrl_ps_pio
• CMD_PAUSE_BITS : cmd_encod_linear_rd , cmd_encod_linear_rw , cmd_encod_linear_wr , cmd_encod_tiled_32_rd , cmd_encod_tiled_32_rw , cmd_encod_tiled_32_wr , cmd_encod_tiled_rd , cmd_encod_tiled_rw , cmd_encod_tiled_wr , mcntrl393 , mcontr_sequencer , memctrl16 , phy_cmd
• cmd_pend : status_generate_extra , status_generate_only
• CMD_PRECHARGE : cmd_encod_linear_rd , cmd_encod_linear_wr
• cmd_ps_pio_ad : mcntrl393
• cmd_ps_pio_stb : mcntrl393
• CMD_READ : cmd_encod_linear_rd , cmd_encod_tiled_32_rd , cmd_encod_tiled_rd
• cmd_readback : x393
• cmd_reg : debug_master , debug_slave
• cmd_reg_dly : debug_master , debug_slave
• cmd_root_ad : x393
• cmd_root_stb : x393
• cmd_saxi1wr_ad : x393
• cmd_saxi1wr_stb : x393
• cmd_scanline_chn1_ad : mcntrl393
• cmd_scanline_chn1_stb : mcntrl393
• cmd_scanline_chn3_ad : mcntrl393
• cmd_scanline_chn3_stb : mcntrl393
• cmd_sel : mcontr_sequencer
• cmd_sens_ad : mcntrl393
• cmd_sens_stb : mcntrl393
• cmd_sensor_ad : x393
• cmd_sensor_stb : x393
• cmd_seq_a : mcntrl_ps_pio
• cmd_seq_addr : memctrl16
• cmd_seq_chn : memctrl16
• cmd_seq_fill : memctrl16
• cmd_seq_full : memctrl16
• cmd_seq_mux : x393
• cmd_seq_need : memctrl16
• cmd_seq_refresh : memctrl16
• cmd_seq_run : memctrl16
• cmd_seq_set : memctrl16
• cmd_sequencer_ad : x393
• cmd_sequencer_stb : x393
• cmd_set : mcntrl_ps_pio
• cmd_set_d : mcntrl_ps_pio
• cmd_start : ahci_dma
• cmd_start_hclk : ahci_dma
• cmd_status : cmd_seq_mux , event_logger
• cmd_stb : camsync393 , clocks393 , clocks393m , cmd_frame_sequencer , cmd_seq_mux , cmprs_afi_mux , compressor393 , debug_master , event_logger , gpio393 , histogram_saxi , jp_channel , lens_flat393 , mcntrl393 , mcntrl393_test01 , mcntrl_linear_rw , mcntrl_ps_pio , mcntrl_tiled_rw , mcontr_sequencer , membridge , memctrl16 , mult_saxi_wr , rtc393 , sens_10398 , sens_gamma , sens_histogram , sens_histogram_snglclk , sens_parallel12 , sens_sync , sensor_channel , sensor_i2c , sensor_i2c_io , sensors393 , timing393
• cmd_stb_in : sensor_channel , sensors393
• cmd_suspend_w : mcntrl393_test01
• cmd_test01_ad : x393
• cmd_test01_stb : x393
• cmd_tiled_chn2_ad : mcntrl393
• cmd_tiled_chn2_stb : mcntrl393
• cmd_tiled_chn4_ad : mcntrl393
• cmd_tiled_chn4_stb : mcntrl393
• cmd_timing_ad : x393
• cmd_timing_stb : x393
• cmd_wa : histogram_saxi
• cmd_wait : mcntrl_ps_pio
• cmd_wait_r : mcntrl_ps_pio
• cmd_we : camsync393 , clocks393 , clocks393m , cmd_frame_sequencer , cmprs_afi_mux , debug_master , event_logger , gpio393 , jp_channel , lens_flat393 , mcntrl393 , mcntrl393_test01 , mcntrl_linear_rw , mcntrl_ps_pio , mcntrl_tiled_rw , membridge , rtc393 , sens_10398 , sens_gamma , sens_parallel12 , sens_sync
• cmd_we_abs_r : cmd_frame_sequencer
• cmd_we_abs_w : cmd_frame_sequencer
• cmd_we_any_r : cmd_frame_sequencer
• cmd_we_ctl_r : cmd_frame_sequencer
• cmd_we_ctl_w : cmd_frame_sequencer
• cmd_we_en_w : cmprs_afi_mux
• cmd_we_mode_w : cmprs_afi_mux
• cmd_we_r : cmd_frame_sequencer
• cmd_we_rel_r : cmd_frame_sequencer
• cmd_we_rel_w : cmd_frame_sequencer
• cmd_we_rst_w : cmprs_afi_mux
• cmd_we_sa_len : mult_saxi_wr
• cmd_we_sa_len_w : cmprs_afi_mux
• cmd_we_status_w : cmprs_afi_mux
• CMD_WIDTH : mcntrl_ps_pio
• cmd_wr : mcntrl_ps_pio
• cmd_wr_chn : memctrl16
• cmd_wr_out : mcntrl_ps_pio
• CMD_WRITE : cmd_encod_linear_wr , cmd_encod_tiled_32_wr , cmd_encod_tiled_wr
• cmd_wrmem : mcntrl_linear_rw , mcntrl_tiled_rw , membridge
• cmd_wrmem_chn1 : mcntrl393 , x393
• CMDA_DELAY : ddr3_wrap
• CMDA_DELAY_H : ddr3_wrap
• CMDA_DELAY_HSDA_D : ddr3_wrap
• CMDA_DELAY_HSDA_H1 : ddr3_wrap
• CMDA_DELAY_HSDA_H2 : ddr3_wrap
• CMDA_DELAY_HSDA_H3 : ddr3_wrap
• CMDA_DELAY_HSDBA_D : ddr3_wrap
• CMDA_DELAY_HSDBA_H1 : ddr3_wrap
• CMDA_DELAY_HSDBA_H2 : ddr3_wrap
• CMDA_DELAY_HSDBA_H3 : ddr3_wrap
• CMDA_DELAY_HSDCAS_D : ddr3_wrap
• CMDA_DELAY_HSDCAS_H1 : ddr3_wrap
• CMDA_DELAY_HSDCAS_H2 : ddr3_wrap
• CMDA_DELAY_HSDCAS_H3 : ddr3_wrap
• CMDA_DELAY_HSDCKE_D : ddr3_wrap
• CMDA_DELAY_HSDCKE_H1 : ddr3_wrap
• CMDA_DELAY_HSDCKE_H2 : ddr3_wrap
• CMDA_DELAY_HSDCKE_H3 : ddr3_wrap
• CMDA_DELAY_HSDODT_D : ddr3_wrap
• CMDA_DELAY_HSDODT_H1 : ddr3_wrap
• CMDA_DELAY_HSDODT_H2 : ddr3_wrap
• CMDA_DELAY_HSDODT_H3 : ddr3_wrap
• CMDA_DELAY_HSDRAS_D : ddr3_wrap
• CMDA_DELAY_HSDRAS_H1 : ddr3_wrap
• CMDA_DELAY_HSDRAS_H2 : ddr3_wrap
• CMDA_DELAY_HSDRAS_H3 : ddr3_wrap
• CMDA_DELAY_HSDRST_D : ddr3_wrap
• CMDA_DELAY_HSDRST_H1 : ddr3_wrap
• CMDA_DELAY_HSDRST_H2 : ddr3_wrap
• CMDA_DELAY_HSDRST_H3 : ddr3_wrap
• CMDA_DELAY_HSDWE_D : ddr3_wrap
• CMDA_DELAY_HSDWE_H1 : ddr3_wrap
• CMDA_DELAY_HSDWE_H2 : ddr3_wrap
• CMDA_DELAY_HSDWE_H3 : ddr3_wrap
• cmda_en : mcontr_sequencer , phy_cmd
• cmda_single : cmd_addr
• cmda_tri : phy_cmd
• CMDFRAMESEQ_ABS : cmd_frame_sequencer
• CMDFRAMESEQ_ADDR : cmd_frame_sequencer
• CMDFRAMESEQ_CTRL : cmd_frame_sequencer
• CMDFRAMESEQ_DEPTH : cmd_frame_sequencer
• CMDFRAMESEQ_IRQ_BIT : cmd_frame_sequencer
• CMDFRAMESEQ_MASK : cmd_frame_sequencer
• CMDFRAMESEQ_REL : cmd_frame_sequencer
• CMDFRAMESEQ_RST_BIT : cmd_frame_sequencer
• CMDFRAMESEQ_RUN_BIT : cmd_frame_sequencer
• cmdseq_di : cmd_frame_sequencer
• cmdseq_do : cmd_frame_sequencer
• cmdseq_full_r : cmd_mux
• CMDSEQMUX_ADDR : cmd_seq_mux
• CMDSEQMUX_MASK : cmd_seq_mux
• CMDSEQMUX_STATUS : cmd_seq_mux
• CMPRS_ADDR : jp_channel
• cmprs_afi_mux : compressor393
• cmprs_afi_mux_ptr : cmprs_afi_mux
• cmprs_afi_mux_ptr_wresp : cmprs_afi_mux
• cmprs_afi_mux_status : cmprs_afi_mux
• CMPRS_AFIMUX_ADDR : cmprs_afi_mux
• CMPRS_AFIMUX_CYCBITS : cmprs_afi_mux , cmprs_afi_mux_status , compressor393
• CMPRS_AFIMUX_EN : cmprs_afi_mux , compressor393
• CMPRS_AFIMUX_MASK : cmprs_afi_mux , compressor393
• CMPRS_AFIMUX_MODE : cmprs_afi_mux , compressor393
• CMPRS_AFIMUX_RADDR0 : compressor393
• CMPRS_AFIMUX_RADDR1 : compressor393
• CMPRS_AFIMUX_REG_ADDR0 : compressor393
• CMPRS_AFIMUX_REG_ADDR1 : compressor393
• CMPRS_AFIMUX_RST : cmprs_afi_mux , compressor393
• CMPRS_AFIMUX_SA_LEN : cmprs_afi_mux , compressor393
• CMPRS_AFIMUX_STATUS_CNTRL : cmprs_afi_mux , compressor393
• CMPRS_AFIMUX_STATUS_REG_ADDR : cmprs_afi_mux , cmprs_afi_mux_status
• CMPRS_AFIMUX_WIDTH : cmprs_afi_mux , cmprs_afi_mux_status , compressor393
• cmprs_bank : mcntrl393
• CMPRS_BASE_INC : compressor393 , jp_channel
• cmprs_buf_average : jp_channel
• cmprs_buf_din : mcntrl393 , x393
• CMPRS_BUF_EXTRA_LATENCY : cmprs_pixel_buf_iface
• cmprs_buf_we : mcntrl393 , x393
• cmprs_buf_wpage_nxt : mcntrl393 , x393
• CMPRS_CBIT_BAYER : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CBIT_BAYER_BITS : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CBIT_CMODE : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CBIT_CMODE_BITS : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CBIT_CMODE_JP4 : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CBIT_CMODE_JP46 : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CBIT_CMODE_JP46DC : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CBIT_CMODE_JP4DC : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CBIT_CMODE_JP4DIFF : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CBIT_CMODE_JP4DIFFDIV2 : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CBIT_CMODE_JP4DIFFHDR : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CBIT_CMODE_JPEG18 : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CBIT_CMODE_JPEG20 : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CBIT_CMODE_MONO1 : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CBIT_CMODE_MONO4 : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CBIT_CMODE_MONO6 : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CBIT_DCSUB : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CBIT_DCSUB_BITS : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CBIT_FOCUS : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CBIT_FOCUS_BITS : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CBIT_FRAMES : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CBIT_FRAMES_BITS : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CBIT_FRAMES_SINGLE : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CBIT_QBANK : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CBIT_QBANK_BITS : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CBIT_RUN : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CBIT_RUN_BITS : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CBIT_RUN_ENABLE : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CBIT_RUN_RST : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CBIT_RUN_STANDALONE : cmprs_cmd_decode , compressor393 , jp_channel
• cmprs_channel_pgm_en : mcntrl393
• cmprs_cmd_decode : jp_channel
• cmprs_col : mcntrl393
• CMPRS_COLOR18 : cmprs_buf_average , cmprs_cmd_decode , cmprs_pixel_buf_iface , cmprs_tile_mode2_decode , cmprs_tile_mode_decode , compressor393 , csconvert , jp_channel
• CMPRS_COLOR20 : cmprs_buf_average , cmprs_cmd_decode , cmprs_pixel_buf_iface , cmprs_tile_mode2_decode , cmprs_tile_mode_decode , compressor393 , csconvert , jp_channel
• CMPRS_COLOR_SATURATION : compressor393 , jp_channel
• CMPRS_CONTROL_REG : compressor393 , jp_channel
• CMPRS_CORING_BITS : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CORING_MODE : compressor393 , jp_channel
• CMPRS_CSAT_CB : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CSAT_CB_BITS : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CSAT_CR : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_CSAT_CR_BITS : cmprs_cmd_decode , compressor393 , jp_channel
• cmprs_dcsub : cmprs_cmd_decode
• cmprs_dcsub_mclk : cmprs_cmd_decode
• cmprs_dcsub_xclk : cmprs_cmd_decode
• cmprs_en : cmprs_frame_sync
• cmprs_en_d : cmprs_frame_sync
• cmprs_en_extend : cmprs_cmd_decode , cmprs_frame_sync , jp_channel
• cmprs_en_extend_r : cmprs_frame_sync
• cmprs_en_late_xclk : cmprs_cmd_decode
• cmprs_en_mclk : cmprs_cmd_decode , jp_channel
• cmprs_en_mclk_r : cmprs_cmd_decode
• cmprs_en_xclk : cmprs_cmd_decode
• cmprs_first_rd_in_frame : mcntrl393
• cmprs_first_rd_pending_r : mcntrl393
• cmprs_fmode : cmprs_cmd_decode , jp_channel
• cmprs_fmode_mclk : cmprs_cmd_decode
• cmprs_fmode_xclk : cmprs_cmd_decode
• CMPRS_FORMAT : compressor393 , jp_channel
• cmprs_frame_done_dst : mcntrl393 , x393
• cmprs_frame_done_src : mcntrl393 , x393
• cmprs_frame_number_dst : mcntrl393 , x393
• cmprs_frame_number_finished : x393
• cmprs_frame_number_src : mcntrl393 , x393
• cmprs_frame_start_dst : mcntrl393 , x393
• cmprs_frame_sync : jp_channel
• CMPRS_FRMT_LMARG : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_FRMT_LMARG_BITS : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_FRMT_MBCM1 : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_FRMT_MBCM1_BITS : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_FRMT_MBRM1 : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_FRMT_MBRM1_BITS : cmprs_cmd_decode , compressor393 , jp_channel
• CMPRS_GROUP_ADDR : compressor393 , jp_channel
• CMPRS_HIFREQ_REG_ADDR : jp_channel
• CMPRS_HIFREQ_REG_BASE : compressor393 , jp_channel
• CMPRS_HIFREQ_REG_INC : compressor393 , jp_channel
• CMPRS_INTERRUPTS : compressor393 , jp_channel
• cmprs_irq : compressor393 , x393
• CMPRS_JP4 : cmprs_buf_average , cmprs_cmd_decode , cmprs_pixel_buf_iface , cmprs_tile_mode2_decode , cmprs_tile_mode_decode , compressor393 , csconvert , jp_channel
• CMPRS_JP4DIFF : cmprs_buf_average , cmprs_cmd_decode , cmprs_pixel_buf_iface , cmprs_tile_mode2_decode , cmprs_tile_mode_decode , compressor393 , csconvert , jp_channel
• cmprs_keep_open : mcntrl393
• cmprs_line_unfinished_dst : mcntrl393 , x393
• cmprs_line_unfinished_src : mcntrl393 , x393
• cmprs_macroblock_buf_iface : jp_channel
• CMPRS_MASK : compressor393 , jp_channel
• cmprs_mode_mclk : cmprs_cmd_decode
• cmprs_mode_xclk : cmprs_cmd_decode
• CMPRS_MONO16 : cmprs_buf_average , cmprs_cmd_decode , cmprs_pixel_buf_iface , cmprs_tile_mode2_decode , cmprs_tile_mode_decode , compressor393 , csconvert , jp_channel
• CMPRS_MONO8 : cmprs_buf_average , cmprs_cmd_decode , cmprs_pixel_buf_iface , cmprs_tile_mode2_decode , cmprs_tile_mode_decode , compressor393 , csconvert , jp_channel
• cmprs_need : mcntrl393
• cmprs_next_page : mcntrl393 , x393
• CMPRS_NUM_AFI_CHN : compressor393
• cmprs_num_cols_m1 : mcntrl393
• cmprs_num_rows_m1 : mcntrl393
• CMPRS_NUMBER : jp_channel
• cmprs_out_fifo32 : jp_channel
• cmprs_page_ready : mcntrl393 , x393
• cmprs_partial : mcntrl393
• cmprs_pixel_buf_iface : jp_channel
• CMPRS_PREEND_EARLY : cmprs_pixel_buf_iface
• cmprs_qpage : cmprs_cmd_decode , jp_channel
• cmprs_qpage_mclk : cmprs_cmd_decode
• cmprs_qpage_xclk : cmprs_cmd_decode
• cmprs_reject : mcntrl393
• CMPRS_RELEASE_EARLY : cmprs_pixel_buf_iface
• cmprs_row : mcntrl393
• cmprs_rowcol_inc : mcntrl393
• cmprs_run : cmprs_frame_sync
• cmprs_run_mclk : cmprs_cmd_decode , jp_channel
• cmprs_seq_done : mcntrl393
• cmprs_standalone : cmprs_cmd_decode , cmprs_frame_sync , jp_channel
• cmprs_start_rd16 : mcntrl393
• cmprs_start_rd32 : mcntrl393
• cmprs_status : jp_channel
• CMPRS_STATUS_CNTRL : compressor393 , jp_channel
• CMPRS_STATUS_REG_ADDR : jp_channel
• CMPRS_STATUS_REG_BASE : compressor393 , jp_channel
• CMPRS_STATUS_REG_INC : compressor393 , jp_channel
• cmprs_suspend : mcntrl393 , x393
• CMPRS_TABLES : compressor393 , jp_channel
• cmprs_tile_mode2_decode : cmprs_buf_average
• cmprs_tile_mode_decode : jp_channel
• CMPRS_TIMEOUT : cmprs_frame_sync , compressor393 , jp_channel
• CMPRS_TIMEOUT_BITS : cmprs_frame_sync , compressor393 , jp_channel
• cmprs_want : mcntrl393
• cmprs_xfer_reset_page_rd : mcntrl393 , x393
• cnt : clock_divider
• cnt_rd : resync_fifo_nonsynt
• cnt_wr : resync_fifo_nonsynt
• cntr : cmprs_afi_mux_status , debug_master , encoderDCAC393 , imu_timestamps393 , sim_clk_div , simul_sensor12bits , timestamp_snapshot , timestamp_to_serial
• cntr_in : dct1d_chen_reorder_in , dct1d_chen_reorder_out , dct2d8x8_chen
• cntr_w : timestamp_to_serial
• cntrd : simul_sensor12bits
• cnxt : csconvert18a
• CODE_ALIGNP : link
• CODE_CONTP : link
• CODE_CRC : link
• CODE_DATA : link
• CODE_DMATP : link
• CODE_EOFP : link
• CODE_ERRP : link
• CODE_HOLDAP : link
• CODE_HOLDP : link
• CODE_IPP : link
• CODE_OKP : link
• CODE_RRDYP : link
• CODE_SOFP : link
• CODE_SYNCP : link
• code_typ0 : huffman393
• code_typ1 : huffman393
• code_typ2 : huffman393
• code_typ3 : huffman393
• code_typ4 : huffman393
• CODE_WTRMP : link
• CODE_XRDYP : link
• codel : varlen_encode393 , varlen_encode_snglclk
• codel0 : varlen_encode393 , varlen_encode_snglclk
• codel1 : varlen_encode393 , varlen_encode_snglclk
• codel2 : varlen_encode393 , varlen_encode_snglclk
• col : cmd_encod_linear_rd , cmd_encod_linear_wr , cmd_encod_tiled_32_rd , cmd_encod_tiled_32_wr , cmd_encod_tiled_mux , cmd_encod_tiled_rd , cmd_encod_tiled_wr , simul_sensor12bits
• col12 : cmd_encod_tiled_mux
• col13 : cmd_encod_tiled_mux
• col14 : cmd_encod_tiled_mux
• col15 : cmd_encod_tiled_mux
• col2 : cmd_encod_tiled_mux
• col4 : cmd_encod_tiled_mux
• col_bank : cmd_encod_tiled_32_rd , cmd_encod_tiled_32_wr , cmd_encod_tiled_rd , cmd_encod_tiled_wr
• col_inc : cmprs_pixel_buf_iface
• col_index : simul_sensor12bits
• col_r : cmd_encod_tiled_mux
• col_w : cmd_encod_tiled_mux
• COL_WDTH : mcntrl393
• COLADDR_NUMBER : cmd_encod_linear_mux , cmd_encod_linear_rd , cmd_encod_linear_rw , cmd_encod_linear_wr , cmd_encod_tiled_32_rd , cmd_encod_tiled_32_rw , cmd_encod_tiled_32_wr , cmd_encod_tiled_mux , cmd_encod_tiled_rd , cmd_encod_tiled_rw , cmd_encod_tiled_wr , mcntrl393 , mcntrl_linear_rw , mcntrl_tiled_rw
• cold : simul_sensor12bits
• color : lens_flat393 , sens_gamma
• color_enable : cmprs_buf_average , cmprs_tile_mode2_decode
• color_enable_d : cmprs_buf_average
• color_first : bit_stuffer_metadata , huffman_stuffer_meta , jp_channel , quantizer393 , stuffer393
• color_first_r : bit_stuffer_metadata , stuffer393
• color_last : jp_channel
• color_sat_cb : cmprs_cmd_decode
• color_sat_cr : cmprs_cmd_decode
• color_sat_mclk : cmprs_cmd_decode
• color_sat_we : cmprs_cmd_decode
• color_sat_we_r : cmprs_cmd_decode
• color_sat_we_xclk : cmprs_cmd_decode
• color_sat_xclk : cmprs_cmd_decode
• color_tn : jp_channel
• cols_left : cmprs_pixel_buf_iface
• column_width_or : cmprs_pixel_buf_iface
• column_x : cmprs_pixel_buf_iface
• comb_out : iserdes_mem
• comb_rst : x393
• combined_qf : focus_sharp393
• cominit_allow : oob , oob_ctrl
• COMINIT_DONE_TIME : oob
• cominit_got : ahci_fsm , ahci_sata_layers , ahci_top , sata_ahci_top , sata_phy
• cominit_req : oob , oob_ctrl
• cominit_req_l : oob
• cominit_req_r : oob
• cominit_req_set : oob
• comma : datascope_incoming_raw , gtx_comma_align , gtx_wrap
• COMMA_ALIGN_LATENCY : GTXE2_GPL
• comma_detected : gtx_comma_align
• comma_match : gtx_comma_align , gtxe2_chnl_rx_align
• comma_match_p : gtx_comma_align
• comma_match_prev : gtx_comma_align
• comma_n : gtx_comma_align
• comma_p : gtx_comma_align
• comma_pos : gtxe2_chnl_rx_align
• comma_width : gtxe2_chnl_rx_align
• comma_window : gtxe2_chnl_rx_align
• command : SocketCommand
• commands_pending : cmd_frame_sequencer
• communicate() : x393Client
• comp_colori : encoderDCAC393
• comp_coloro : encoderDCAC393
• comp_firsti : encoderDCAC393
• comp_firsto : encoderDCAC393
• comp_lastinmbi : encoderDCAC393
• comp_lastinmbo : encoderDCAC393
• comp_numberi : encoderDCAC393
• comp_numbero : encoderDCAC393
• COMPENSATION : mmcm_adv , mmcm_phase_cntr
• component_color : cmprs_buf_average , jp_channel
• component_colors : cmprs_buf_average , cmprs_tile_mode2_decode
• component_colorsS : cmprs_buf_average
• component_first : cmprs_buf_average , cmprs_tile_mode2_decode , jp_channel
• component_firsts : cmprs_buf_average
• component_firstsS : cmprs_buf_average
• component_lastinmb : cmprs_buf_average , jp_channel
• component_num : cmprs_buf_average , jp_channel
• component_numsH : cmprs_buf_average , cmprs_tile_mode2_decode
• component_numsHS : cmprs_buf_average
• component_numsL : cmprs_buf_average , cmprs_tile_mode2_decode
• component_numsLS : cmprs_buf_average
• component_numsM : cmprs_buf_average , cmprs_tile_mode2_decode
• component_numsMS : cmprs_buf_average
• compressed_frames : frame_num_sync
• compressor393 : x393
• comreset_send : ahci_fsm , ahci_sata_layers , ahci_top , oob_ctrl , sata_ahci_top , sata_phy
• comreset_send0 : ahci_top
• COMWAKE_DONE_TIME : oob
• comwake_got : sata_phy
• cond_met_w : ahci_fsm
• cond_r : condition_mux
• condition : condition_mux
• condition_mux : ahci_fsm
• conditions_ce : ahci_fsm
• conf_send : cmd_frame_sequencer
• config_debug : event_logger , imu_spi393
• config_debug_mclk : event_logger
• config_gps : event_logger
• config_gps_mclk : event_logger
• config_imu : event_logger
• config_imu_mclk : event_logger
• config_late_clk : imu_spi393
• config_long_sda_en : imu_spi393
• config_msg : event_logger
• config_msg_mclk : event_logger
• config_rst : event_logger
• config_rst_mclk : event_logger
• config_single_wire : imu_spi393
• config_syn_mclk : event_logger
• confirm_write : histogram_saxi
• CONT_PRIM : datascope_incoming
• continued_tile : mcntrl_tiled_rw
• continued_xfer : mcntrl_linear_rw
• contral_status_data : mcontr_sequencer
• CONTROL_ADDR : cmd_mux , cmd_readback
• CONTROL_ADDR_MASK : cmd_mux , cmd_readback
• CONTROL_RBACK_ADDR : cmd_readback
• CONTROL_RBACK_ADDR_MASK : cmd_readback
• CONTROL_RBACK_DEPTH : cmd_readback
• control_status_we : mcontr_sequencer
• conv18_caddrw : csconvert
• conv18_cwe : csconvert
• conv18_n000 : csconvert
• conv18_n255 : csconvert
• conv18_pre_first_out : csconvert
• conv18_signed_c : csconvert
• conv18_signed_y : csconvert
• conv18_yaddrw : csconvert
• conv18_ywe : csconvert
• conv20_caddrw : csconvert
• conv20_cwe : csconvert
• conv20_n000 : csconvert
• conv20_n255 : csconvert
• conv20_pre_first_out : csconvert
• conv20_signed_c : csconvert
• conv20_signed_y : csconvert
• conv20_yaddrw : csconvert
• conv20_ywe : csconvert
• converter_type : cmprs_buf_average , cmprs_cmd_decode , cmprs_pixel_buf_iface , cmprs_tile_mode2_decode , cmprs_tile_mode_decode , csconvert , jp_channel
• converter_type_r : cmprs_buf_average , cmprs_tile_mode2_decode , csconvert
• copy_acc_frame : focus_sharp393
• copy_cntr : imu_exttime393
• copy_data : imu_exttime393
• copy_data_r : imu_exttime393
• copy_dc_tdo : quantizer393
• copy_selected : imu_exttime393
• copy_started : imu_exttime393
• coring : cmprs_cmd_decode
• coring.dat.vh : quantizer393
• coring_mclk : cmprs_cmd_decode
• coring_num : jp_channel , quantizer393
• coring_range : quantizer393
• coring_sel : quantizer393
• coring_we : cmprs_cmd_decode
• coring_we_r : cmprs_cmd_decode
• coring_we_xclk : cmprs_cmd_decode
• coring_xclk : cmprs_cmd_decode
• corr : rtc393
• CORR_OFFSET : elastic1632
• correct : elastic1632
• correct_first : elastic1632
• correct_r : elastic1632
• correct_stream : elastic1632
• correct_table_disp : gtx_10x8dec
• COS_1_16 : dct1d_chen
• COS_2_16 : dct1d_chen
• COS_3_16 : dct1d_chen
• COS_4_16 : dct1d_chen
• COS_5_16 : dct1d_chen
• COS_6_16 : dct1d_chen
• COS_7_16 : dct1d_chen
• COSINE_SHIFT : dct1d_chen
• count : simul_fifo
• count32 : cmprs_out_fifo , cmprs_out_fifo32
• counter : freq_meter , gtxe2_chnl_cpll
• counts_corr0 : cmprs_afi_mux
• counts_corr1 : cmprs_afi_mux
• counts_corr2 : cmprs_afi_mux
• CPLL_CFG : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_clocking , gtxe2_chnl_cpll , GTXE2_GPL
• cpll_clk_out : gtxe2_chnl_clocking
• CPLL_FBDIV : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_clocking , gtxe2_chnl_cpll , GTXE2_GPL
• CPLL_FBDIV_45 : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_clocking , gtxe2_chnl_cpll , GTXE2_GPL
• CPLL_INIT_CFG : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_clocking , gtxe2_chnl_cpll , GTXE2_GPL
• CPLL_LOCK_CFG : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_clocking , gtxe2_chnl_cpll , GTXE2_GPL
• CPLL_MUX_CLK_OUT : gtxe2_chnl_cpll_inmux
• CPLL_REFCLK_DIV : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_clocking , gtxe2_chnl_cpll , GTXE2_GPL
• CPLLFBCLKLOST : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_clocking , gtxe2_chnl_cpll , GTXE2_GPL
• CPLLLOCK : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_clocking , gtxe2_chnl_cpll , GTXE2_GPL
• cplllock : sata_phy , sata_phy_dev
• cplllock_debug : sata_phy
• cplllock_r : sata_phy
• CPLLLOCKDETCLK : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_clocking , gtxe2_chnl_cpll , GTXE2_GPL
• cplllockdetclk : sata_phy , sata_phy_dev
• CPLLLOCKEN : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_clocking , gtxe2_chnl_cpll , GTXE2_GPL
• CPLLPD : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_clocking , gtxe2_chnl_cpll , GTXE2_GPL
• CPLLREFCLKLOST : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_clocking , gtxe2_chnl_cpll , GTXE2_GPL
• CPLLREFCLKSEL : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_clocking , gtxe2_chnl_cpll_inmux , GTXE2_GPL
• CPLLRESET : gtxe2_channel_wrapper , gtxe2_chnl , gtxe2_chnl_clocking , gtxe2_chnl_cpll , GTXE2_GPL
• cpllreset : sata_phy , sata_phy_dev
• crc : crc , link
• crc_bad : link
• crc_bit : crc
• crc_dword : link
• crc_good : link
• crc_out : crc
• crst : x393
• cry : ddr_refresh
• cry_ff : bit_stuffer_escape
• cry_ff_w : bit_stuffer_escape
• cs_first_out : cmprs_buf_average
• cs_first_out_late : cmprs_buf_average
• csconvert : jp_channel
• csconvert18a : csconvert
• csconvert_jp4 : csconvert
• csconvert_jp4diff : csconvert
• csconvert_mono : csconvert
• cseq_ackn : cmd_mux , x393
• cseq_waddr : cmd_mux , x393
• cseq_waddr_r : cmd_mux
• cseq_wdata : cmd_mux , x393
• cseq_wdata_r : cmd_mux
• cseq_wr_en : cmd_mux , x393
• cstrt : csconvert18a
• csync : focus_sharp393
• ct_addr : ahci_dma , ahci_fis_transmit
• ct_busy : ahci_dma
• ct_busy_r : ahci_dma
• ct_data : ahci_dma , ahci_fis_transmit
• ct_data_ram : ahci_dma
• ct_data_reg : ahci_dma
• ct_done : ahci_dma
• ct_done_mclk : ahci_dma
• ct_id : ahci_dma
• ct_maddr : ahci_dma
• ct_over_prd_enabled : ahci_dma
• ct_re : ahci_dma , ahci_fis_transmit
• ct_re_r : ahci_fis_transmit
• ct_re_w : ahci_fis_transmit
• ct_stb : ahci_fis_transmit
• ctba : ahci_dma
• CTBA_B : condition_mux
• CTBA_C : condition_mux
• ctba_ld : ahci_dma , ahci_top
• ctba_r : ahci_dma
• CTBAA_CTBAP : condition_mux
• CTBAP : condition_mux
• ctrl_addr : event_logger
• ctrl_we : cmprs_cmd_decode
• ctrl_we_r : cmprs_cmd_decode
• ctrl_we_xclk : cmprs_cmd_decode
• ctype : quantizer393
• ctype_prev : quantizer393
• ctypei : quantizer393
• cur_chn : cmprs_afi_mux
• cur_time : datascope_timing
• curr_x : mcntrl_linear_rw , mcntrl_tiled_rw
• curr_y : mcntrl_linear_rw , mcntrl_tiled_rw
• current_chn_r : status_router2
• current_offset : gtx_elastic
• cut_buf_rd : cmd_encod_linear_wr
• CUT_DUAL_ADDR : cmd_encod_linear_wr
• CUT_SINGLE_ADDR : cmd_encod_linear_wr
• cwe : cmprs_buf_average , csconvert , csconvert18a , jp_channel
• cwe0 : csconvert18a
• cwe_r : csconvert18a
• cwe_r2 : csconvert18a
• cycles : varlen_encode393
• CYCLES_PER_PIXEL : x393_dut