42 //command interface parameters 43 //0x1080..10ff - 8- bit data - to set various delay values 44 parameter DLY_LD =
'h080,
// address to generate delay load 45 parameter DLY_LD_MASK =
'h780,
// address mask to generate delay load 46 // 0x1080..109f - set delay for SDD0-SDD7 47 // 0x10a0..10bf - set delay for SDD8-SDD15 48 // 0x10c0..10df - set delay for SD_CMDA 49 // 0x10e0 - set delay for MMCM 50 //0x1000..103f - 0- bit data (set/reset) 53 // 0x1024..1025 - CMDA_EN // 0 bits - enable/disable command/address outputs 54 // 0x1026..1027 - SDRST_ACT // 0 bits - enable/disable active-low reset signal to DDR3 memory 55 // 0x1028..1029 - CKE_EN // 0 bits - enable/disable CKE signal to memory 56 // 0x102a..102b - DCI_RST // 0 bits - enable/disable CKE signal to memory 57 // 0x102c..102d - DLY_RST // 0 bits - enable/disable CKE signal to memory 66 //0x1040..107f - 16-bit data 67 // 0x1040..104f - RUN_CHN // address to set sequncer channel and run (4 LSB-s - channel) - bits? 68 // parameter RUN_CHN_REL = 'h040, // address to set sequnecer channel and run (4 LSB-s - channel) 69 // parameter RUN_CHN_REL_MASK = 'h7f0, // address mask to generate sequencer channel/run 70 // 0x1050..1057: MCONTR_PHY16 74 parameter MCONTR_PHY_16BIT_PATTERNS_TRI =
'h1,
// 16-bit address to set DQM and DQS tristate on/off patterns {dqs_off,dqs_on, dq_off,dq_on} - 4 bits each 97 parameter CLKFBOUT_MULT =
8,
// Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE 113 output SDRST,
// DDR3 reset (active low) 114 output SDCLK,
// DDR3 clock differential output, positive 115 output SDNCLK,
// DDR3 clock differential output, negative 117 output [
2:
0]
SDBA,
// output bank address ports 121 output SDCKE,
// output Clock Enable port 124 inout [
15:
0]
SDD,
// DQ I/O pads 125 output SDDML,
// LDM I/O pad (actually only output) 128 output SDDMU,
// UDM I/O pad (actually only output) 134 output mclk,
// global clock, half DDR3 clock, synchronizes all I/O through the command port 135 input mrst,
// @posedge mclk, sync reset (should not interrupt mclk!) 137 input ref_clk,
// global clock for idelay_ctrl calibration 139 // command port 0 (filled by software - 32w->32r) - used for mode set, refresh, write levelling, ... 144 // automatic command port1 , filled by the PL, 32w 32r, used for actual page R/W 149 // Controller run interface, posedge mclk 150 input [
10:
0]
run_addr,
// controller sequencer start address (0..11'h3ff - cmd0, 11'h400..11'h7ff - cmd1) 153 input run_seq,
// start controller sequence (will end with !ddr_rst for stable mclk) 155 output run_busy,
// controller sequence in progress 157 // programming interface 158 input [
7:
0]
cmd_ad,
// byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 159 input cmd_stb,
// strobe (with first byte) for the command a/d 160 output [
7:
0]
status_ad,
// status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25] 161 output status_rq,
// input request to send status downstream 162 input status_start,
// Acknowledge of the first status packet byte (address) 164 // Interface to write-to-memory buffers (up to 16) 165 // There will be =1 cycle external latency in address/re and 1 cycle latency in read data (should match sequence programs) 166 // Address data is sync to posedge mclk 170 // output [6:0] ext_buf_raddr, // valid with ext_buf_rd, 2 page MSB to be generated externally 171 output [
3:
0]
ext_buf_rchn,
// ==run_chn_d valid 1 cycle ahead opf ext_buf_rd!, maybe not needed - will be generated externally 173 output ext_buf_rrun,
// run read sequence (to be used with external buffer to set initial address 176 // Interface to memory read channels (up to 16) 177 // Address/data sync to negedge mclk!, any latency OK - just generate DONE appropriately (through the sequencer with delay? 178 // folowing a sync to negedge! 181 // output [6:0] ext_buf_waddr, // valid with ext_buf_wr 182 output [
3:
0]
ext_buf_wchn,
// external buffer channel with timing matching buffer writes 184 output ext_buf_wrun,
// @negedge,first cycle of sequencer run matching write delay 186 // temporary debug data 196 reg cmda_en;
// enable (!tristate) command and address lines // not likely to be used 197 reg ddr_rst=
1;
// generate reset to DDR3 memory (active high) 198 reg dci_rst;
// active high - reset DCI circuitry 199 reg dly_rst;
// active high - delay calibration circuitry 200 reg ddr_cke;
// DDR clock enable , XOR-ed with command bit 225 // wire [PHASE_WIDTH-1:0] ps_out; 238 // wire [35:0] phy_cmd; // input[35:0] 239 wire [
31:
0]
phy_cmd_word;
// selected output from either cmd0 buffer or cmd1 buffer 248 wire [
63:
0]
buf_rdata;
// multiplexed input from one of the write channels buffer 249 wire buf_wr;
// delayed by specified number of clock cycles 251 wire buf_rd;
// read next 64 bits from the buffer, need one extra pre-read 258 wire phy_cmd_add_pause;
// decoded from the command word - add one pause command after the current one 259 reg add_pause;
// previos command had phy_cmd_add_pause set 262 reg cmd_fetch;
// previous cycle command was read from the command memory, current: command valid 263 wire pause;
// do not register new data from the command memory 289 assign run_done=
sequence_done;
// & cmd_busy[2]; // limit done to 1 cycle only even if duration is non-zero - already set in pause_len 293 // assign phy_cmd_word = cmd_sel?phy_cmd1_word:phy_cmd0_word; // TODO: hangs even with 0-s in phy_cmd 297 /// assign phy_cmd_word = phy_cmd_word?0:0; 299 // assign buf_rdata[63:0] = ({64{buf_sel_1hot[1]}} & buf1_rdata[63:0]); // ORed with other read channels terms 301 // External buffers buffer related signals 303 // assign buf_raddr_reset= buf_rst & ~mem_read_mode; // run_seq_d; 307 // assign ext_buf_raddr= buf_raddr; 315 // assign ext_buf_waddr= buf_waddr_negedge; 320 // generation of the control signals from byte-serial channel 321 // generate 8-bit delay data 329 .
rst (
1'b0),
// rst), // input 338 // generate on/off dependent on lsb and 0-bit commands 346 .
rst (
1'b0),
// rst), // input 352 .
data (),
// output[31:0] 374 // generate 16-bit data commands (and set defaults to registers) 381 )
cmd_deser_16bit_i (
382 .
rst (
1'b0),
// rst), // input 435 // assign status_data={dly_ready,dci_ready, locked_mmcm, locked_pll, run_busy,locked,ps_rdy,ps_out[7:0]}; 440 )
status_generate_i (
441 .
rst (
1'b0),
// rst), // input 455 else if (
ddr_rst)
cmd_busy <=
0;
// *************** reset sequencer with DDR reset 462 else if (
pause_cntr!=
0)
pause_cntr <=
pause_cntr-
1;
//SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 10-bit target. 463 // Fetch - command data valid 470 // Command read address 473 else if (
cmd_busy[
0] && !
pause)
cmd_addr <=
cmd_addr +
1;
//SuppressThisWarning ISExst Result of 11-bit expression is truncated to fit in 10-bit target. 474 // command bank select (0 - "manual" (software programmed sequences), 1 - "auto" (normal block r/w) 478 // if (rst) buf_raddr <= 7'h0; 479 // else if (run_seq_d) buf_raddr <= 7'h0; 480 // else if (buf_wr || buf_rd) buf_raddr <= buf_raddr +1; // Separate read/write address? read address re-registered @ negedge //SuppressThisWarning ISExst Result of 10-bit expression is truncated to fit in 9-bit target. 504 // re-register buffer write address to match DDR3 data 506 // buf_waddr_negedge <= buf_raddr; 515 // Command sequence memories: 516 // Command sequence memory 0 ("manual"): 520 .
REGISTERS(
1)
// (0) // register output 524 .
ren (
ren0),
// input TODO: verify cmd_busy[0] is correct (was cmd_busy ). TODO: make cleaner ren/regen 525 // .ren (ren0 && !sequence_done), // input TODO: verify cmd_busy[0] is correct (was cmd_busy ). TODO: make cleaner ren/regen 531 .
web (
4'hf),
// input[3:0] 534 // NOTE: Simulation sometimes may show: 535 // Memory Collision Error on RAMB36E1 : x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.RAMB36E1_i.genblk1.INT_RAMB_TDP.chk_for_col_msg 536 // It is OK, as the sequencer reads 2 extra (unused) locations before it stops at the end of block (stop depends on the read memory that has latency) 539 // Command sequence memory 1 541 .
REGISTERS (
1)
// (0) // register output 545 .
ren (
ren1),
// input ??? TODO: make cleaner ren/regen 546 // .ren ( ren1 && !sequence_done), // input ??? TODO: make cleaner ren/regen 552 .
web (
4'hf),
// input[3:0] 592 .
SDD (
SDD[
15:
0]),
// inout[15:0] 609 // .locked (locked), // output 634 .
buf_rst (
buf_rst),
// reset external buffer address to page start 648 // delay buf_wr by 1-16 cycles to compensate for DDR and HDL code latency (~7 cycles?)
[ 3:0] 6454dq_tri_on_pattern
6329phy_cmd0_wordwire[31:0]
6194MCONTR_PHY_0BIT_DCI_RST'ha
6336buf_wdata_negedgereg[63:0]
6205DFLT_DQM_PATTERN8'h00
6207DFLT_DQ_TRI_OFF_PATTERN4'he
6189MCONTR_PHY_0BIT_ADDR_MASK'h7f0
6208DFLT_DQS_TRI_ON_PATTERN4'h3
6188MCONTR_PHY_0BIT_ADDR'h020
real 6218REFCLK_FREQUENCY300.0
6360run_refresh_w_d_negedgereg
6196MCONTR_PHY_STATUS_REG_ADDR'h0
[ADDRESS_NUMBER-1:0] 6400SDA
6307dq_tri_on_patternreg[3:0]
[ 3:0] 6455dq_tri_off_pattern
6308dq_tri_off_patternreg[3:0]
[ 3:0] 6456dqs_tri_on_pattern
status_generate_i status_generate
6197MCONTR_PHY_16BIT_ADDR'h050
[ADDRESS_NUMBER-1:0] 6238SDA
6202MCONTR_PHY_16BIT_EXTRA'h3
cmd1_buf_i ram_1kx32_1kx32
[ADDR_MASK2!=0?2:ADDR_MASK1!=0?1:0:0] 9935we
6209DFLT_DQS_TRI_OFF_PATTERN4'hc
6330phy_cmd1_wordwire[31:0]
6298phy_0bit_addrwire[3:0]
6206DFLT_DQ_TRI_ON_PATTERN4'h7
[ 3:0] 6457dqs_tri_off_pattern
6219HIGH_PERFORMANCE_MODE"FALSE"
6323status_datawire[14:0]
6199MCONTR_PHY_16BIT_PATTERNS'h0
6333buf_waddr_reset_negedgereg
6191MCONTR_PHY_0BIT_CMDA_EN'h4
6190MCONTR_PHY_0BIT_DLY_SET'h0
6312wbuf_delay_m1wire[3:0]
6203MCONTR_PHY_STATUS_CNTRL'h4
6200MCONTR_PHY_16BIT_PATTERNS_TRI'h1
6350pause_lenwire[CMD_PAUSE_BITS-1:0]
6204DFLT_DQS_PATTERN8'h55
[PHASE_WIDTH-1:0] 6434ps_out
[DATA_WIDTH-1:0] 9934data
6328phy_cmd_wordwire[31:0]
cmd_deser_16bit_i cmd_deser
[ADDR_WIDTH-1:0] 9933addr
6313phy_16bit_addrwire[2:0]
6310dqs_tri_off_patternreg[3:0]
6201MCONTR_PHY_16BIT_WBUF_DELAY'h2
6347phy_cmd_add_pausewire
6314phy_16bit_datawire[15:0]
6193MCONTR_PHY_0BIT_CKE_EN'h8
6223CLKFBOUT_USE_FINE_PS1
6353pause_cntrreg[CMD_PAUSE_BITS-1:0]
6309dqs_tri_on_patternreg[3:0]
6192MCONTR_PHY_0BIT_SDRST_ACT'h6
6359run_chn_w_d_negedgereg[3:0]
6198MCONTR_PHY_16BIT_ADDR_MASK'h7f8
6195MCONTR_PHY_0BIT_DLY_RST'hc
[ALL_BITS-1:0] 10777status
6369control_status_wewire
6370contral_status_datawire[7:0]
[CMD_PAUSE_BITS-1:0] 6439pause_len