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x393
1.0
FPGAcodeforElphelNC393camera
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Files | |
| file | byte_lane.v [code] |
| DDR3 byte lane, including DQS I/O, 8xDQ I/O and DM output. | |
| file | cmd_addr.v [code] |
| DDR3 command/address signals. | |
| file | cmda_single.v [code] |
| Single-bit CMD/address output. | |
| file | dm_single.v [code] |
| Single-bit DDR3 DQ I/O, same used for DM. | |
| file | dq_single.v [code] |
| Single-bit DDR3 DQ I/O, same used for DM. | |
| file | dqs_single.v [code] |
| Single-bit DDR3 DQS I/O. | |
| file | dqs_single_nofine.v [code] |
| Single-bit DDR3 DQS I/O. | |
| file | mcontr_sequencer.v [code] |
| ddr3 sequnecer | |
| file | phy_cmd.v [code] |
| Executes a stream of commands to DDR3 phy at 1/2 ddr3 clock, global (also proveides r/w interface to the x64 external buffer) | |
| file | phy_top.v [code] |
| Top module of the DDR3 phy. | |