Static Public Member Functions

Always Constructs
ALWAYS_316	( mclk )
ALWAYS_317	( mclk )
ALWAYS_318	( mclk )
ALWAYS_319	( mclk )
ALWAYS_320	( mclk )

Public Attributes

Inputs
clk_in
rst_in
mrst
ref_clk
cmd0_clk
cmd0_we
cmd0_addr	[ 9 : 0 ]
cmd0_data	[ 31 : 0 ]
cmd1_clk
cmd1_we
cmd1_addr	[ 9 : 0 ]
cmd1_data	[ 31 : 0 ]
run_addr	[ 10 : 0 ]
run_chn	[ 3 : 0 ]
run_refresh
run_seq
cmd_ad	[ 7 : 0 ]
cmd_stb
status_start
ext_buf_rdata	[ 63 : 0 ]

Inouts
SDD	[ 15 : 0 ]
DQSL
NDQSL
DQSU
NDQSU

Outputs
SDRST
SDCLK
SDNCLK
SDA	[ADDRESS_NUMBER - 1 : 0 ]
SDBA	[ 2 : 0 ]
SDWE
SDRAS
SDCAS
SDCKE
SDODT
SDDML
SDDMU
mclk
locked
idelay_ctrl_reset
run_done
run_busy
mcontr_reset
status_ad	[ 7 : 0 ]
status_rq
ext_buf_page_nxt
ext_buf_rd
ext_buf_rpage_nxt
ext_buf_rchn	[ 3 : 0 ]
ext_buf_rrefresh
ext_buf_rrun
ext_buf_wr
ext_buf_wpage_nxt
ext_buf_wchn	[ 3 : 0 ]
ext_buf_wrefresh
ext_buf_wrun
ext_buf_wdata	[ 63 : 0 ]
tmp_debug	[ 11 : 0 ]

Parameters
DLY_LD	'h080
DLY_LD_MASK	'h780
MCONTR_PHY_0BIT_ADDR	'h020
MCONTR_PHY_0BIT_ADDR_MASK	'h7f0
MCONTR_PHY_0BIT_DLY_SET	'h0
MCONTR_PHY_0BIT_CMDA_EN	'h4
MCONTR_PHY_0BIT_SDRST_ACT	'h6
MCONTR_PHY_0BIT_CKE_EN	'h8
MCONTR_PHY_0BIT_DCI_RST	'ha
MCONTR_PHY_0BIT_DLY_RST	'hc
MCONTR_PHY_STATUS_REG_ADDR	'h0
MCONTR_PHY_16BIT_ADDR	'h050
MCONTR_PHY_16BIT_ADDR_MASK	'h7f8
MCONTR_PHY_16BIT_PATTERNS	'h0
MCONTR_PHY_16BIT_PATTERNS_TRI	'h1
MCONTR_PHY_16BIT_WBUF_DELAY	'h2
MCONTR_PHY_16BIT_EXTRA	'h3
MCONTR_PHY_STATUS_CNTRL	'h4
DFLT_DQS_PATTERN	8 'h55
DFLT_DQM_PATTERN	8 'h00
DFLT_DQ_TRI_ON_PATTERN	4 'h7
DFLT_DQ_TRI_OFF_PATTERN	4 'he
DFLT_DQS_TRI_ON_PATTERN	4 'h3
DFLT_DQS_TRI_OFF_PATTERN	4 'hc
DFLT_WBUF_DELAY	4 'h8
DFLT_INV_CLK_DIV	1 'b0
PHASE_WIDTH	8
SLEW_DQ	"SLOW"
SLEW_DQS	"SLOW"
SLEW_CMDA	"SLOW"
SLEW_CLK	"SLOW"
IBUF_LOW_PWR	"TRUE"
REFCLK_FREQUENCY	real 300 . 0
HIGH_PERFORMANCE_MODE	"FALSE"
CLKIN_PERIOD	10
CLKFBOUT_MULT	8
DIVCLK_DIVIDE	1
CLKFBOUT_USE_FINE_PS	1
CLKFBOUT_PHASE	0 . 000
SDCLK_PHASE	0 . 000
CLK_PHASE	0 . 000
CLK_DIV_PHASE	0 . 000
MCLK_PHASE	90 . 000
REF_JITTER1	0 . 010
SS_EN	"FALSE"
SS_MODE	"CENTER_HIGH"
SS_MOD_PERIOD	10000
CMD_PAUSE_BITS	10
CMD_DONE_BIT	10
ADDRESS_NUMBER	15

Signals
wire[ 7 : 0 ]	dly_data
wire[ 6 : 0 ]	dly_addr
wire	ld_delay
wire	set
wire[ 3 : 0 ]	phy_0bit_addr
wire	phy_0bit_we
reg	cmda_en
reg	ddr_rst
reg	dci_rst
reg	dly_rst
reg	ddr_cke
reg[ 7 : 0 ]	dqs_pattern
reg[ 7 : 0 ]	dqm_pattern
reg[ 3 : 0 ]	dq_tri_on_pattern
reg[ 3 : 0 ]	dq_tri_off_pattern
reg[ 3 : 0 ]	dqs_tri_on_pattern
reg[ 3 : 0 ]	dqs_tri_off_pattern
reg[ 3 : 0 ]	wbuf_delay
wire[ 3 : 0 ]	wbuf_delay_m1
wire[ 2 : 0 ]	phy_16bit_addr
wire[ 15 : 0 ]	phy_16bit_data
wire	phy_16bit_we
reg	inv_clk_div
wire	locked_mmcm
wire	locked_pll
wire	dly_ready
wire	dci_ready
wire[ 7 : 0 ]	ps_out
wire	ps_rdy
wire[ 14 : 0 ]	status_data
wire	phy_locked_mmcm
wire	phy_locked_pll
wire	phy_dly_ready
wire	phy_dci_ready
wire[ 31 : 0 ]	phy_cmd_word
wire[ 31 : 0 ]	phy_cmd0_word
wire[ 31 : 0 ]	phy_cmd1_word
reg	buf_raddr_reset
reg	buf_addr_reset
reg	buf_waddr_reset_negedge
reg	buf_wr_negedge
wire[ 63 : 0 ]	buf_wdata
reg[ 63 : 0 ]	buf_wdata_negedge
wire[ 63 : 0 ]	buf_rdata
wire	buf_wr
wire	buf_wr_ndly
wire	buf_rd
wire	buf_rst
wire	buf_rst_d
reg[ 9 : 0 ]	cmd_addr
reg	cmd_sel
reg[ 2 : 0 ]	cmd_busy
wire	phy_cmd_nop
wire	phy_cmd_add_pause
reg	add_pause
wire	sequence_done
wire[CMD_PAUSE_BITS - 1 : 0 ]	pause_len
reg	cmd_fetch
wire	pause
reg[CMD_PAUSE_BITS - 1 : 0 ]	pause_cntr
wire[ 3 : 0 ]	run_chn_w_d
wire	run_refresh_w_d
wire	run_w_d
reg[ 3 : 0 ]	run_chn_d
reg	run_refresh_d
reg[ 3 : 0 ]	run_chn_w_d_negedge
reg	run_refresh_w_d_negedge
reg	run_w_d_negedge
reg	run_seq_d
reg	mem_read_mode
wire[ 7 : 0 ]	tmp_debug_a
wire	set_patterns
wire	set_patterns_tri
wire	set_wbuf_delay
wire	set_extra
wire	control_status_we
wire[ 7 : 0 ]	contral_status_data
wire	ren0
wire	ren1

Module Instances
cmd_deser::cmd_deser_dly_i	Module cmd_deser
cmd_deser::cmd_deser_0bit_i	Module cmd_deser
cmd_deser::cmd_deser_16bit_i	Module cmd_deser
status_generate::status_generate_i	Module status_generate
ram_1kx32_1kx32::cmd0_buf_i	Module ram_1kx32_1kx32
ram_1kx32_1kx32::cmd1_buf_i	Module ram_1kx32_1kx32
phy_cmd::phy_cmd_i	Module phy_cmd
dly_16::buf_wr_dly_i	Module dly_16
dly_16::buf_wchn_dly_i	Module dly_16