53 parameter CLKFBOUT_MULT =
8,
// Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE 66 parameter CMD_DONE_BIT=
10 // bit number (address) to signal sequence done 69 output SDRST,
// DDR3 reset (active low) 70 output SDCLK,
// DDR3 clock differential output, positive 71 output SDNCLK,
// DDR3 clock differential output, negative 72 output [
ADDRESS_NUMBER-
1:
0]
SDA,
// output address ports (14:0) for 4Gb deviceencode_seq_word 73 output [
2:
0]
SDBA,
// output bank address ports 74 output SDWE,
// output WE port 75 output SDRAS,
// output RAS port 76 output SDCAS,
// output CAS port 77 output SDCKE,
// output Clock Enable port 78 output SDODT,
// output ODT port 80 inout [
15:
0]
SDD,
// DQ I/O pads 81 output SDDML,
// LDM I/O pad (actually only output) 82 inout DQSL,
// LDQS I/O pad 84 output SDDMU,
// UDM I/O pad (actually only output) 85 inout DQSU,
// UDQS I/O pad 90 output mclk,
// global clock, half DDR3 clock, synchronizes all I/O through the command port 91 input mrst,
// @posedge mclk synchronous reset - should not interrupt mclk generation 92 input ref_clk,
// global clock for idelay_ctrl calibration 94 // inteface to control I/O delays and mmcm 95 input [
7:
0]
dly_data,
// delay value (3 LSB - fine delay) 96 input [
6:
0]
dly_addr,
// select which delay to program 97 input ld_delay,
// load delay data to selected iodelayl (clk_div synchronous) 98 input set,
// clk_div synchronous set all delays from previously loaded values 117 input add_pause,
// use previous command settings, just replace command with nop 120 // external memory buffer (cs- channel select, high addresses- page addresses are decoded externally) 121 output [
63:
0]
buf_wdata,
// data to be written to the buffer (from DDR3), valid @ negedge mclk 122 input [
63:
0]
buf_rdata,
// data read from the buffer (to DDR3) 123 output buf_wr,
// write buffer (next cycle!) 124 output buf_rd,
// read buffer (ready next cycle) 125 output buf_rst,
// reset external buffer address to page start 127 input cmda_en,
// tristate command and address lines // not likely to be used 128 input ddr_rst,
// generate reset to DDR3 memory (active high) 129 input dci_rst,
// active high - reset DCI circuitry 130 input dly_rst,
// active high - delay calibration circuitry 131 input ddr_cke,
// DDR clock enable , XOR-ed with command bit 141 // Decoding phy_cmd[35:0] into individual fields; 144 wire [
2:
0]
phy_rcw_pos;
// positive lof=gic for RAS, CAS, WE (0 - NOP) 150 wire phy_sel_in;
// first/second half-cycle, oter will be nop (cke+odt applicable to both) 153 wire phy_dq_tri_in;
// tristate DQ lines (internal timing sequencer for 0->1 and 1->0) 154 wire phy_dqs_tri_in;
// tristate DQS lines (internal timing sequencer for 0->1 and 1->0) 155 wire phy_dci_en_in;
// DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 156 wire phy_dci_in;
// DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 165 wire phy_cke_dis_cur;
// disable cke (0 - enable), also controlled by a command bit ddr_cke (XOR-ed) 166 wire phy_sel_cur;
// first/second half-cycle, oter will be nop (cke+odt applicable to both) 167 wire phy_dq_en_cur;
//phy_dq_tri_in, // tristate DQ lines (internal timing sequencer for 0->1 and 1->0) 168 wire phy_dqs_en_cur;
//phy_dqs_tri_in, // tristate DQS lines (internal timing sequencer for 0->1 and 1->0) 170 wire phy_dci_en_cur;
//phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 179 reg ld_delay_r;
// load delay data to selected iodelayl (clk_div synchronous) 180 reg set_r;
// clk_div synchronous set all delays from previously loaded values 186 wire [
1:
0]
phy_cke;
// may be optphy_dqs_tri_inimized? 187 wire [
7:
0]
phy_dq_tri;
// tristate DQ lines (internal timing sequencer for 0->1 and 1->0) 188 wire [
7:
0]
phy_dqs_tri;
// tristate DQS lines (internal timing sequencer for 0->1 and 1->0) 203 wire [
63:
0]
phy_rdata;
// data read from ddr3 iserdese2 at posedge clk_div 217 phy_cke_dis,
// disable cke (0 - enable), also controlled by a command bit ddr_cke (XOR-ed) 218 phy_sel_in,
// fitst/second half-cycle, oter will be nop (cke+odt applicable to both) 219 phy_dq_en_in,
//phy_dq_tri_in, // tristate DQ lines (internal timing sequencer for 0->1 and 1->0) 220 phy_dqs_en_in,
//phy_dqs_tri_in, // tristate DQS lines (internal timing sequencer for 0->1 and 1->0) 222 phy_dci_en_in,
//phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 223 phy_buf_wr,
// connect to external buffer (but only if not paused) 224 phy_buf_rd,
// connect to external buffer (but only if not paused) 226 phy_buf_rst // phy_spare // Reserved for future use 232 phy_cke_dis_cur,
// 8 7 disable cke (0 - enable), also controlled by a command bit ddr_cke (XOR-ed) 233 phy_sel_cur,
// 7 6 first/second half-cycle, other will be nop (cke+odt applicable to both) - NOT USED? 234 phy_dq_en_cur,
// 6 5 phy_dq_tri_in, // tristate DQ lines (internal timing sequencer for 0->1 and 1->0) 235 phy_dqs_en_cur,
// 5 4 phy_dqs_tri_in, // tristate DQS lines (internal timing sequencer for 0->1 and 1->0) 237 phy_dci_en_cur,
// 3 2 phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 238 phy_buf_wr_cur,
// 2 1 connect to external buffer (but only if not paused) 239 phy_buf_rd_cur,
// 1 0 connect to external buffer (but only if not paused) 245 phy_cke_dis,
// disable cke (0 - enable), also controlled by a command bit ddr_cke (XOR-ed) 246 phy_sel_in,
// first/second half-cycle, oter will be nop (cke+odt applicable to both) 247 phy_dq_en_in,
//phy_dq_tri_in, // tristate DQ lines (internal timing sequencer for 0->1 and 1->0) 248 phy_dqs_en_in,
//phy_dqs_tri_in, // tristate DQS lines (internal timing sequencer for 0->1 and 1->0) 250 phy_dci_en_in,
//phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 251 phy_buf_wr,
// connect to external buffer (but only if not paused) 252 phy_buf_rd,
// connect to external buffer (but only if not paused) 276 // tristate DQ lines (internal timing sequencer for 0->1 and 1->0) 279 // tristate DQS lines (internal timing sequencer for 0->1 and 1->0) 282 assign phy_dci_dis_dq =
phy_dci_in;
// DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 312 phy_cke_dis,
// 8 7 disable cke (0 - enable), also controlled by a command bit ddr_cke (XOR-ed) 313 phy_sel_in,
// 7 6 first/second half-cycle, other will be nop (cke+odt applicable to both) 314 phy_dq_en_in,
// 6 5 phy_dq_tri_in, // tristate DQ lines (internal timing sequencer for 0->1 and 1->0) 315 phy_dqs_en_in,
// 5 4 phy_dqs_tri_in, // tristate DQS lines (internal timing sequencer for 0->1 and 1->0) 317 phy_dci_en_in,
// 3 2 phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 318 phy_buf_wr,
// 2 1 connect to external buffer (but only if not paused) 319 phy_buf_rd,
// 1 0 connect to external buffer (but only if not paused) 320 phy_buf_rst // 0 connect to external buffer (but only if not paused) 327 // cross clock boundary posedge mclk -> posedge clk_div (mclk is later than clk_div) 346 // cross clock boundary posedge posedge clk_div->negedge clk_div -> posedge mclk (mclk is later than clk_div) 378 .
IOSTANDARD_DQ (
"SSTL15_T_DCI"),
379 .
IOSTANDARD_DM (
"SSTL15"),
380 .
IOSTANDARD_DQS (
"DIFF_SSTL15_T_DCI"),
381 .
IOSTANDARD_CMDA (
"SSTL15"),
382 .
IOSTANDARD_CLK (
"DIFF_SSTL15"),
388 .
IODELAY_GRP (
"IODELAY_MEMORY"),
393 .
BANDWIDTH (
"OPTIMIZED"),
418 .
dq (
SDD[
15:
0]),
// inout[15:0] [ 3:0] 6454dq_tri_on_pattern
6520phy_addr_prevreg[ADDRESS_NUMBER-1:0]
6381HIGH_PERFORMANCE_MODE"FALSE"
[ADDRESS_NUMBER-1:0] 6559ddr3_a
6493phy_addrwire[2*ADDRESS_NUMBER-1:0]
6472phy_dqs_toggle_enwire
[ADDRESS_NUMBER-1:0] 6400SDA
[ 3:0] 6455dq_tri_off_pattern
[ 3:0] 6456dqs_tri_on_pattern
6458phy_addr_inwire[ADDRESS_NUMBER-1:0]
6505phy_ps_outwire[PHASE_WIDTH-1:0]
6516ps_out_r1reg[PHASE_WIDTH-1:0]
6385CLKFBOUT_USE_FINE_PS1
[ 3:0] 6457dqs_tri_off_pattern
6523phy_bank_calmwire[2:0]
6517ps_out_r2reg[PHASE_WIDTH-1:0]
[PHASE_WIDTH-1:0] 6434ps_out
real 6380REFCLK_FREQUENCY300.0
[2*ADDRESS_NUMBER-1:0] 6584in_a
6483phy_dqs_toggle_curwire
6521phy_bank_prevreg[2:0]
[PHASE_WIDTH-1:0] 6611ps_out
6522phy_addr_calmwire[ADDRESS_NUMBER-1:0]
[CMD_PAUSE_BITS-1:0] 6439pause_len