Static Public Member Functions

Always Constructs
ALWAYS_321	( mclk )
ALWAYS_322	( mclk )
ALWAYS_323	( clk_div )
ALWAYS_324	( clk_div )
ALWAYS_325	( clk_div )
ALWAYS_326	( mclk )
ALWAYS_327	( mclk )

Public Attributes

Inputs
clk_in
rst_in
mrst
ref_clk
dly_data	[ 7 : 0 ]
dly_addr	[ 6 : 0 ]
ld_delay
set
phy_cmd_word	[ 31 : 0 ]
add_pause
buf_rdata	[ 63 : 0 ]
cmda_en
ddr_rst
dci_rst
dly_rst
ddr_cke
inv_clk_div
dqs_pattern	[ 7 : 0 ]
dqm_pattern	[ 7 : 0 ]
dq_tri_on_pattern	[ 3 : 0 ]
dq_tri_off_pattern	[ 3 : 0 ]
dqs_tri_on_pattern	[ 3 : 0 ]
dqs_tri_off_pattern	[ 3 : 0 ]

Inouts
SDD	[ 15 : 0 ]
DQSL
NDQSL
DQSU
NDQSU

Outputs
SDRST
SDCLK
SDNCLK
SDA	[ADDRESS_NUMBER - 1 : 0 ]
SDBA	[ 2 : 0 ]
SDWE
SDRAS
SDCAS
SDCKE
SDODT
SDDML
SDDMU
mclk
idelay_ctrl_reset
locked_mmcm
locked_pll
dly_ready
dci_ready
phy_locked_mmcm
phy_locked_pll
phy_dly_ready
phy_dci_ready
tmp_debug	[ 7 : 0 ]
ps_rdy
ps_out	[PHASE_WIDTH - 1 : 0 ]
phy_cmd_nop
phy_cmd_add_pause
pause_len	[CMD_PAUSE_BITS - 1 : 0 ]
sequence_done
buf_wdata	[ 63 : 0 ]
buf_wr
buf_rd
buf_rst

Parameters
ADDRESS_NUMBER	15
PHASE_WIDTH	8
SLEW_DQ	"SLOW"
SLEW_DQS	"SLOW"
SLEW_CMDA	"SLOW"
SLEW_CLK	"SLOW"
IBUF_LOW_PWR	"TRUE"
REFCLK_FREQUENCY	real 300 . 0
HIGH_PERFORMANCE_MODE	"FALSE"
CLKIN_PERIOD	10
CLKFBOUT_MULT	8
DIVCLK_DIVIDE	1
CLKFBOUT_USE_FINE_PS	1
CLKFBOUT_PHASE	0 . 000
SDCLK_PHASE	0 . 000
CLK_PHASE	0 . 000
CLK_DIV_PHASE	0 . 000
MCLK_PHASE	90 . 000
REF_JITTER1	0 . 010
SS_EN	"FALSE"
SS_MODE	"CENTER_HIGH"
SS_MOD_PERIOD	10000
CMD_PAUSE_BITS	10
CMD_DONE_BIT	10

Signals
wire[ADDRESS_NUMBER - 1 : 0 ]	phy_addr_in
wire[ 2 : 0 ]	phy_bank_in
wire[ 2 : 0 ]	phy_rcw_pos
wire[ 2 : 0 ]	phy_rcw_in
wire	phy_odt_in
wire	phy_cke_dis
wire	phy_cke_in
wire	phy_sel_in
wire	phy_dq_en_in
wire	phy_dqs_en_in
wire	phy_dq_tri_in
wire	phy_dqs_tri_in
wire	phy_dci_en_in
wire	phy_dci_in
wire	phy_dqs_toggle_en
wire	phy_buf_wr
wire	phy_buf_rd
wire	phy_buf_rst
wire	cmda_tri
wire[ 2 : 0 ]	phy_rcw_cur
wire	phy_odt_cur
wire	phy_cke_dis_cur
wire	phy_sel_cur
wire	phy_dq_en_cur
wire	phy_dqs_en_cur
wire	phy_dqs_toggle_cur
wire	phy_dci_en_cur
wire	phy_buf_wr_cur
wire	phy_buf_rd_cur
wire	phy_buf_rst_cur
wire	clk_div
reg[ 7 : 0 ]	dly_data_r
reg[ 6 : 0 ]	dly_addr_r
reg	ld_delay_r
reg	set_r
wire[ 2 ADDRESS_NUMBER* - 1 : 0 ]**	phy_addr
wire[ 5 : 0 ]	phy_bank
wire[ 5 : 0 ]	phy_rcw
wire[ 1 : 0 ]	phy_odt
wire[ 1 : 0 ]	phy_cke
wire[ 7 : 0 ]	phy_dq_tri
wire[ 7 : 0 ]	phy_dqs_tri
wire	phy_dci_dis_dq
wire	phy_dci_dis_dqs
reg	dqs_tri_prev
reg	dq_tri_prev
wire	phy_ps_rdy
wire[PHASE_WIDTH - 1 : 0 ]	phy_ps_out
reg	ps_rdy_r1
reg	ps_rdy_r2
reg	locked_mmcm_r1
reg	locked_mmcm_r2
reg	locked_pll_r1
reg	locked_pll_r2
reg	dly_ready_r1
reg	dly_ready_r2
reg	dci_ready_r1
reg	dci_ready_r2
reg[PHASE_WIDTH - 1 : 0 ]	ps_out_r1
reg[PHASE_WIDTH - 1 : 0 ]	ps_out_r2
wire[ 63 : 0 ]	phy_rdata
reg[ 63 : 0 ]	phy_rdata_r
reg[ADDRESS_NUMBER - 1 : 0 ]	phy_addr_prev
reg[ 2 : 0 ]	phy_bank_prev
wire[ADDRESS_NUMBER - 1 : 0 ]	phy_addr_calm
wire[ 2 : 0 ]	phy_bank_calm
reg[ 9 : 0 ]	extra_prev
reg	rst_clk_div
wire[ 7 : 0 ]	dqs_data