dly_16.v

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`timescale 1ns/1ps

module  dly_16 #(
    parameter WIDTH=1
    )(
    input               clk,
    input               rst,
    input         [3:0] dly,
    input   [WIDTH-1:0] din,
    output  [WIDTH-1:0] dout
);
  generate
    genvar i;
    for (i=0; i < WIDTH; i=i+1) begin: bit_block
        dly01_16 dly01_16_i (
            .clk(clk), // input
            .rst(rst), // input
            .dly(dly), // input[3:0] 
            .din(din[i]), // input
            .dout(dout[i]) // output reg 
        );
    end
  endgenerate
endmodule