os/linux-2.6-tag--devboard-R2_10-4/arch/cris/arch-v32/drivers/elphel/x353.h File Reference

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Defines

#define X313_MINMODREV   0x03534000

#define X313_MAXMODREV   0x035340ff

#define X313__RA__STATUS   0x10

#define X313__RA__IRQS   0x11

#define X313__RA__TRIGPH   0x12

#define X313__RA__MODEL   0x13

#define X313__RA__TABLE   0x14

#define X313__RA__XFERCNTR   0x14

#define X313__RA__HIGHFREQ   0x15

#define X313__RA__IOPINS   0x70

#define X313__RA__SENSFPGA   0x74

#define SFPGA_RD_BIT   16

#define I2C_FRAME_NUMBER   0x16

#define X313__RA__SDCH0   0x20

#define X313__RA__SDCH1   0x24

#define X313__RA__SDCH2   0x28

#define X313__RA__SDCH3   0x2c

#define X313__RA__SDBUF3   0x30

#define X313_SR__CLK_LOCKED   28

#define X313_SR__SENS_DCM_OVFL   27

#define X313_SR__SENS_DCM_LOCKED   26

#define X313_SR__SENS_DCM_RDY   25

#define X313_SR__SENS_DCM_EARLY   24

#define X313_SR__SENS_DCM_LATE   23

#define X313_SR__SENS_DCM_ERROR   24

#define X313_SR__SENS_DCM_LATE   23

#define X313_SENSOR_PHASE   ((port_csp0_addr[X313__RA__STATUS] >> X313_SR__SENS_DCM_LATE ) & 3)

#define X313_SR__DCM_OVFL   22

#define X313_SR__DCM_LOCKED   21

#define X313_SR__DCM_RDY   20

#define X313_SR__DCM_EARLY   19

#define X313_SR__DCM_LATE   18

#define X313_SR__DMA_EMPTY   17

#define X313_SR__DONE_CMPRS   16

#define X313_SR__DONE_CI   15

#define X313_SR__DCCRDY   14

#define X313_SR__DONE   13

#define X313_SR__SENST1   12

#define X313_SR__SENST0   11

#define X313_SR__NXTFR3   10

#define X313_SR__NXTFR2   9

#define X313_SR__NXTFR1   8

#define X313_SR__NXTFR0   7

#define X313_SR__PIOWEMPTY   6

#define X313_SR__PIORDY   5

#define X313_SR__CH2RDY   4

#define X313_SR__CH1RDY   3

#define X313_SR__CH0RDY   2

#define X313_SR__SCL0   1

#define X313_SR__SDA0   0

#define X313_PIOR__SCL1   0

#define X313_PIOR__SDA1   1

#define X313_PIOR__XRST   2

#define X313_PIOR__AUXCLK   3

#define X313_PIOR__EXPS   4

#define X313_PIOR__TRIG   5

#define X313_SR__X323_SI   0

#define X313_SR(x)   ((port_csp0_addr[X313__RA__STATUS] >> X313_SR__##x ) & 1)

#define X313_PIOR(x)   ((port_csp0_addr[X313__RA__IOPINS] >> X313_PIOR__##x ) & 1)

#define X313_IR__VACT   0

#define X313_IR__XINT   1

#define X313_IR__XFEROVR   2

#define X313_IR__DONE   3

#define X313_IR__EOT   4

#define X313_IR__DCC   5

#define X313_IR__DONE_INPUT   6

#define X313_IR__DONE_COMPRESS   7

#define X313_IR__SMART   8

#define X313_IR(x)   ((port_csp0_addr[X313__RA__IRQS] >> ( X313_IR__##x ) + 8) & 1)

#define EN_INTERRUPT(x)   port_csp0_addr[X313_WA_IRQ_ENA]= (1<< ( X313_IR__##x ))

#define DIS_INTERRUPT(x)   {port_csp0_addr[X313_WA_IRQ_DIS]= (1<< ( X313_IR__##x ) ); port_csp0_addr[X313_WA_IRQ_RST]= (1<< ( X313_IR__##x ) );}

#define DIS_INTERRUPTS   {port_csp0_addr[X313_WA_IRQ_DIS]= 0xffff; port_csp0_addr[X313_WA_IRQ_RST]= 0xffff;}

#define X313_WA_WCTL   0

#define X313_WA_DMACR   1

#define X313_WA_SENSFPN   2

#define X313_SENSFPN_D(t, s, m, d, l)

#define X313_WA_VIRTTRIG   3

#define X313_WA_TRIG   4

#define X313_WA_NLINES   5

#define X313_WA_WCTL24   6

#define X313_WA_DCDC   7

#define X313_WA_DCM   8

#define X3X3_RSTSENSDCM   {port_csp0_addr[X313_WA_DCM]=0xf0;}

#define X3X3_SENSDCM_INC90   {port_csp0_addr[X313_WA_DCM]=0x80;}

#define X3X3_SENSDCM_DEC90   {port_csp0_addr[X313_WA_DCM]=0x40;}

#define X3X3_SENSDCM_INC   {port_csp0_addr[X313_WA_DCM]=0x20;}

#define X3X3_SENSDCM_DEC   {port_csp0_addr[X313_WA_DCM]=0x10;}

#define X3X3_SENSDCM_NOP   {port_csp0_addr[X313_WA_DCM]=0x0;}

#define X313_WA_COLOR_SAT   9

#define DEFAULT_COLOR_SATURATION_BLUE   0x90

#define DEFAULT_COLOR_SATURATION_RED   0xb6

#define X313_WA_FRAMESYNC_DLY   0x0a

#define X313_WA_QUANTIZER_MODE   0x0b

#define X313_WA_COMP_CMD   0x0c

#define COMPCMD_FOCUS(x)   ((1<<23) | (((x) & 3) << 21))

#define COMPCMD_BAYERSHIFT(x)   ((1<<20) | (((x) & 3) << 18))

#define COMPCMD_TILESHIFT(x)   ((1<<17) | (((x) & 7) << 14))

#define COMPCMD_DEMOS(x)   ((1<<13) | (((x) & 0x0f) << 9))

#define DEMOS_MONO6   0

#define DEMOS_COLOR18   1

#define DEMOS_JP46   2

#define DEMOS_JP46DC   3

#define DEMOS_COLOR20   4

#define DEMOS_JP4   5

#define DEMOS_JP4DC   6

#define DEMOS_JP4DIFF   7

#define DEMOS_JP4HDR   8

#define DEMOS_JP4DIFF2   9

#define DEMOS_JP4HDR2   10

#define DEMOS_MONO4   14

#define COMPCMD_DCSUB(x)   ((1<<8) | (((x) & 1) << 7))

#define COMPCMD_QTAB(x)   ((1<<6) | (((x) & 7) << 3))

#define FPGA_NQTAB   8

#define COMPCMD_RESET   4

#define COMPCMD_STOP   5

#define COMPCMD_SINGLE   6

#define COMPCMD_RUN   7

#define X313_WA_COMP_TA   0x0e

#define X313_WA_COMP_TD   0x0f

#define X313_WA_MCUNUM   0x0d

#define X313_WA_SMART_IRQ   0x1a

FIXME: (in FPGA) - now if "smart" mode is disabled, VACT will not cause interrupt on smart bit. So smart mode will be always enabled for now.

#define X313_WA_DCM_RST   0x1b

#define X313_WA_IRQ_RST   0x1c

#define X313_WA_IRQ_DIS   0x1d

#define X313_WA_IRQ_ENA   0x1e

#define X313_WA_IRQ_WVECT   0x1f

#define EN_INTERRUPT(x)   port_csp0_addr[X313_WA_IRQ_ENA]= (1<< ( X313_IR__##x ))

#define DIS_INTERRUPT(x)   {port_csp0_addr[X313_WA_IRQ_DIS]= (1<< ( X313_IR__##x ) ); port_csp0_addr[X313_WA_IRQ_RST]= (1<< ( X313_IR__##x ) );}

#define DIS_INTERRUPTS   {port_csp0_addr[X313_WA_IRQ_DIS]= 0xffff; port_csp0_addr[X313_WA_IRQ_RST]= 0xffff;}

#define X313_WA_HIST_LEFT   0x40

#define X313_WA_HIST_TOP   0x41

#define X313_WA_HIST_WIDTH   0x42

#define X313_WA_HIST_HEIGHT   0x43

#define X313_WA_HIST_ADDR   0x44

#define X313_RA_HIST_DATA   0x45

#define X313_WA_RTC_USEC   0x48

#define X313_WA_RTC_SEC   0x49

#define X313_WA_RTC_CORR   0x4a

#define X313_WA_RTC_LATCH   0x4b

#define X313_RA_RTC_USEC   0x48

#define X313_RA_RTC_SEC   0x49

#define X313_WA_TIMESTAMP   0x4c

#define X313_TIMESTAMPLEN   28

#define X313_WA_DCR0   0x4e

#define X313_WA_DCR1   0x4f

#define X353_DCR0(x, y)   (((((y) & ((1 << X353DCR0__##x##__WIDTH)-1))) | (1 << X353DCR0__##x##__WIDTH) ) << X353DCR0__##x##__BITNM)

#define X353_DCR1(x, y)   (((((y) & ((1 << X353DCR1__##x##__WIDTH)-1))) | (1 << X353DCR1__##x##__WIDTH) ) << X353DCR1__##x##__BITNM)

#define X353DCR0__BAYER_PHASE__BITNM   0

============ X313_WA_DCR0 ==============

#define X353DCR0__BAYER_PHASE__WIDTH   2

#define X353DCR0__FILLFACTORY__BITNM   3

#define X353DCR0__FILLFACTORY__WIDTH   1

#define X353DCR0__DLYHOR__BITNM   5

#define X353DCR0__DLYHOR__WIDTH   1

#define X353DCR0__NEGRST__BITNM   7

#define X353DCR0__NEGRST__WIDTH   1

#define X353DCR0__SKIPLINEL__BITNM   9

#define X353DCR0__SKIPLINE__WIDTH   1

#define X353DCR0__XT_POL__BITNM   11

#define X353DCR0__XT_POL__WIDTH   1

#define X353DCR0__ARST__BITNM   13

#define X353DCR0__ARST__WIDTH   1

#define X353DCR0__ARO__BITNM   15

#define X353DCR0__ARO__WIDTH   1

#define X353DCR0__CNVEN__BITNM   17

#define X353DCR0__CNVEN__WIDTH   1

#define X353DCR0__SENSTRIGEN__BITNM   19

#define X353DCR0__SENSTRIGEN__WIDTH   1

#define X353DCR1__MRST__BITNM   0

============ X313_WA_DCR1 ==============

#define X353DCR1__MRST__WIDTH   1

#define X353DCR1__EARLYTRIG__BITNM   2

#define X353DCR1__EARLYTRIG__WIDTH   1

#define X353DCR1__DCLKMODE__BITNM   4

#define X353DCR1__DCLKMODE__WIDTH   1

#define X353DCR1__PXD14__BITNM   6

#define X353DCR1__PXD14__WIDTH   1

#define X353DCR1__HACT_PHASE__BITNM   8

#define X353DCR1__HACT_PHASE__WIDTH   2

#define X353DCR1__PCLKSRC__BITNM   11

#define X353DCR1__PCLKSRC__WIDTH   2

#define X353DCR1__HFCOMP__BITNM   14

#define X353DCR1__HFCOMP__WIDTH   3

#define X353DCR1__BLOCKVSYNC__BITNM   18

#define X353DCR1__BLOCKVSYNC__WIDTH   1

#define CCAM_ARO_ON   port_csp0_addr[X313_WA_DCR0]=X353_DCR0(ARO,1)

#define CCAM_ARO_OFF   port_csp0_addr[X313_WA_DCR0]=X353_DCR0(ARO,0)

#define CCAM_DCLK_OFF   port_csp0_addr[X313_WA_DCR1]=X353_DCR1(DCLKMODE,1)

turn clock to sensor on/off (default - on)

#define CCAM_DCLK_ON   port_csp0_addr[X313_WA_DCR1]=X353_DCR1(DCLKMODE,0)

#define CCAM_ARST_OFF   port_csp0_addr[X313_WA_DCR0]=X353_DCR0(ARST,1)

#define CCAM_ARST_ON   port_csp0_addr[X313_WA_DCR0]=X353_DCR0(ARST,0)

#define CCAM_MRST_OFF   port_csp0_addr[X313_WA_DCR1]=X353_DCR1(MRST,1)

#define CCAM_MRST_ON   port_csp0_addr[X313_WA_DCR1]=X353_DCR1(MRST,0)

#define CCAM_NEGRST   port_csp0_addr[X313_WA_DCR0]=X353_DCR0(NEGRST,1)

#define CCAM_POSRST   port_csp0_addr[X313_WA_DCR0]=X353_DCR0(NEGRST,0)

#define CCAM_CNVEN_ON   port_csp0_addr[X313_WA_DCR0]=X353_DCR0(CNVEN,1)

enable power converter control. *** Only if it is not MT9P001 !!! ***

#define CCAM_CNVEN_OFF   port_csp0_addr[X313_WA_DCR0]=X353_DCR0(CNVEN,0)

#define CCAM_TRIG_INT   port_csp0_addr[X313_WA_DCR0]=X353_DCR0(SENSTRIGEN,0)

Sensor (MT9X001) trigger source selection (internal/external).

#define CCAM_TRIG_EXT   port_csp0_addr[X313_WA_DCR0]=X353_DCR0(SENSTRIGEN,1)

#define CCAM_TIMESTAMP_NORMAL   port_csp0_addr[X313_WA_DCR1]=X353_DCR1(EARLYTRIG,0)

early/normal timestamp in async mode

#define CCAM_TIMESTAMP_EARLY   port_csp0_addr[X313_WA_DCR1]=X353_DCR1(EARLYTRIG,1)

#define CCAM_SET_HACT_PHASE(x)   port_csp0_addr[X313_WA_DCR1]=X353_DCR1(HACT_PHASE,(x))

Set HACT phase (90 degrees increments - needed for MT9P001.

#define CCAM_VSYNC_ON   port_csp0_addr[X313_WA_DCR1]=X353_DCR1(BLOCKVSYNC,0)

#define CCAM_VSYNC_OFF   port_csp0_addr[X313_WA_DCR1]=X353_DCR1(BLOCKVSYNC,1)

#define X313_I2C_FRAME0   0x50

=============================

#define X313_I2C_FRAME1   0x51

#define X313_I2C_FRAME2   0x52

#define X313_I2C_FRAME3   0x53

#define X313_I2C_FRAME4   0x54

#define X313_I2C_FRAME5   0x55

#define X313_I2C_FRAME6   0x56

#define X313_I2C_FRAME7   0x57

#define X313_I2C_ASAP   0x58

#define X313_I2C_NEXT   0x59

#define X313_I2C_NEXT2   0x5a

#define X313_I2C_NEXT3   0x5b

#define X313_I2C_NEXT4   0x5c

#define X313_I2C_NEXT5   0x5d

#define X313_I2C_NEXT6   0x5e

#define X313_I2C_CMD   0x5f

#define X3X3_SET_I2C_DLY(x)   (0x100 | ((x) & 0xff))

#define X3X3_SET_I2C_BYTES(x)   (0x800 | (((x)<<9) & 0x600))

#define X3X3_I2C_RUN_BITS   0x3000

#define X3X3_I2C_STOP_BITS   0x2000

#define X3X3_I2C_RESET_BITS   0x4000

#define X3X3_I2C_SCL_0_BITS   0x10000

software control of SDA0, SCL0 lines (when hardware i2c is off)

#define X3X3_I2C_SCL_1_BITS   0x20000

#define X3X3_I2C_SCL_Z_BITS   0x30000

#define X3X3_I2C_SDA_0_BITS   0x40000

#define X3X3_I2C_SDA_1_BITS   0x80000

#define X3X3_I2C_SDA_Z_BITS   0xc0000

#define X3X3_I2C_IS_BUSY

#define X3X3_I2C_FRAME   (port_csp0_addr[I2C_FRAME_NUMBER] & 0x7)

#define X3X3_I2C_SEND2(a, s, r, d)   {port_csp0_addr[a] = ((s)<<24) | (((r) & 0xff) << 16) | ((d) & 0xffff) ; X3X3_AFTERWRITE ;}

#define X3X3_I2C_SEND1(a, s, r, d)   {port_csp0_addr[a] = ((s)<<24) | (((r) & 0xff) << 16) | (((d) & 0xff) << 8) ; X3X3_AFTERWRITE ;}

#define X3X3_GAMMA_PAGE   ((port_csp0_addr[I2C_FRAME_NUMBER] & 0x20000)?1:0)

#define X3X3_I2C_STOP_WAIT   {port_csp0_addr[X313_I2C_CMD]=X3X3_I2C_STOP_BITS; while (X3X3_I2C_IS_BUSY) ; }

X3X3_I2C_STOP_WAIT does not stop frame counter - it still counts frame pulses.

#define X3X3_I2C_RUN   {port_csp0_addr[X313_I2C_CMD]=X3X3_I2C_RUN_BITS ; X3X3_AFTERWRITE ;}

#define X3X3_I2C_RESET_WAIT   {port_csp0_addr[X313_I2C_CMD]=X3X3_I2C_RESET_BITS; while (X3X3_I2C_IS_BUSY) ; }

#define X313_SEQ_FRAME0   0x60

#define X313_SEQ_FRAME1   0x61

#define X313_SEQ_FRAME2   0x62

#define X313_SEQ_FRAME3   0x63

#define X313_SEQ_FRAME4   0x64

#define X313_SEQ_FRAME5   0x65

#define X313_SEQ_FRAME6   0x66

#define X313_SEQ_FRAME7   0x67

#define X313_SEQ_ASAP   0x68

#define X313_SEQ_NEXT   0x69

#define X313_SEQ_NEXT2   0x6a

#define X313_SEQ_NEXT3   0x6b

#define X313_SEQ_NEXT4   0x6c

#define X313_SEQ_NEXT5   0x6d

#define X313_SEQ_NEXT6   0x6e

#define X313_SEQ_CMD   0x6f

#define X3X3_SEQ_RUN_BITS   0x3000

#define X3X3_SEQ_STOP_BITS   0x2000

#define X3X3_SEQ_RESET_BITS   0x4000

#define X3X3_SEQ_SEND1(f, a, d)   {port_csp0_addr[f] = ((a)<<24) | ((d) & 0xffffff) ; X3X3_AFTERWRITE ;}

#define X3X3_SEQ_STOP   {port_csp0_addr[X313_SEQ_CMD]=X3X3_SEQ_STOP_BITS;}

#define X3X3_SEQ_RUN   {port_csp0_addr[X313_SEQ_CMD]=X3X3_SEQ_RUN_BITS ; X3X3_AFTERWRITE ;}

#define X3X3_SEQ_RESET   {port_csp0_addr[X313_SEQ_CMD]=X3X3_SEQ_RESET_BITS; X3X3_AFTERWRITE ; X3X3_AFTERWRITE ; X3X3_AFTERWRITE ; X3X3_AFTERWRITE ; }

#define X313_WA_IOPINS   0x70

#define X313_WA_SENSFPGA   0x74

#define X313_WA_CAMSYNCTRIG   0x78

#define X313_WA_CAMSYNCDLY   0x79

#define X313_WA_CAMSYNCOUT   0x7a

#define X313_WA_CAMSYNCPER   0x7b

#define SFPGA_TDI_BIT   0x0

#define SFPGA_TMS_BIT   0x2

#define SFPGA_TCK_BIT   0x4

#define SFPGA_PROG_BIT   0x6

#define SFPGA_PGMEN_BIT   0x8

#define SFPGA_RD_SENSPGMPIN   0x80000

#define SFPGA_RD_TDO   0x90000

#define SFPGA_RD_DONE   0xa0000

#define X3X3_AFTERWRITE   {if (!port_csp0_addr[X313__RA__MODEL]) printk ("model=0");}

#define x3x3_DELAY(x)   {int iiii; for (iiii=0; iiii < (x); iiii++) X3X3_AFTERWRITE ; }

#define X313_WA_SDCH0_CTL0   0x20

#define X313_WA_SDCH0_CTL1   0x21

#define X313_WA_SDCH0_CTL2   0x22

#define X313_WA_SD_MANCMD   0x23

#define X313_WA_SDCH1_CTL0   0x24

#define X313_WA_SDCH1_CTL1   0x25

#define X313_WA_SDCH1_CTL2   0x26

#define X313_WA_SD_MODE   0x27

#define X313_WA_SDCH2_CTL0   0x28

#define X313_WA_SDCH2_CTL1   0x29

#define X313_WA_SDCH2_CTL2   0x2a

#define X313_WA_SDCH3_CTL0   0x2c

#define X313_WA_SDCH3_CTL1   0x2d

#define X313_WA_SDCH3_CTL2   0x2e

#define X313_WA_SDPIO_NEXT   0x2f

#define X313_WA_SD_PIOWIN   0x30

#define X313_WA_LENSCORR   0x31

#define X313_LENS_AX(x)   ( 0x0 | ((x)& 0x7ffff))

#define X313_LENS_AY(x)   ( 0x80000 | ((x)& 0x7ffff))

#define X313_LENS_C(x)   (0x100000 | ((x)& 0x7ffff))

#define X313_LENS_BX(x)   (0x200000 | ((x)& 0x1fffff))

#define X313_LENS_BY(x)   (0x400000 | ((x)& 0x1fffff))

#define X313_LENS_SCALES(color, x)   (0x600000 | (((color)&3)<<17) | ((x)& 0x1ffff))

#define X313_LENS_FATZERO_IN(x)   (0x680000 | ((x)& 0xffff))

#define X313_LENS_FATZERO_OUT(x)   (0x690000 | ((x)& 0xffff))

#define X313_LENS_POSTSCALE(x)   (0x6a0000 | ((x)& 0x7))

#define RD_SD_PIOWIN   port_csp4_addr[X313_WA_SD_PIOWIN]

#define X313_PREINIT_SDCHAN(num, mode, wnr, dep, sa, ntilex, ntiley)

Old style memory channel programming.

#define X313_POSTINIT_SDCHAN(num, cmd)   {port_csp0_addr[X313_WA_SDCH0_CTL0+0+((num)<<2)] = cmd; X3X3_AFTERWRITE}

#define X313_INIT_SDCHAN(num, mode, wnr, dep, sa, ntilex, ntiley)   {X313_POSTINIT_SDCHAN ( num, X313_PREINIT_SDCHAN ( num,mode,wnr,dep,sa,ntilex,ntiley ))}

#define X313_SDCHAN_REG0(mode, wnr, dep, sa, ntilex, ntiley)   ((((mode) & 1) << 15) | (((wnr) & 1) << 14) | (((dep) & 1) << 13) | (((sa) >> 8) & 0x1fff))

data to be programmed to the memory registers through the sequencer (all arguments are the same, not all are used for all registers)

#define X313_SDCHAN_REG1(mode, wnr, dep, sa, ntilex, ntiley)   (0x8000 | (((ntilex) & 0x3ff) << 4) | (((sa) >> 21) & 0xf))

#define X313_SDCHAN_REG2(mode, wnr, dep, sa, ntilex, ntiley)   ((ntiley) & 0xfff)

#define X313_CHN_EN_D(x)   ((0x30 << (((x)& 3)<<1)) | 0xf)

mode=1, wnr=1 - photofinish

#define X313_CHN_DIS_D(x)   (0x20 << (((x)& 3)<<1))

#define X313_CHN_DISALL_D   0xaa0

#define X313_SDRAM_OFF_D   0xaaa

#define X313_SDRAM_ON_D   0xaaf

#define X313_CHN_EN(x)   {X3X3_AFTERWRITE ; port_csp0_addr[X313_WA_SD_MODE] = X313_CHN_EN_D(x); }

#define X313_CHN_DIS(x)   {X3X3_AFTERWRITE ; port_csp0_addr[X313_WA_SD_MODE] = X313_CHN_DIS_D(x); }

#define X313_CHN_DISALL   {X3X3_AFTERWRITE ; port_csp0_addr[X313_WA_SD_MODE] = X313_CHN_DISALL_D ; }

#define X313_SDRAM_OFF   {port_csp0_addr[X313_WA_SD_MODE]= X313_SDRAM_OFF_D;}

#define X313_SDRAM_ON   {port_csp0_addr[X313_WA_SD_MODE]= X313_SDRAM_ON_D;}

#define X313_IS_SDRAM_ON   (port_csp0_addr[X313_WA_SD_MODE],((port_csp0_addr[X313_WA_SD_MODE] & 3)==3))

#define X313_CHN0_BOUND   (port_csp0_addr[X313_WA_SDCH2_CTL0],(port_csp0_addr[X313_WA_SDCH2_CTL0] & 0x2000))

#define X313_XFERCNTR   (port_csp0_addr[X313__RA__XFERCNTR],port_csp0_addr[X313__RA__XFERCNTR])

#define X313_HIGHFREQ   (port_csp0_addr[X313__RA__HIGHFREQ],port_csp0_addr[X313__RA__HIGHFREQ])

#define X313_IRQSTATE   (port_csp0_addr[0x11],port_csp0_addr[0x11])

#define X313_IOPINS   (port_csp0_addr[X313__RA__IOPINS],port_csp0_addr[X313__RA__IOPINS])

#define X313_CHN0_USED

X313_WA_SDCH0_CTL2 bits 12..15 are coming from dynamic register and do not depend on the written data.

#define X313_CHN0_SET_USED   { port_csp0_addr[X313_WA_SDCH0_CTL1]=0x8000; }

#define X313_CHN0_SET_UNUSED   { port_csp0_addr[X313_WA_SDCH0_CTL1]=0; }

#define X313_SET_FPGA_TIME(x, y)   { port_csp0_addr[X313_WA_RTC_USEC]= ( y ); port_csp0_addr[X313_WA_RTC_SEC]= ( x ); }

#define X313_GET_FPGA_TIME(x, y)   { port_csp0_addr[X313_WA_RTC_LATCH]= 0; X3X3_AFTERWRITE ; x = port_csp0_addr[X313_WA_RTC_SEC]; y = port_csp0_addr[X313_WA_RTC_USEC];}

#define X313_GET_FPGA_SECONDS(x)   { port_csp0_addr[X313_WA_RTC_LATCH]= 0; X3X3_AFTERWRITE ; x = port_csp0_addr[X313_WA_RTC_SEC]}

#define X313_MAP_FPN   0

#define X313_SDRAM_SIZE   0x4000000

#define X313_MAXWIDTH   4096

#define X313_MAXHEIGHT   4096

#define X313_MAP_FRAME   ((X313_MAP_FPN) + (X313_MAXWIDTH) * (X313_MAXHEIGHT))

#define X313_MARGINS   4

#define X313_TILEHOR   16

#define X313_TILEVERT   16

Define Documentation

#define CCAM_ARO_OFF port_csp0_addr[X313_WA_DCR0]=X353_DCR0(ARO,0)

Definition at line 391 of file x353.h.

#define CCAM_ARO_ON port_csp0_addr[X313_WA_DCR0]=X353_DCR0(ARO,1)

Macros that replace old ones for the control register in cc313.h these macros write directly, bypassing the sequencer For sequencer (preferred way in most cases) - use something like X3X3_SEQ_SEND1(fpga_addr, X313_WA_DCR0, X353_DCR0(SENSTRIGEN,async);

Definition at line 390 of file x353.h.

#define CCAM_ARST_OFF port_csp0_addr[X313_WA_DCR0]=X353_DCR0(ARST,1)

Definition at line 395 of file x353.h.

Referenced by mt9x001_pgm_detectsensor(), and pgm_detectsensor().

#define CCAM_ARST_ON port_csp0_addr[X313_WA_DCR0]=X353_DCR0(ARST,0)

Definition at line 396 of file x353.h.

#define CCAM_CNVEN_OFF port_csp0_addr[X313_WA_DCR0]=X353_DCR0(CNVEN,0)

Definition at line 403 of file x353.h.

Referenced by pgm_detectsensor().

#define CCAM_CNVEN_ON port_csp0_addr[X313_WA_DCR0]=X353_DCR0(CNVEN,1)

enable power converter control. *** Only if it is not MT9P001 !!! ***

Definition at line 402 of file x353.h.

Referenced by pgm_detectsensor().

#define CCAM_DCLK_OFF port_csp0_addr[X313_WA_DCR1]=X353_DCR1(DCLKMODE,1)

turn clock to sensor on/off (default - on)

Definition at line 393 of file x353.h.

#define CCAM_DCLK_ON port_csp0_addr[X313_WA_DCR1]=X353_DCR1(DCLKMODE,0)

Definition at line 394 of file x353.h.

Referenced by pgm_detectsensor().

#define CCAM_MRST_OFF port_csp0_addr[X313_WA_DCR1]=X353_DCR1(MRST,1)

Definition at line 397 of file x353.h.

Referenced by mt9x001_pgm_detectsensor(), mt9x001_pgm_initsensor(), and pgm_detectsensor().

#define CCAM_MRST_ON port_csp0_addr[X313_WA_DCR1]=X353_DCR1(MRST,0)

Definition at line 398 of file x353.h.

Referenced by mt9x001_pgm_initsensor(), and pgm_detectsensor().

#define CCAM_NEGRST port_csp0_addr[X313_WA_DCR0]=X353_DCR0(NEGRST,1)

Definition at line 399 of file x353.h.

Referenced by mt9x001_pgm_detectsensor(), and pgm_detectsensor().

#define CCAM_POSRST port_csp0_addr[X313_WA_DCR0]=X353_DCR0(NEGRST,0)

Definition at line 400 of file x353.h.

Referenced by pgm_detectsensor().

#define CCAM_SET_HACT_PHASE ( x ) port_csp0_addr[X313_WA_DCR1]=X353_DCR1(HACT_PHASE,(x))

Set HACT phase (90 degrees increments - needed for MT9P001.

Definition at line 411 of file x353.h.

Referenced by pgm_sensorphase().

#define CCAM_TIMESTAMP_EARLY port_csp0_addr[X313_WA_DCR1]=X353_DCR1(EARLYTRIG,1)

Definition at line 409 of file x353.h.

#define CCAM_TIMESTAMP_NORMAL port_csp0_addr[X313_WA_DCR1]=X353_DCR1(EARLYTRIG,0)

early/normal timestamp in async mode

Definition at line 408 of file x353.h.

Referenced by pgm_detectsensor().

#define CCAM_TRIG_EXT port_csp0_addr[X313_WA_DCR0]=X353_DCR0(SENSTRIGEN,1)

Definition at line 406 of file x353.h.

#define CCAM_TRIG_INT port_csp0_addr[X313_WA_DCR0]=X353_DCR0(SENSTRIGEN,0)

Sensor (MT9X001) trigger source selection (internal/external).

Definition at line 405 of file x353.h.

Referenced by mt9x001_pgm_detectsensor(), and pgm_detectsensor().

#define CCAM_VSYNC_OFF port_csp0_addr[X313_WA_DCR1]=X353_DCR1(BLOCKVSYNC,1)

Definition at line 418 of file x353.h.

#define CCAM_VSYNC_ON port_csp0_addr[X313_WA_DCR1]=X353_DCR1(BLOCKVSYNC,0)

disable (CCAM_VSYNC_OFF) and enable (CCAM_VSYNC_ON) sensor vertical sync pulses to i2c and command sequencer to prevent their mismatch (it also disable "smart" interrupts so before enabling (from reset state) these two sequencer - disable vsync and reenable it after both sequencers are enabled

Definition at line 417 of file x353.h.

#define COMPCMD_BAYERSHIFT ( x ) ((1<<20) | (((x) & 3) << 18))

Definition at line 217 of file x353.h.

Referenced by pgm_compmode().

#define COMPCMD_DCSUB ( x ) ((1<<8) | (((x) & 1) << 7))

Definition at line 263 of file x353.h.

Referenced by pgm_compmode().

#define COMPCMD_DEMOS ( x ) ((1<<13) | (((x) & 0x0f) << 9))

Definition at line 243 of file x353.h.

Referenced by pgm_compmode().

#define COMPCMD_FOCUS ( x ) ((1<<23) | (((x) & 3) << 21))

Definition at line 213 of file x353.h.

Referenced by pgm_compmode().

#define COMPCMD_QTAB ( x ) ((1<<6) | (((x) & 7) << 3))

Definition at line 268 of file x353.h.

Referenced by pgm_quality().

#define COMPCMD_RESET 4

Definition at line 271 of file x353.h.

Referenced by reset_compressor().

#define COMPCMD_RUN 7

Definition at line 274 of file x353.h.

Referenced by pgm_compctl(), and pgm_comprestart().

#define COMPCMD_SINGLE 6

Definition at line 273 of file x353.h.

Referenced by pgm_compctl(), and pgm_comprestart().

#define COMPCMD_STOP 5

Definition at line 272 of file x353.h.

Referenced by pgm_compctl(), and pgm_compstop().

#define COMPCMD_TILESHIFT ( x ) ((1<<17) | (((x) & 7) << 14))

Definition at line 225 of file x353.h.

Referenced by pgm_compmode().

#define DEFAULT_COLOR_SATURATION_BLUE 0x90

Definition at line 200 of file x353.h.

Referenced by pgm_compmode().

#define DEFAULT_COLOR_SATURATION_RED 0xb6

Definition at line 201 of file x353.h.

Referenced by pgm_compmode().

#define DEMOS_COLOR18 1

Definition at line 246 of file x353.h.

Referenced by pgm_compmode().

#define DEMOS_COLOR20 4

Definition at line 249 of file x353.h.

Referenced by pgm_compmode().

#define DEMOS_JP4 5

Definition at line 251 of file x353.h.

Referenced by pgm_compmode().

#define DEMOS_JP46 2

Definition at line 247 of file x353.h.

Referenced by pgm_compmode().

#define DEMOS_JP46DC 3

Definition at line 248 of file x353.h.

Referenced by pgm_compmode().

#define DEMOS_JP4DC 6

Definition at line 252 of file x353.h.

Referenced by pgm_compmode().

#define DEMOS_JP4DIFF 7

Definition at line 253 of file x353.h.

Referenced by pgm_compmode().

#define DEMOS_JP4DIFF2 9

Definition at line 256 of file x353.h.

Referenced by pgm_compmode().

#define DEMOS_JP4HDR 8

Definition at line 254 of file x353.h.

Referenced by pgm_compmode().

#define DEMOS_JP4HDR2 10

Definition at line 258 of file x353.h.

Referenced by pgm_compmode().

#define DEMOS_MONO4 14

Definition at line 259 of file x353.h.

Referenced by pgm_compmode().

#define DEMOS_MONO6 0

Definition at line 245 of file x353.h.

Referenced by pgm_compmode().

#define DIS_INTERRUPT ( x ) {port_csp0_addr[X313_WA_IRQ_DIS]= (1<< ( X313_IR__##x ) ); port_csp0_addr[X313_WA_IRQ_RST]= (1<< ( X313_IR__##x ) );}

Definition at line 296 of file x353.h.

#define DIS_INTERRUPT ( x ) {port_csp0_addr[X313_WA_IRQ_DIS]= (1<< ( X313_IR__##x ) ); port_csp0_addr[X313_WA_IRQ_RST]= (1<< ( X313_IR__##x ) );}

Definition at line 296 of file x353.h.

#define DIS_INTERRUPTS {port_csp0_addr[X313_WA_IRQ_DIS]= 0xffff; port_csp0_addr[X313_WA_IRQ_RST]= 0xffff;}

Definition at line 297 of file x353.h.

#define DIS_INTERRUPTS {port_csp0_addr[X313_WA_IRQ_DIS]= 0xffff; port_csp0_addr[X313_WA_IRQ_RST]= 0xffff;}

Definition at line 297 of file x353.h.

Referenced by camera_interrupts(), and elphel_FPGA_interrupt().

#define EN_INTERRUPT ( x ) port_csp0_addr[X313_WA_IRQ_ENA]= (1<< ( X313_IR__##x ))

Definition at line 295 of file x353.h.

#define EN_INTERRUPT ( x ) port_csp0_addr[X313_WA_IRQ_ENA]= (1<< ( X313_IR__##x ))

Definition at line 295 of file x353.h.

Referenced by camera_interrupts(), and elphel_FPGA_interrupt().

#define FPGA_NQTAB 8

Definition at line 269 of file x353.h.

Referenced by init_qtable_fpga(), and set_qtable_fpga().

#define I2C_FRAME_NUMBER 0x16

Definition at line 26 of file x353.h.

#define RD_SD_PIOWIN port_csp4_addr[X313_WA_SD_PIOWIN]

******************************************************************************************************* ! Moved all references to FPGA access to memory-control registers here to simplify code maitenance ! when FPGA changes. ! ! Split SDARM channel initailization in 3 macros ! X313_PREINIT_SDCHAN(num,mode,wnr,dep,sa,ntilex,ntiley) - writes two (of 3) registers (not yet starting the channel) ! returns value foo the 3-rd (command) register ! X313_PREINIT_SDCHAN(num,cmd) - writes the channel command register, starting it ! waits 2 cycles after (if ETRAX FS) to make next reads safe ! X313_INIT_SDCHAN(num,mode,wnr,dep,sa,ntilex,ntiley) - combination of the 2 above, works as before ! !/ added X3X3_AFTERWRITE to be able to read FPGA after that macro (w/o -= failed in ETRAX FS)

Definition at line 940 of file x353.h.

Referenced by x353raw_fpn_readline(), and x353raw_frame_readline().

#define SFPGA_PGMEN_BIT 0x8

Definition at line 538 of file x353.h.

Referenced by set_pgm_mode().

#define SFPGA_PROG_BIT 0x6

Definition at line 537 of file x353.h.

Referenced by set_pgm().

#define SFPGA_RD_BIT 16

Definition at line 25 of file x353.h.

Referenced by jtag_send(), jtag_write_bits(), and read_done().

#define SFPGA_RD_DONE 0xa0000

Definition at line 541 of file x353.h.

Referenced by read_done().

#define SFPGA_RD_SENSPGMPIN 0x80000

Definition at line 539 of file x353.h.

Referenced by set_pgm_mode().

#define SFPGA_RD_TDO 0x90000

Definition at line 540 of file x353.h.

Referenced by jtag_send(), and jtag_write_bits().

#define SFPGA_TCK_BIT 0x4

Definition at line 536 of file x353.h.

Referenced by jtag_send(), jtag_write_bits(), and set_pgm_mode().

#define SFPGA_TDI_BIT 0x0

Definition at line 534 of file x353.h.

Referenced by jtag_send(), and jtag_write_bits().

#define SFPGA_TMS_BIT 0x2

Definition at line 535 of file x353.h.

Referenced by jtag_send(), and jtag_write_bits().

#define X313__RA__HIGHFREQ 0x15

Definition at line 13 of file x353.h.

#define X313__RA__IOPINS 0x70

Definition at line 17 of file x353.h.

#define X313__RA__IRQS 0x11

Definition at line 7 of file x353.h.

#define X313__RA__MODEL 0x13

Definition at line 9 of file x353.h.

Referenced by fpga_jtag_release(), and init_FPGA().

#define X313__RA__SDBUF3 0x30

Definition at line 33 of file x353.h.

#define X313__RA__SDCH0 0x20

Definition at line 29 of file x353.h.

#define X313__RA__SDCH1 0x24

Definition at line 30 of file x353.h.

#define X313__RA__SDCH2 0x28

Definition at line 31 of file x353.h.

#define X313__RA__SDCH3 0x2c

Definition at line 32 of file x353.h.

#define X313__RA__SENSFPGA 0x74

Definition at line 24 of file x353.h.

Referenced by read_done().

#define X313__RA__STATUS 0x10

Definition at line 6 of file x353.h.

#define X313__RA__TABLE 0x14

Definition at line 10 of file x353.h.

#define X313__RA__TRIGPH 0x12

Definition at line 8 of file x353.h.

#define X313__RA__XFERCNTR 0x14

Definition at line 12 of file x353.h.

#define X313_CHN0_BOUND (port_csp0_addr[X313_WA_SDCH2_CTL0],(port_csp0_addr[X313_WA_SDCH2_CTL0] & 0x2000))

Definition at line 971 of file x353.h.

#define X313_CHN0_SET_UNUSED { port_csp0_addr[X313_WA_SDCH0_CTL1]=0; }

Definition at line 983 of file x353.h.

#define X313_CHN0_SET_USED { port_csp0_addr[X313_WA_SDCH0_CTL1]=0x8000; }

Definition at line 982 of file x353.h.

#define X313_CHN0_USED

Value:

( (port_csp0_addr[X313_WA_SDCH0_CTL1]& 0xffff), \
                          (port_csp0_addr[X313_WA_SDCH0_CTL1] & 0xffff) )

X313_WA_SDCH0_CTL2 bits 12..15 are coming from dynamic register and do not depend on the written data.

Definition at line 979 of file x353.h.

Referenced by init_FPGA().

#define X313_CHN_DIS ( x ) {X3X3_AFTERWRITE ; port_csp0_addr[X313_WA_SD_MODE] = X313_CHN_DIS_D(x); }

Definition at line 965 of file x353.h.

Referenced by read_page_to_buffer().

#define X313_CHN_DIS_D ( x ) (0x20 << (((x)& 3)<<1))

Definition at line 959 of file x353.h.

Referenced by pgm_memsensor().

#define X313_CHN_DISALL {X3X3_AFTERWRITE ; port_csp0_addr[X313_WA_SD_MODE] = X313_CHN_DISALL_D ; }

Definition at line 966 of file x353.h.

#define X313_CHN_DISALL_D 0xaa0

Definition at line 960 of file x353.h.

#define X313_CHN_EN ( x ) {X3X3_AFTERWRITE ; port_csp0_addr[X313_WA_SD_MODE] = X313_CHN_EN_D(x); }

Definition at line 964 of file x353.h.

Referenced by fsdram_read(), fsdram_write(), read_page_to_buffer(), x353raw_fpn_readline(), x353raw_fpn_writeline(), x353raw_frame_readline(), and x353raw_frame_writeline().

#define X313_CHN_EN_D ( x ) ((0x30 << (((x)& 3)<<1)) | 0xf)

mode=1, wnr=1 - photofinish

Definition at line 958 of file x353.h.

Referenced by pgm_compctl(), pgm_comprestart(), and pgm_memsensor().

#define X313_GET_FPGA_SECONDS ( x ) { port_csp0_addr[X313_WA_RTC_LATCH]= 0; X3X3_AFTERWRITE ; x = port_csp0_addr[X313_WA_RTC_SEC]}

Definition at line 988 of file x353.h.

#define X313_GET_FPGA_TIME	(	x,
		y		)	{ port_csp0_addr[X313_WA_RTC_LATCH]= 0; X3X3_AFTERWRITE ; x = port_csp0_addr[X313_WA_RTC_SEC]; y = port_csp0_addr[X313_WA_RTC_USEC];}

Definition at line 987 of file x353.h.

Referenced by framepars_lseek(), framepars_write(), and stream__ioctl().

#define X313_HIGHFREQ (port_csp0_addr[X313__RA__HIGHFREQ],port_csp0_addr[X313__RA__HIGHFREQ])

Definition at line 974 of file x353.h.

Referenced by updateIRQFocus().

#define X313_I2C_ASAP 0x58

Definition at line 443 of file x353.h.

Referenced by mt9x001_pgm_exposure(), mt9x001_pgm_gains(), mt9x001_pgm_initsensor(), mt9x001_pgm_limitfps(), mt9x001_pgm_sensorregs(), mt9x001_pgm_triggermode(), and mt9x001_pgm_window_common().

#define X313_I2C_CMD 0x5f

Definition at line 450 of file x353.h.

Referenced by i2c_scl_0(), i2c_scl_1(), i2c_sda_strong(), i2c_sda_weak(), and pgm_i2c().

#define X313_I2C_FRAME0 0x50

=============================

Definition at line 435 of file x353.h.

Referenced by mt9x001_pgm_exposure(), mt9x001_pgm_gains(), mt9x001_pgm_initsensor(), mt9x001_pgm_limitfps(), mt9x001_pgm_sensorregs(), mt9x001_pgm_triggermode(), and mt9x001_pgm_window_common().

#define X313_I2C_FRAME1 0x51

Definition at line 436 of file x353.h.

#define X313_I2C_FRAME2 0x52

Definition at line 437 of file x353.h.

#define X313_I2C_FRAME3 0x53

Definition at line 438 of file x353.h.

#define X313_I2C_FRAME4 0x54

Definition at line 439 of file x353.h.

#define X313_I2C_FRAME5 0x55

Definition at line 440 of file x353.h.

#define X313_I2C_FRAME6 0x56

Definition at line 441 of file x353.h.

#define X313_I2C_FRAME7 0x57

Definition at line 442 of file x353.h.

#define X313_I2C_NEXT 0x59

Definition at line 444 of file x353.h.

#define X313_I2C_NEXT2 0x5a

Definition at line 445 of file x353.h.

#define X313_I2C_NEXT3 0x5b

Definition at line 446 of file x353.h.

#define X313_I2C_NEXT4 0x5c

Definition at line 447 of file x353.h.

#define X313_I2C_NEXT5 0x5d

Definition at line 448 of file x353.h.

#define X313_I2C_NEXT6 0x5e

Definition at line 449 of file x353.h.

#define X313_INIT_SDCHAN	(	num,
		mode,
		wnr,
		dep,
		sa,
		ntilex,
		ntiley	)	{X313_POSTINIT_SDCHAN ( num, X313_PREINIT_SDCHAN ( num,mode,wnr,dep,sa,ntilex,ntiley ))}

Definition at line 948 of file x353.h.

Referenced by fsdram_read(), fsdram_write(), read_page_to_buffer(), x353raw_fpn_readline(), x353raw_fpn_writeline(), x353raw_frame_readline(), and x353raw_frame_writeline().

#define X313_IOPINS (port_csp0_addr[X313__RA__IOPINS],port_csp0_addr[X313__RA__IOPINS])

Definition at line 976 of file x353.h.

#define X313_IR ( x ) ((port_csp0_addr[X313__RA__IRQS] >> ( X313_IR__##x ) + 8) & 1)

Definition at line 112 of file x353.h.

#define X313_IR__DCC 5

Definition at line 106 of file x353.h.

#define X313_IR__DONE 3

Definition at line 104 of file x353.h.

#define X313_IR__DONE_COMPRESS 7

Definition at line 109 of file x353.h.

#define X313_IR__DONE_INPUT 6

Definition at line 108 of file x353.h.

#define X313_IR__EOT 4

Definition at line 105 of file x353.h.

#define X313_IR__SMART 8

Definition at line 110 of file x353.h.

#define X313_IR__VACT 0

Definition at line 101 of file x353.h.

#define X313_IR__XFEROVR 2

Definition at line 103 of file x353.h.

#define X313_IR__XINT 1

Definition at line 102 of file x353.h.

#define X313_IRQSTATE (port_csp0_addr[0x11],port_csp0_addr[0x11])

Definition at line 975 of file x353.h.

Referenced by elphel_FPGA_interrupt().

#define X313_IS_SDRAM_ON (port_csp0_addr[X313_WA_SD_MODE],((port_csp0_addr[X313_WA_SD_MODE] & 3)==3))

Definition at line 970 of file x353.h.

Referenced by fpga_open(), fsdram_open(), fsdram_read(), fsdram_write(), and init_FPGA().

#define X313_LENS_AX ( x ) ( 0x0 | ((x)& 0x7ffff))

Definition at line 915 of file x353.h.

Referenced by pgm_prescal().

#define X313_LENS_AY ( x ) ( 0x80000 | ((x)& 0x7ffff))

Definition at line 916 of file x353.h.

Referenced by pgm_prescal().

#define X313_LENS_BX ( x ) (0x200000 | ((x)& 0x1fffff))

Definition at line 918 of file x353.h.

Referenced by pgm_prescal().

#define X313_LENS_BY ( x ) (0x400000 | ((x)& 0x1fffff))

Definition at line 919 of file x353.h.

Referenced by pgm_prescal().

#define X313_LENS_C ( x ) (0x100000 | ((x)& 0x7ffff))

Definition at line 917 of file x353.h.

Referenced by pgm_prescal().

#define X313_LENS_FATZERO_IN ( x ) (0x680000 | ((x)& 0xffff))

Definition at line 921 of file x353.h.

Referenced by pgm_prescal().

#define X313_LENS_FATZERO_OUT ( x ) (0x690000 | ((x)& 0xffff))

Definition at line 922 of file x353.h.

Referenced by pgm_prescal().

#define X313_LENS_POSTSCALE ( x ) (0x6a0000 | ((x)& 0x7))

Definition at line 923 of file x353.h.

Referenced by pgm_prescal().

#define X313_LENS_SCALES	(	color,
		x		)	(0x600000 \| (((color)&3)<<17) \| ((x)& 0x1ffff))

Definition at line 920 of file x353.h.

Referenced by pgm_prescal().

#define X313_MAP_FPN 0

Definition at line 994 of file x353.h.

Referenced by pgm_memsensor(), x353raw_fpn_readline(), and x353raw_fpn_writeline().

#define X313_MAP_FRAME ((X313_MAP_FPN) + (X313_MAXWIDTH) * (X313_MAXHEIGHT))

Definition at line 998 of file x353.h.

Referenced by pgm_memcompressor(), pgm_memsensor(), x353raw_frame_readline(), and x353raw_frame_writeline().

#define X313_MARGINS 4

Definition at line 999 of file x353.h.

Referenced by mt9x001_pgm_window_common(), pgm_memcompressor(), pgm_memsensor(), pgm_sensorin(), and pgm_window_common().

#define X313_MAXHEIGHT 4096

Definition at line 997 of file x353.h.

Referenced by pgm_window_common().

#define X313_MAXMODREV 0x035340ff

Definition at line 4 of file x353.h.

Referenced by init_FPGA().

#define X313_MAXWIDTH 4096

Definition at line 996 of file x353.h.

#define X313_MINMODREV 0x03534000

Definition at line 3 of file x353.h.

Referenced by init_FPGA().

#define X313_PIOR ( x ) ((port_csp0_addr[X313__RA__IOPINS] >> X313_PIOR__##x ) & 1)

Definition at line 98 of file x353.h.

Referenced by i2c_getbit(), and i2c_getscl().

#define X313_PIOR__AUXCLK 3

Definition at line 86 of file x353.h.

#define X313_PIOR__EXPS 4

Definition at line 87 of file x353.h.

#define X313_PIOR__SCL1 0

Definition at line 83 of file x353.h.

#define X313_PIOR__SDA1 1

Definition at line 84 of file x353.h.

#define X313_PIOR__TRIG 5

Definition at line 88 of file x353.h.

#define X313_PIOR__XRST 2

Definition at line 85 of file x353.h.

#define X313_POSTINIT_SDCHAN	(	num,
		cmd		)	{port_csp0_addr[X313_WA_SDCH0_CTL0+0+((num)<<2)] = cmd; X3X3_AFTERWRITE}

Definition at line 947 of file x353.h.

#define X313_PREINIT_SDCHAN	(	num,
		mode,
		wnr,
		dep,
		sa,
		ntilex,
		ntiley	)

Value:

((port_csp0_addr[X313_WA_SDCH0_CTL0+1+((num)<<2)] = (0x8000 | (((ntilex) & 0x3ff) << 4) | (((sa) >> 21) & 0xf))), \
           (port_csp0_addr[X313_WA_SDCH0_CTL0+2+((num)<<2)] =            ((ntiley) & 0xfff)), \
           (((mode) & 1) << 15) | (((wnr) & 1) << 14) | (((dep) & 1) << 13) | (((sa) >> 8) & 0x1fff))

Old style memory channel programming.

Definition at line 943 of file x353.h.

#define X313_RA_HIST_DATA 0x45

Definition at line 306 of file x353.h.

Referenced by fpga_hist_read_nice().

#define X313_RA_RTC_SEC 0x49

Definition at line 313 of file x353.h.

Referenced by ext353__ioctl().

#define X313_RA_RTC_USEC 0x48

Definition at line 312 of file x353.h.

Referenced by ext353__ioctl().

#define X313_SDCHAN_REG0	(	mode,
		wnr,
		dep,
		sa,
		ntilex,
		ntiley	)	((((mode) & 1) << 15) \| (((wnr) & 1) << 14) \| (((dep) & 1) << 13) \| (((sa) >> 8) & 0x1fff))

data to be programmed to the memory registers through the sequencer (all arguments are the same, not all are used for all registers)

Definition at line 952 of file x353.h.

Referenced by pgm_memcompressor(), and pgm_memsensor().

#define X313_SDCHAN_REG1	(	mode,
		wnr,
		dep,
		sa,
		ntilex,
		ntiley	)	(0x8000 \| (((ntilex) & 0x3ff) << 4) \| (((sa) >> 21) & 0xf))

Definition at line 953 of file x353.h.

Referenced by pgm_memcompressor(), and pgm_memsensor().

#define X313_SDCHAN_REG2	(	mode,
		wnr,
		dep,
		sa,
		ntilex,
		ntiley	)	((ntiley) & 0xfff)

Definition at line 954 of file x353.h.

Referenced by pgm_memcompressor(), and pgm_memsensor().

#define X313_SDRAM_OFF {port_csp0_addr[X313_WA_SD_MODE]= X313_SDRAM_OFF_D;}

Definition at line 967 of file x353.h.

Referenced by fpga_initSDRAM(), and fpga_resetSDRAM().

#define X313_SDRAM_OFF_D 0xaaa

Definition at line 961 of file x353.h.

#define X313_SDRAM_ON {port_csp0_addr[X313_WA_SD_MODE]= X313_SDRAM_ON_D;}

Definition at line 968 of file x353.h.

Referenced by fpga_initSDRAM().

#define X313_SDRAM_ON_D 0xaaf

Definition at line 962 of file x353.h.

#define X313_SDRAM_SIZE 0x4000000

Definition at line 995 of file x353.h.

Referenced by fsdram_lseek(), fsdram_open(), fsdram_read(), and fsdram_write().

#define X313_SENSFPN_D	(	t,
		s,
		m,
		d,
		l	)

Value:

(((t) & 1) << 10) | \
                                        (((s) & 7) << 7) | \
                                        (((m) & 7) << 4) | \
                                        (((d) & 1) << 3) | \
                                        (((l) & 7) << 0)

Definition at line 153 of file x353.h.

Referenced by pgm_sensorin().

#define X313_SENSOR_PHASE ((port_csp0_addr[X313__RA__STATUS] >> X313_SR__SENS_DCM_LATE ) & 3)

Definition at line 47 of file x353.h.

#define X313_SEQ_ASAP 0x68

Definition at line 489 of file x353.h.

Referenced by pgm_compctl(), pgm_compmode(), pgm_comprestart(), pgm_compstop(), pgm_hist(), pgm_i2c(), pgm_irq(), pgm_memsensor(), pgm_prescal(), pgm_quality(), pgm_sensorin(), pgm_sensorrun(), pgm_sensorstop(), and pgm_triggermode().

#define X313_SEQ_CMD 0x6f

Definition at line 496 of file x353.h.

#define X313_SEQ_FRAME0 0x60

Definition at line 481 of file x353.h.

#define X313_SEQ_FRAME1 0x61

Definition at line 482 of file x353.h.

#define X313_SEQ_FRAME2 0x62

Definition at line 483 of file x353.h.

#define X313_SEQ_FRAME3 0x63

Definition at line 484 of file x353.h.

#define X313_SEQ_FRAME4 0x64

Definition at line 485 of file x353.h.

#define X313_SEQ_FRAME5 0x65

Definition at line 486 of file x353.h.

#define X313_SEQ_FRAME6 0x66

Definition at line 487 of file x353.h.

#define X313_SEQ_FRAME7 0x67

Definition at line 488 of file x353.h.

#define X313_SEQ_NEXT 0x69

Definition at line 490 of file x353.h.

#define X313_SEQ_NEXT2 0x6a

Definition at line 491 of file x353.h.

#define X313_SEQ_NEXT3 0x6b

Definition at line 492 of file x353.h.

#define X313_SEQ_NEXT4 0x6c

Definition at line 493 of file x353.h.

#define X313_SEQ_NEXT5 0x6d

Definition at line 494 of file x353.h.

#define X313_SEQ_NEXT6 0x6e

Definition at line 495 of file x353.h.

#define X313_SET_FPGA_TIME	(	x,
		y		)	{ port_csp0_addr[X313_WA_RTC_USEC]= ( y ); port_csp0_addr[X313_WA_RTC_SEC]= ( x ); }

Definition at line 986 of file x353.h.

Referenced by framepars_lseek(), and framepars_write().

#define X313_SR ( x ) ((port_csp0_addr[X313__RA__STATUS] >> X313_SR__##x ) & 1)

Definition at line 97 of file x353.h.

Referenced by fsdram_read(), fsdram_write(), i2c_getbit(), i2c_getscl(), read_page_to_buffer(), x353raw_fpn_readline(), x353raw_fpn_writeline(), x353raw_frame_readline(), and x353raw_frame_writeline().

#define X313_SR__CH0RDY 2

Definition at line 77 of file x353.h.

#define X313_SR__CH1RDY 3

Definition at line 76 of file x353.h.

#define X313_SR__CH2RDY 4

Definition at line 75 of file x353.h.

#define X313_SR__CLK_LOCKED 28

Definition at line 35 of file x353.h.

#define X313_SR__DCCRDY 14

Definition at line 60 of file x353.h.

#define X313_SR__DCM_EARLY 19

Definition at line 53 of file x353.h.

#define X313_SR__DCM_LATE 18

Definition at line 54 of file x353.h.

#define X313_SR__DCM_LOCKED 21

Definition at line 51 of file x353.h.

#define X313_SR__DCM_OVFL 22

Definition at line 50 of file x353.h.

#define X313_SR__DCM_RDY 20

Definition at line 52 of file x353.h.

#define X313_SR__DMA_EMPTY 17

Definition at line 57 of file x353.h.

#define X313_SR__DONE 13

Definition at line 62 of file x353.h.

#define X313_SR__DONE_CI 15

Definition at line 59 of file x353.h.

#define X313_SR__DONE_CMPRS 16

Definition at line 58 of file x353.h.

#define X313_SR__NXTFR0 7

Definition at line 72 of file x353.h.

#define X313_SR__NXTFR1 8

Definition at line 71 of file x353.h.

#define X313_SR__NXTFR2 9

Definition at line 70 of file x353.h.

#define X313_SR__NXTFR3 10

Definition at line 69 of file x353.h.

#define X313_SR__PIORDY 5

Definition at line 74 of file x353.h.

#define X313_SR__PIOWEMPTY 6

Definition at line 73 of file x353.h.

#define X313_SR__SCL0 1

Definition at line 80 of file x353.h.

#define X313_SR__SDA0 0

Definition at line 81 of file x353.h.

#define X313_SR__SENS_DCM_EARLY 24

Definition at line 40 of file x353.h.

#define X313_SR__SENS_DCM_ERROR 24

Definition at line 43 of file x353.h.

#define X313_SR__SENS_DCM_LATE 23

Definition at line 45 of file x353.h.

#define X313_SR__SENS_DCM_LATE 23

Definition at line 45 of file x353.h.

#define X313_SR__SENS_DCM_LOCKED 26

Definition at line 37 of file x353.h.

#define X313_SR__SENS_DCM_OVFL 27

Definition at line 36 of file x353.h.

#define X313_SR__SENS_DCM_RDY 25

Definition at line 38 of file x353.h.

#define X313_SR__SENST0 11

Definition at line 68 of file x353.h.

#define X313_SR__SENST1 12

Definition at line 67 of file x353.h.

#define X313_SR__X323_SI 0

Definition at line 93 of file x353.h.

#define X313_TILEHOR 16

Definition at line 1000 of file x353.h.

Referenced by pgm_window_common().

#define X313_TILEVERT 16

Definition at line 1001 of file x353.h.

Referenced by pgm_window_common().

#define X313_TIMESTAMPLEN 28

Definition at line 315 of file x353.h.

Referenced by pgm_window_common().

#define X313_WA_CAMSYNCDLY 0x79

Definition at line 531 of file x353.h.

Referenced by pgm_trigseq().

#define X313_WA_CAMSYNCOUT 0x7a

Definition at line 532 of file x353.h.

Referenced by pgm_trigseq().

#define X313_WA_CAMSYNCPER 0x7b

Definition at line 533 of file x353.h.

Referenced by pgm_trigseq().

#define X313_WA_CAMSYNCTRIG 0x78

Definition at line 530 of file x353.h.

Referenced by pgm_trigseq().

#define X313_WA_COLOR_SAT 9

Definition at line 198 of file x353.h.

Referenced by pgm_compmode().

#define X313_WA_COMP_CMD 0x0c

Definition at line 206 of file x353.h.

Referenced by pgm_compctl(), pgm_compmode(), pgm_comprestart(), pgm_compstop(), pgm_quality(), and reset_compressor().

#define X313_WA_COMP_TA 0x0e

Definition at line 282 of file x353.h.

Referenced by fpga_table_write_nice().

#define X313_WA_COMP_TD 0x0f

Definition at line 283 of file x353.h.

Referenced by fpga_table_write_nice().

#define X313_WA_DCDC 7

Definition at line 180 of file x353.h.

Referenced by pgm_detectsensor().

#define X313_WA_DCM 8

Definition at line 188 of file x353.h.

#define X313_WA_DCM_RST 0x1b

0xc - en/0x8 - dis waiting for DMA FIFO empty 0x8000 - reset circuitry

Definition at line 289 of file x353.h.

#define X313_WA_DCR0 0x4e

Definition at line 318 of file x353.h.

Referenced by pgm_sensorin(), and pgm_triggermode().

#define X313_WA_DCR1 0x4f

Definition at line 319 of file x353.h.

Referenced by pgm_triggermode().

#define X313_WA_DMACR 1

Definition at line 121 of file x353.h.

Referenced by x313_dma_start(), and x313_dma_stop().

#define X313_WA_FRAMESYNC_DLY 0x0a

Definition at line 203 of file x353.h.

#define X313_WA_HIST_ADDR 0x44

Definition at line 305 of file x353.h.

Referenced by fpga_hist_read_nice().

#define X313_WA_HIST_HEIGHT 0x43

Definition at line 304 of file x353.h.

Referenced by pgm_hist().

#define X313_WA_HIST_LEFT 0x40

Definition at line 301 of file x353.h.

Referenced by pgm_hist().

#define X313_WA_HIST_TOP 0x41

Definition at line 302 of file x353.h.

Referenced by pgm_hist().

#define X313_WA_HIST_WIDTH 0x42

Definition at line 303 of file x353.h.

Referenced by pgm_hist().

#define X313_WA_IOPINS 0x70

Definition at line 519 of file x353.h.

Referenced by i2c_scl_0(), i2c_scl_1(), i2c_sda_strong(), and i2c_sda_weak().

#define X313_WA_IRQ_DIS 0x1d

Definition at line 291 of file x353.h.

#define X313_WA_IRQ_ENA 0x1e

Definition at line 292 of file x353.h.

#define X313_WA_IRQ_RST 0x1c

Definition at line 290 of file x353.h.

#define X313_WA_IRQ_WVECT 0x1f

Definition at line 293 of file x353.h.

#define X313_WA_LENSCORR 0x31

Definition at line 913 of file x353.h.

Referenced by pgm_prescal().

#define X313_WA_MCUNUM 0x0d

Definition at line 284 of file x353.h.

Referenced by pgm_compctl(), and pgm_comprestart().

#define X313_WA_NLINES 5

Definition at line 169 of file x353.h.

Referenced by pgm_sensorin().

#define X313_WA_QUANTIZER_MODE 0x0b

Definition at line 204 of file x353.h.

Referenced by pgm_compmode().

#define X313_WA_RTC_CORR 0x4a

Definition at line 310 of file x353.h.

#define X313_WA_RTC_LATCH 0x4b

Definition at line 311 of file x353.h.

Referenced by ext353__ioctl().

#define X313_WA_RTC_SEC 0x49

Definition at line 309 of file x353.h.

#define X313_WA_RTC_USEC 0x48

Definition at line 308 of file x353.h.

#define X313_WA_SD_MANCMD 0x23

Definition at line 660 of file x353.h.

Referenced by fpga_initSDRAM().

#define X313_WA_SD_MODE 0x27

Definition at line 747 of file x353.h.

Referenced by pgm_compctl(), pgm_comprestart(), pgm_memsensor(), x353raw_fpn_readline(), x353raw_fpn_writeline(), x353raw_frame_readline(), and x353raw_frame_writeline().

#define X313_WA_SD_PIOWIN 0x30

Definition at line 911 of file x353.h.

Referenced by fsdram_read(), fsdram_write(), read_page_to_buffer(), x353raw_fpn_writeline(), and x353raw_frame_writeline().

#define X313_WA_SDCH0_CTL0 0x20

Definition at line 575 of file x353.h.

Referenced by pgm_memsensor().

#define X313_WA_SDCH0_CTL1 0x21

Definition at line 613 of file x353.h.

Referenced by pgm_memsensor().

#define X313_WA_SDCH0_CTL2 0x22

Definition at line 643 of file x353.h.

Referenced by pgm_memsensor().

#define X313_WA_SDCH1_CTL0 0x24

Definition at line 680 of file x353.h.

Referenced by pgm_memsensor().

#define X313_WA_SDCH1_CTL1 0x25

Definition at line 707 of file x353.h.

Referenced by pgm_memsensor().

#define X313_WA_SDCH1_CTL2 0x26

Definition at line 728 of file x353.h.

Referenced by pgm_memsensor().

#define X313_WA_SDCH2_CTL0 0x28

rev 0x03533022 - now 0x27 used 12-bit input, each internal bit is controlled by an input dibit (0x - don't change, 10 - reset, 11 - set) reading back 0x27 returns "old" data (non-masked enable bits) in 5:0, and masked (by other factors, like waiting for linked channel) in bits 11:6

Definition at line 769 of file x353.h.

Referenced by pgm_compctl(), and pgm_comprestart().

#define X313_WA_SDCH2_CTL1 0x29

Definition at line 800 of file x353.h.

Referenced by pgm_compctl(), and pgm_comprestart().

#define X313_WA_SDCH2_CTL2 0x2a

Definition at line 819 of file x353.h.

Referenced by pgm_compctl(), and pgm_comprestart().

#define X313_WA_SDCH3_CTL0 0x2c

Definition at line 836 of file x353.h.

#define X313_WA_SDCH3_CTL1 0x2d

Definition at line 865 of file x353.h.

#define X313_WA_SDCH3_CTL2 0x2e

Definition at line 886 of file x353.h.

#define X313_WA_SDPIO_NEXT 0x2f

Definition at line 903 of file x353.h.

Referenced by fsdram_read(), fsdram_write(), x353raw_fpn_readline(), x353raw_fpn_writeline(), x353raw_frame_readline(), and x353raw_frame_writeline().

#define X313_WA_SENSFPGA 0x74

Definition at line 529 of file x353.h.

Referenced by jtag_send(), jtag_write_bits(), read_done(), set_pgm(), and set_pgm_mode().

#define X313_WA_SENSFPN 2

Definition at line 126 of file x353.h.

Referenced by pgm_sensorin().

#define X313_WA_SMART_IRQ 0x1a

FIXME: (in FPGA) - now if "smart" mode is disabled, VACT will not cause interrupt on smart bit. So smart mode will be always enabled for now.

Definition at line 286 of file x353.h.

Referenced by camera_interrupts(), and pgm_irq().

#define X313_WA_TIMESTAMP 0x4c

Definition at line 314 of file x353.h.

#define X313_WA_TRIG 4

Definition at line 164 of file x353.h.

Referenced by pgm_sensorrun(), and pgm_sensorstop().

#define X313_WA_VIRTTRIG 3

Definition at line 159 of file x353.h.

#define X313_WA_WCTL 0

Definition at line 120 of file x353.h.

#define X313_WA_WCTL24 6

Definition at line 178 of file x353.h.

#define X313_XFERCNTR (port_csp0_addr[X313__RA__XFERCNTR],port_csp0_addr[X313__RA__XFERCNTR])

Definition at line 973 of file x353.h.

Referenced by updateIRQJPEG_wp().

#define X353_DCR0	(	x,
		y		)	(((((y) & ((1 << X353DCR0__##x##__WIDTH)-1))) \| (1 << X353DCR0__##x##__WIDTH) ) << X353DCR0__##x##__BITNM)

FPGA control bits/field can be modified without keeping shadow register, it is important when using "write only" sequencer, that just writes data at appropriate time, so CPU does not know the current shadow Tee following macro returnes data to be written to X313_WA_DCR0 or X313_WA_DCR1 (same register can be OR-ed) to change control bits for x to the value y

Definition at line 324 of file x353.h.

Referenced by pgm_sensorin(), and pgm_triggermode().

#define X353_DCR1	(	x,
		y		)	(((((y) & ((1 << X353DCR1__##x##__WIDTH)-1))) \| (1 << X353DCR1__##x##__WIDTH) ) << X353DCR1__##x##__BITNM)

Definition at line 325 of file x353.h.

Referenced by pgm_triggermode().

#define X353DCR0__ARO__BITNM 15

Definition at line 348 of file x353.h.

#define X353DCR0__ARO__WIDTH 1

Definition at line 349 of file x353.h.

#define X353DCR0__ARST__BITNM 13

Definition at line 346 of file x353.h.

#define X353DCR0__ARST__WIDTH 1

Definition at line 347 of file x353.h.

#define X353DCR0__BAYER_PHASE__BITNM 0

============ X313_WA_DCR0 ==============

Definition at line 329 of file x353.h.

#define X353DCR0__BAYER_PHASE__WIDTH 2

Definition at line 330 of file x353.h.

#define X353DCR0__CNVEN__BITNM 17

Definition at line 352 of file x353.h.

#define X353DCR0__CNVEN__WIDTH 1

Definition at line 353 of file x353.h.

#define X353DCR0__DLYHOR__BITNM 5

Definition at line 335 of file x353.h.

#define X353DCR0__DLYHOR__WIDTH 1

Definition at line 336 of file x353.h.

#define X353DCR0__FILLFACTORY__BITNM 3

Definition at line 332 of file x353.h.

#define X353DCR0__FILLFACTORY__WIDTH 1

Definition at line 333 of file x353.h.

#define X353DCR0__NEGRST__BITNM 7

Definition at line 338 of file x353.h.

#define X353DCR0__NEGRST__WIDTH 1

Definition at line 339 of file x353.h.

#define X353DCR0__SENSTRIGEN__BITNM 19

Definition at line 355 of file x353.h.

#define X353DCR0__SENSTRIGEN__WIDTH 1

Definition at line 356 of file x353.h.

#define X353DCR0__SKIPLINE__WIDTH 1

Definition at line 342 of file x353.h.

#define X353DCR0__SKIPLINEL__BITNM 9

Definition at line 341 of file x353.h.

#define X353DCR0__XT_POL__BITNM 11

Definition at line 344 of file x353.h.

#define X353DCR0__XT_POL__WIDTH 1

Definition at line 345 of file x353.h.

#define X353DCR1__BLOCKVSYNC__BITNM 18

Definition at line 384 of file x353.h.

#define X353DCR1__BLOCKVSYNC__WIDTH 1

Definition at line 385 of file x353.h.

#define X353DCR1__DCLKMODE__BITNM 4

Definition at line 367 of file x353.h.

#define X353DCR1__DCLKMODE__WIDTH 1

Definition at line 368 of file x353.h.

#define X353DCR1__EARLYTRIG__BITNM 2

Definition at line 363 of file x353.h.

#define X353DCR1__EARLYTRIG__WIDTH 1

Definition at line 364 of file x353.h.

#define X353DCR1__HACT_PHASE__BITNM 8

Definition at line 374 of file x353.h.

#define X353DCR1__HACT_PHASE__WIDTH 2

Definition at line 375 of file x353.h.

#define X353DCR1__HFCOMP__BITNM 14

Definition at line 381 of file x353.h.

#define X353DCR1__HFCOMP__WIDTH 3

Definition at line 382 of file x353.h.

#define X353DCR1__MRST__BITNM 0

============ X313_WA_DCR1 ==============

Definition at line 359 of file x353.h.

#define X353DCR1__MRST__WIDTH 1

Definition at line 360 of file x353.h.

#define X353DCR1__PCLKSRC__BITNM 11

Definition at line 378 of file x353.h.

#define X353DCR1__PCLKSRC__WIDTH 2

Definition at line 379 of file x353.h.

#define X353DCR1__PXD14__BITNM 6

Definition at line 371 of file x353.h.

#define X353DCR1__PXD14__WIDTH 1

Definition at line 372 of file x353.h.

#define X3X3_AFTERWRITE {if (!port_csp0_addr[X313__RA__MODEL]) printk ("model=0");}

Definition at line 572 of file x353.h.

Referenced by fpga_hist_read_nice().

#define x3x3_DELAY ( x ) {int iiii; for (iiii=0; iiii < (x); iiii++) X3X3_AFTERWRITE ; }

Definition at line 573 of file x353.h.

Referenced by i2c_inbyte(), i2c_outbyte(), i2c_restart(), i2c_start(), and i2c_stop().

#define X3X3_GAMMA_PAGE ((port_csp0_addr[I2C_FRAME_NUMBER] & 0x20000)?1:0)

Definition at line 474 of file x353.h.

#define X3X3_I2C_FRAME (port_csp0_addr[I2C_FRAME_NUMBER] & 0x7)

Definition at line 470 of file x353.h.

Referenced by elphel_FPGA_interrupt(), resetFrameNumber(), and tasklet_fpga_function().

#define X3X3_I2C_IS_BUSY

Value:

(((port_csp0_addr[I2C_FRAME_NUMBER] | \
                                port_csp0_addr[I2C_FRAME_NUMBER] | \
                                port_csp0_addr[I2C_FRAME_NUMBER] | \
                                port_csp0_addr[I2C_FRAME_NUMBER] | \
                                port_csp0_addr[I2C_FRAME_NUMBER] ) & 0x10000)?1:0)

Definition at line 465 of file x353.h.

#define X3X3_I2C_RESET_BITS 0x4000

Definition at line 456 of file x353.h.

#define X3X3_I2C_RESET_WAIT {port_csp0_addr[X313_I2C_CMD]=X3X3_I2C_RESET_BITS; while (X3X3_I2C_IS_BUSY) ; }

Definition at line 478 of file x353.h.

Referenced by initSequencers().

#define X3X3_I2C_RUN {port_csp0_addr[X313_I2C_CMD]=X3X3_I2C_RUN_BITS ; X3X3_AFTERWRITE ;}

Definition at line 477 of file x353.h.

Referenced by mt9x001_pgm_initsensor().

#define X3X3_I2C_RUN_BITS 0x3000

Definition at line 454 of file x353.h.

#define X3X3_I2C_SCL_0_BITS 0x10000

software control of SDA0, SCL0 lines (when hardware i2c is off)

Definition at line 458 of file x353.h.

Referenced by i2c_scl_0().

#define X3X3_I2C_SCL_1_BITS 0x20000

Definition at line 459 of file x353.h.

Referenced by i2c_scl_1().

#define X3X3_I2C_SCL_Z_BITS 0x30000

Definition at line 460 of file x353.h.

#define X3X3_I2C_SDA_0_BITS 0x40000

Definition at line 461 of file x353.h.

Referenced by i2c_sda_strong(), and i2c_sda_weak().

#define X3X3_I2C_SDA_1_BITS 0x80000

Definition at line 462 of file x353.h.

Referenced by i2c_sda_strong().

#define X3X3_I2C_SDA_Z_BITS 0xc0000

Definition at line 463 of file x353.h.

Referenced by i2c_sda_weak().

#define X3X3_I2C_SEND1	(	a,
		s,
		r,
		d	)	{port_csp0_addr[a] = ((s)<<24) \| (((r) & 0xff) << 16) \| (((d) & 0xff) << 8) ; X3X3_AFTERWRITE ;}

Definition at line 472 of file x353.h.

#define X3X3_I2C_SEND2	(	a,
		s,
		r,
		d	)	{port_csp0_addr[a] = ((s)<<24) \| (((r) & 0xff) << 16) \| ((d) & 0xffff) ; X3X3_AFTERWRITE ;}

Definition at line 471 of file x353.h.

Referenced by mt9x001_pgm_gains(), mt9x001_pgm_initsensor(), mt9x001_pgm_limitfps(), mt9x001_pgm_sensorregs(), mt9x001_pgm_triggermode(), and mt9x001_pgm_window_common().

#define X3X3_I2C_STOP_BITS 0x2000

Definition at line 455 of file x353.h.

#define X3X3_I2C_STOP_WAIT {port_csp0_addr[X313_I2C_CMD]=X3X3_I2C_STOP_BITS; while (X3X3_I2C_IS_BUSY) ; }

X3X3_I2C_STOP_WAIT does not stop frame counter - it still counts frame pulses.

Definition at line 476 of file x353.h.

Referenced by mt9x001_pgm_detectsensor(), and mt9x001_pgm_initsensor().

#define X3X3_RSTSENSDCM {port_csp0_addr[X313_WA_DCM]=0xf0;}

Definition at line 190 of file x353.h.

Referenced by pgm_detectsensor(), and pgm_sensorphase().

#define X3X3_SENSDCM_DEC {port_csp0_addr[X313_WA_DCM]=0x10;}

Definition at line 195 of file x353.h.

Referenced by pgm_sensorphase().

#define X3X3_SENSDCM_DEC90 {port_csp0_addr[X313_WA_DCM]=0x40;}

Definition at line 192 of file x353.h.

#define X3X3_SENSDCM_INC {port_csp0_addr[X313_WA_DCM]=0x20;}

Definition at line 194 of file x353.h.

Referenced by pgm_sensorphase().

#define X3X3_SENSDCM_INC90 {port_csp0_addr[X313_WA_DCM]=0x80;}

Definition at line 191 of file x353.h.

Referenced by pgm_sensorphase().

#define X3X3_SENSDCM_NOP {port_csp0_addr[X313_WA_DCM]=0x0;}

Definition at line 196 of file x353.h.

#define X3X3_SEQ_RESET {port_csp0_addr[X313_SEQ_CMD]=X3X3_SEQ_RESET_BITS; X3X3_AFTERWRITE ; X3X3_AFTERWRITE ; X3X3_AFTERWRITE ; X3X3_AFTERWRITE ; }

Definition at line 506 of file x353.h.

Referenced by initSequencers().

#define X3X3_SEQ_RESET_BITS 0x4000

Definition at line 500 of file x353.h.

#define X3X3_SEQ_RUN {port_csp0_addr[X313_SEQ_CMD]=X3X3_SEQ_RUN_BITS ; X3X3_AFTERWRITE ;}

Definition at line 505 of file x353.h.

Referenced by mt9x001_pgm_initsensor().

#define X3X3_SEQ_RUN_BITS 0x3000

Definition at line 498 of file x353.h.

#define X3X3_SEQ_SEND1	(	f,
		a,
		d	)	{port_csp0_addr[f] = ((a)<<24) \| ((d) & 0xffffff) ; X3X3_AFTERWRITE ;}

Definition at line 502 of file x353.h.

#define X3X3_SEQ_STOP {port_csp0_addr[X313_SEQ_CMD]=X3X3_SEQ_STOP_BITS;}

Definition at line 504 of file x353.h.

#define X3X3_SEQ_STOP_BITS 0x2000

Definition at line 499 of file x353.h.

#define X3X3_SET_I2C_BYTES ( x ) (0x800 | (((x)<<9) & 0x600))

Definition at line 453 of file x353.h.

Referenced by pgm_i2c().

#define X3X3_SET_I2C_DLY ( x ) (0x100 | ((x) & 0xff))

Definition at line 452 of file x353.h.

Referenced by pgm_i2c().

Generated on Fri Nov 28 00:08:14 2008 for elphel by

1.5.1


Defines
#define	X313_MINMODREV 0x03534000
#define	X313_MAXMODREV 0x035340ff
#define	X313__RA__STATUS 0x10
#define	X313__RA__IRQS 0x11
#define	X313__RA__TRIGPH 0x12
#define	X313__RA__MODEL 0x13
#define	X313__RA__TABLE 0x14
#define	X313__RA__XFERCNTR 0x14
#define	X313__RA__HIGHFREQ 0x15
#define	X313__RA__IOPINS 0x70
#define	X313__RA__SENSFPGA 0x74
#define	SFPGA_RD_BIT 16
#define	I2C_FRAME_NUMBER 0x16
#define	X313__RA__SDCH0 0x20
#define	X313__RA__SDCH1 0x24
#define	X313__RA__SDCH2 0x28
#define	X313__RA__SDCH3 0x2c
#define	X313__RA__SDBUF3 0x30
#define	X313_SR__CLK_LOCKED 28
#define	X313_SR__SENS_DCM_OVFL 27
#define	X313_SR__SENS_DCM_LOCKED 26
#define	X313_SR__SENS_DCM_RDY 25
#define	X313_SR__SENS_DCM_EARLY 24
#define	X313_SR__SENS_DCM_LATE 23
#define	X313_SR__SENS_DCM_ERROR 24
#define	X313_SR__SENS_DCM_LATE 23
#define	X313_SENSOR_PHASE ((port_csp0_addr[X313__RA__STATUS] >> X313_SR__SENS_DCM_LATE ) & 3)
#define	X313_SR__DCM_OVFL 22
#define	X313_SR__DCM_LOCKED 21
#define	X313_SR__DCM_RDY 20
#define	X313_SR__DCM_EARLY 19
#define	X313_SR__DCM_LATE 18
#define	X313_SR__DMA_EMPTY 17
#define	X313_SR__DONE_CMPRS 16
#define	X313_SR__DONE_CI 15
#define	X313_SR__DCCRDY 14
#define	X313_SR__DONE 13
#define	X313_SR__SENST1 12
#define	X313_SR__SENST0 11
#define	X313_SR__NXTFR3 10
#define	X313_SR__NXTFR2 9
#define	X313_SR__NXTFR1 8
#define	X313_SR__NXTFR0 7
#define	X313_SR__PIOWEMPTY 6
#define	X313_SR__PIORDY 5
#define	X313_SR__CH2RDY 4
#define	X313_SR__CH1RDY 3
#define	X313_SR__CH0RDY 2
#define	X313_SR__SCL0 1
#define	X313_SR__SDA0 0
#define	X313_PIOR__SCL1 0
#define	X313_PIOR__SDA1 1
#define	X313_PIOR__XRST 2
#define	X313_PIOR__AUXCLK 3
#define	X313_PIOR__EXPS 4
#define	X313_PIOR__TRIG 5
#define	X313_SR__X323_SI 0
#define	X313_SR(x) ((port_csp0_addr[X313__RA__STATUS] >> X313_SR__##x ) & 1)
#define	X313_PIOR(x) ((port_csp0_addr[X313__RA__IOPINS] >> X313_PIOR__##x ) & 1)
#define	X313_IR__VACT 0
#define	X313_IR__XINT 1
#define	X313_IR__XFEROVR 2
#define	X313_IR__DONE 3
#define	X313_IR__EOT 4
#define	X313_IR__DCC 5
#define	X313_IR__DONE_INPUT 6
#define	X313_IR__DONE_COMPRESS 7
#define	X313_IR__SMART 8
#define	X313_IR(x) ((port_csp0_addr[X313__RA__IRQS] >> ( X313_IR__##x ) + 8) & 1)
#define	EN_INTERRUPT(x) port_csp0_addr[X313_WA_IRQ_ENA]= (1<< ( X313_IR__##x ))
#define	DIS_INTERRUPT(x) {port_csp0_addr[X313_WA_IRQ_DIS]= (1<< ( X313_IR__##x ) ); port_csp0_addr[X313_WA_IRQ_RST]= (1<< ( X313_IR__##x ) );}
#define	DIS_INTERRUPTS {port_csp0_addr[X313_WA_IRQ_DIS]= 0xffff; port_csp0_addr[X313_WA_IRQ_RST]= 0xffff;}
#define	X313_WA_WCTL 0
#define	X313_WA_DMACR 1
#define	X313_WA_SENSFPN 2
#define	X313_SENSFPN_D(t, s, m, d, l)
#define	X313_WA_VIRTTRIG 3
#define	X313_WA_TRIG 4
#define	X313_WA_NLINES 5
#define	X313_WA_WCTL24 6
#define	X313_WA_DCDC 7
#define	X313_WA_DCM 8
#define	X3X3_RSTSENSDCM {port_csp0_addr[X313_WA_DCM]=0xf0;}
#define	X3X3_SENSDCM_INC90 {port_csp0_addr[X313_WA_DCM]=0x80;}
#define	X3X3_SENSDCM_DEC90 {port_csp0_addr[X313_WA_DCM]=0x40;}
#define	X3X3_SENSDCM_INC {port_csp0_addr[X313_WA_DCM]=0x20;}
#define	X3X3_SENSDCM_DEC {port_csp0_addr[X313_WA_DCM]=0x10;}
#define	X3X3_SENSDCM_NOP {port_csp0_addr[X313_WA_DCM]=0x0;}
#define	X313_WA_COLOR_SAT 9
#define	DEFAULT_COLOR_SATURATION_BLUE 0x90
#define	DEFAULT_COLOR_SATURATION_RED 0xb6
#define	X313_WA_FRAMESYNC_DLY 0x0a
#define	X313_WA_QUANTIZER_MODE 0x0b
#define	X313_WA_COMP_CMD 0x0c
#define	COMPCMD_FOCUS(x) ((1<<23) \| (((x) & 3) << 21))
#define	COMPCMD_BAYERSHIFT(x) ((1<<20) \| (((x) & 3) << 18))
#define	COMPCMD_TILESHIFT(x) ((1<<17) \| (((x) & 7) << 14))
#define	COMPCMD_DEMOS(x) ((1<<13) \| (((x) & 0x0f) << 9))
#define	DEMOS_MONO6 0
#define	DEMOS_COLOR18 1
#define	DEMOS_JP46 2
#define	DEMOS_JP46DC 3
#define	DEMOS_COLOR20 4
#define	DEMOS_JP4 5
#define	DEMOS_JP4DC 6
#define	DEMOS_JP4DIFF 7
#define	DEMOS_JP4HDR 8
#define	DEMOS_JP4DIFF2 9
#define	DEMOS_JP4HDR2 10
#define	DEMOS_MONO4 14
#define	COMPCMD_DCSUB(x) ((1<<8) \| (((x) & 1) << 7))
#define	COMPCMD_QTAB(x) ((1<<6) \| (((x) & 7) << 3))
#define	FPGA_NQTAB 8
#define	COMPCMD_RESET 4
#define	COMPCMD_STOP 5
#define	COMPCMD_SINGLE 6
#define	COMPCMD_RUN 7
#define	X313_WA_COMP_TA 0x0e
#define	X313_WA_COMP_TD 0x0f
#define	X313_WA_MCUNUM 0x0d
#define	X313_WA_SMART_IRQ 0x1a
	FIXME: (in FPGA) - now if "smart" mode is disabled, VACT will not cause interrupt on smart bit. So smart mode will be always enabled for now.
#define	X313_WA_DCM_RST 0x1b
#define	X313_WA_IRQ_RST 0x1c
#define	X313_WA_IRQ_DIS 0x1d
#define	X313_WA_IRQ_ENA 0x1e
#define	X313_WA_IRQ_WVECT 0x1f
#define	EN_INTERRUPT(x) port_csp0_addr[X313_WA_IRQ_ENA]= (1<< ( X313_IR__##x ))
#define	DIS_INTERRUPT(x) {port_csp0_addr[X313_WA_IRQ_DIS]= (1<< ( X313_IR__##x ) ); port_csp0_addr[X313_WA_IRQ_RST]= (1<< ( X313_IR__##x ) );}
#define	DIS_INTERRUPTS {port_csp0_addr[X313_WA_IRQ_DIS]= 0xffff; port_csp0_addr[X313_WA_IRQ_RST]= 0xffff;}
#define	X313_WA_HIST_LEFT 0x40
#define	X313_WA_HIST_TOP 0x41
#define	X313_WA_HIST_WIDTH 0x42
#define	X313_WA_HIST_HEIGHT 0x43
#define	X313_WA_HIST_ADDR 0x44
#define	X313_RA_HIST_DATA 0x45
#define	X313_WA_RTC_USEC 0x48
#define	X313_WA_RTC_SEC 0x49
#define	X313_WA_RTC_CORR 0x4a
#define	X313_WA_RTC_LATCH 0x4b
#define	X313_RA_RTC_USEC 0x48
#define	X313_RA_RTC_SEC 0x49
#define	X313_WA_TIMESTAMP 0x4c
#define	X313_TIMESTAMPLEN 28
#define	X313_WA_DCR0 0x4e
#define	X313_WA_DCR1 0x4f
#define	X353_DCR0(x, y) (((((y) & ((1 << X353DCR0__##x##__WIDTH)-1))) \| (1 << X353DCR0__##x##__WIDTH) ) << X353DCR0__##x##__BITNM)
#define	X353_DCR1(x, y) (((((y) & ((1 << X353DCR1__##x##__WIDTH)-1))) \| (1 << X353DCR1__##x##__WIDTH) ) << X353DCR1__##x##__BITNM)
#define	X353DCR0__BAYER_PHASE__BITNM 0
	============ X313_WA_DCR0 ==============
#define	X353DCR0__BAYER_PHASE__WIDTH 2
#define	X353DCR0__FILLFACTORY__BITNM 3
#define	X353DCR0__FILLFACTORY__WIDTH 1
#define	X353DCR0__DLYHOR__BITNM 5
#define	X353DCR0__DLYHOR__WIDTH 1
#define	X353DCR0__NEGRST__BITNM 7
#define	X353DCR0__NEGRST__WIDTH 1
#define	X353DCR0__SKIPLINEL__BITNM 9
#define	X353DCR0__SKIPLINE__WIDTH 1
#define	X353DCR0__XT_POL__BITNM 11
#define	X353DCR0__XT_POL__WIDTH 1
#define	X353DCR0__ARST__BITNM 13
#define	X353DCR0__ARST__WIDTH 1
#define	X353DCR0__ARO__BITNM 15
#define	X353DCR0__ARO__WIDTH 1
#define	X353DCR0__CNVEN__BITNM 17
#define	X353DCR0__CNVEN__WIDTH 1
#define	X353DCR0__SENSTRIGEN__BITNM 19
#define	X353DCR0__SENSTRIGEN__WIDTH 1
#define	X353DCR1__MRST__BITNM 0
	============ X313_WA_DCR1 ==============
#define	X353DCR1__MRST__WIDTH 1
#define	X353DCR1__EARLYTRIG__BITNM 2
#define	X353DCR1__EARLYTRIG__WIDTH 1
#define	X353DCR1__DCLKMODE__BITNM 4
#define	X353DCR1__DCLKMODE__WIDTH 1
#define	X353DCR1__PXD14__BITNM 6
#define	X353DCR1__PXD14__WIDTH 1
#define	X353DCR1__HACT_PHASE__BITNM 8
#define	X353DCR1__HACT_PHASE__WIDTH 2
#define	X353DCR1__PCLKSRC__BITNM 11
#define	X353DCR1__PCLKSRC__WIDTH 2
#define	X353DCR1__HFCOMP__BITNM 14
#define	X353DCR1__HFCOMP__WIDTH 3
#define	X353DCR1__BLOCKVSYNC__BITNM 18
#define	X353DCR1__BLOCKVSYNC__WIDTH 1
#define	CCAM_ARO_ON port_csp0_addr[X313_WA_DCR0]=X353_DCR0(ARO,1)
#define	CCAM_ARO_OFF port_csp0_addr[X313_WA_DCR0]=X353_DCR0(ARO,0)
#define	CCAM_DCLK_OFF port_csp0_addr[X313_WA_DCR1]=X353_DCR1(DCLKMODE,1)
	turn clock to sensor on/off (default - on)
#define	CCAM_DCLK_ON port_csp0_addr[X313_WA_DCR1]=X353_DCR1(DCLKMODE,0)
#define	CCAM_ARST_OFF port_csp0_addr[X313_WA_DCR0]=X353_DCR0(ARST,1)
#define	CCAM_ARST_ON port_csp0_addr[X313_WA_DCR0]=X353_DCR0(ARST,0)
#define	CCAM_MRST_OFF port_csp0_addr[X313_WA_DCR1]=X353_DCR1(MRST,1)
#define	CCAM_MRST_ON port_csp0_addr[X313_WA_DCR1]=X353_DCR1(MRST,0)
#define	CCAM_NEGRST port_csp0_addr[X313_WA_DCR0]=X353_DCR0(NEGRST,1)
#define	CCAM_POSRST port_csp0_addr[X313_WA_DCR0]=X353_DCR0(NEGRST,0)
#define	CCAM_CNVEN_ON port_csp0_addr[X313_WA_DCR0]=X353_DCR0(CNVEN,1)
	enable power converter control. * Only if it is not MT9P001 !!! *
#define	CCAM_CNVEN_OFF port_csp0_addr[X313_WA_DCR0]=X353_DCR0(CNVEN,0)
#define	CCAM_TRIG_INT port_csp0_addr[X313_WA_DCR0]=X353_DCR0(SENSTRIGEN,0)
	Sensor (MT9X001) trigger source selection (internal/external).
#define	CCAM_TRIG_EXT port_csp0_addr[X313_WA_DCR0]=X353_DCR0(SENSTRIGEN,1)
#define	CCAM_TIMESTAMP_NORMAL port_csp0_addr[X313_WA_DCR1]=X353_DCR1(EARLYTRIG,0)
	early/normal timestamp in async mode
#define	CCAM_TIMESTAMP_EARLY port_csp0_addr[X313_WA_DCR1]=X353_DCR1(EARLYTRIG,1)
#define	CCAM_SET_HACT_PHASE(x) port_csp0_addr[X313_WA_DCR1]=X353_DCR1(HACT_PHASE,(x))
	Set HACT phase (90 degrees increments - needed for MT9P001.
#define	CCAM_VSYNC_ON port_csp0_addr[X313_WA_DCR1]=X353_DCR1(BLOCKVSYNC,0)
#define	CCAM_VSYNC_OFF port_csp0_addr[X313_WA_DCR1]=X353_DCR1(BLOCKVSYNC,1)
#define	X313_I2C_FRAME0 0x50
	=============================
#define	X313_I2C_FRAME1 0x51
#define	X313_I2C_FRAME2 0x52
#define	X313_I2C_FRAME3 0x53
#define	X313_I2C_FRAME4 0x54
#define	X313_I2C_FRAME5 0x55
#define	X313_I2C_FRAME6 0x56
#define	X313_I2C_FRAME7 0x57
#define	X313_I2C_ASAP 0x58
#define	X313_I2C_NEXT 0x59
#define	X313_I2C_NEXT2 0x5a
#define	X313_I2C_NEXT3 0x5b
#define	X313_I2C_NEXT4 0x5c
#define	X313_I2C_NEXT5 0x5d
#define	X313_I2C_NEXT6 0x5e
#define	X313_I2C_CMD 0x5f
#define	X3X3_SET_I2C_DLY(x) (0x100 \| ((x) & 0xff))
#define	X3X3_SET_I2C_BYTES(x) (0x800 \| (((x)<<9) & 0x600))
#define	X3X3_I2C_RUN_BITS 0x3000
#define	X3X3_I2C_STOP_BITS 0x2000
#define	X3X3_I2C_RESET_BITS 0x4000
#define	X3X3_I2C_SCL_0_BITS 0x10000
	software control of SDA0, SCL0 lines (when hardware i2c is off)
#define	X3X3_I2C_SCL_1_BITS 0x20000
#define	X3X3_I2C_SCL_Z_BITS 0x30000
#define	X3X3_I2C_SDA_0_BITS 0x40000
#define	X3X3_I2C_SDA_1_BITS 0x80000
#define	X3X3_I2C_SDA_Z_BITS 0xc0000
#define	X3X3_I2C_IS_BUSY
#define	X3X3_I2C_FRAME (port_csp0_addr[I2C_FRAME_NUMBER] & 0x7)
#define	X3X3_I2C_SEND2(a, s, r, d) {port_csp0_addr[a] = ((s)<<24) \| (((r) & 0xff) << 16) \| ((d) & 0xffff) ; X3X3_AFTERWRITE ;}
#define	X3X3_I2C_SEND1(a, s, r, d) {port_csp0_addr[a] = ((s)<<24) \| (((r) & 0xff) << 16) \| (((d) & 0xff) << 8) ; X3X3_AFTERWRITE ;}
#define	X3X3_GAMMA_PAGE ((port_csp0_addr[I2C_FRAME_NUMBER] & 0x20000)?1:0)
#define	X3X3_I2C_STOP_WAIT {port_csp0_addr[X313_I2C_CMD]=X3X3_I2C_STOP_BITS; while (X3X3_I2C_IS_BUSY) ; }
	X3X3_I2C_STOP_WAIT does not stop frame counter - it still counts frame pulses.
#define	X3X3_I2C_RUN {port_csp0_addr[X313_I2C_CMD]=X3X3_I2C_RUN_BITS ; X3X3_AFTERWRITE ;}
#define	X3X3_I2C_RESET_WAIT {port_csp0_addr[X313_I2C_CMD]=X3X3_I2C_RESET_BITS; while (X3X3_I2C_IS_BUSY) ; }
#define	X313_SEQ_FRAME0 0x60
#define	X313_SEQ_FRAME1 0x61
#define	X313_SEQ_FRAME2 0x62
#define	X313_SEQ_FRAME3 0x63
#define	X313_SEQ_FRAME4 0x64
#define	X313_SEQ_FRAME5 0x65
#define	X313_SEQ_FRAME6 0x66
#define	X313_SEQ_FRAME7 0x67
#define	X313_SEQ_ASAP 0x68
#define	X313_SEQ_NEXT 0x69
#define	X313_SEQ_NEXT2 0x6a
#define	X313_SEQ_NEXT3 0x6b
#define	X313_SEQ_NEXT4 0x6c
#define	X313_SEQ_NEXT5 0x6d
#define	X313_SEQ_NEXT6 0x6e
#define	X313_SEQ_CMD 0x6f
#define	X3X3_SEQ_RUN_BITS 0x3000
#define	X3X3_SEQ_STOP_BITS 0x2000
#define	X3X3_SEQ_RESET_BITS 0x4000
#define	X3X3_SEQ_SEND1(f, a, d) {port_csp0_addr[f] = ((a)<<24) \| ((d) & 0xffffff) ; X3X3_AFTERWRITE ;}
#define	X3X3_SEQ_STOP {port_csp0_addr[X313_SEQ_CMD]=X3X3_SEQ_STOP_BITS;}
#define	X3X3_SEQ_RUN {port_csp0_addr[X313_SEQ_CMD]=X3X3_SEQ_RUN_BITS ; X3X3_AFTERWRITE ;}
#define	X3X3_SEQ_RESET {port_csp0_addr[X313_SEQ_CMD]=X3X3_SEQ_RESET_BITS; X3X3_AFTERWRITE ; X3X3_AFTERWRITE ; X3X3_AFTERWRITE ; X3X3_AFTERWRITE ; }
#define	X313_WA_IOPINS 0x70
#define	X313_WA_SENSFPGA 0x74
#define	X313_WA_CAMSYNCTRIG 0x78
#define	X313_WA_CAMSYNCDLY 0x79
#define	X313_WA_CAMSYNCOUT 0x7a
#define	X313_WA_CAMSYNCPER 0x7b
#define	SFPGA_TDI_BIT 0x0
#define	SFPGA_TMS_BIT 0x2
#define	SFPGA_TCK_BIT 0x4
#define	SFPGA_PROG_BIT 0x6
#define	SFPGA_PGMEN_BIT 0x8
#define	SFPGA_RD_SENSPGMPIN 0x80000
#define	SFPGA_RD_TDO 0x90000
#define	SFPGA_RD_DONE 0xa0000
#define	X3X3_AFTERWRITE {if (!port_csp0_addr[X313__RA__MODEL]) printk ("model=0");}
#define	x3x3_DELAY(x) {int iiii; for (iiii=0; iiii < (x); iiii++) X3X3_AFTERWRITE ; }
#define	X313_WA_SDCH0_CTL0 0x20
#define	X313_WA_SDCH0_CTL1 0x21
#define	X313_WA_SDCH0_CTL2 0x22
#define	X313_WA_SD_MANCMD 0x23
#define	X313_WA_SDCH1_CTL0 0x24
#define	X313_WA_SDCH1_CTL1 0x25
#define	X313_WA_SDCH1_CTL2 0x26
#define	X313_WA_SD_MODE 0x27
#define	X313_WA_SDCH2_CTL0 0x28
#define	X313_WA_SDCH2_CTL1 0x29
#define	X313_WA_SDCH2_CTL2 0x2a
#define	X313_WA_SDCH3_CTL0 0x2c
#define	X313_WA_SDCH3_CTL1 0x2d
#define	X313_WA_SDCH3_CTL2 0x2e
#define	X313_WA_SDPIO_NEXT 0x2f
#define	X313_WA_SD_PIOWIN 0x30
#define	X313_WA_LENSCORR 0x31
#define	X313_LENS_AX(x) ( 0x0 \| ((x)& 0x7ffff))
#define	X313_LENS_AY(x) ( 0x80000 \| ((x)& 0x7ffff))
#define	X313_LENS_C(x) (0x100000 \| ((x)& 0x7ffff))
#define	X313_LENS_BX(x) (0x200000 \| ((x)& 0x1fffff))
#define	X313_LENS_BY(x) (0x400000 \| ((x)& 0x1fffff))
#define	X313_LENS_SCALES(color, x) (0x600000 \| (((color)&3)<<17) \| ((x)& 0x1ffff))
#define	X313_LENS_FATZERO_IN(x) (0x680000 \| ((x)& 0xffff))
#define	X313_LENS_FATZERO_OUT(x) (0x690000 \| ((x)& 0xffff))
#define	X313_LENS_POSTSCALE(x) (0x6a0000 \| ((x)& 0x7))
#define	RD_SD_PIOWIN port_csp4_addr[X313_WA_SD_PIOWIN]
#define	X313_PREINIT_SDCHAN(num, mode, wnr, dep, sa, ntilex, ntiley)
	Old style memory channel programming.
#define	X313_POSTINIT_SDCHAN(num, cmd) {port_csp0_addr[X313_WA_SDCH0_CTL0+0+((num)<<2)] = cmd; X3X3_AFTERWRITE}
#define	X313_INIT_SDCHAN(num, mode, wnr, dep, sa, ntilex, ntiley) {X313_POSTINIT_SDCHAN ( num, X313_PREINIT_SDCHAN ( num,mode,wnr,dep,sa,ntilex,ntiley ))}
#define	X313_SDCHAN_REG0(mode, wnr, dep, sa, ntilex, ntiley) ((((mode) & 1) << 15) \| (((wnr) & 1) << 14) \| (((dep) & 1) << 13) \| (((sa) >> 8) & 0x1fff))
	data to be programmed to the memory registers through the sequencer (all arguments are the same, not all are used for all registers)
#define	X313_SDCHAN_REG1(mode, wnr, dep, sa, ntilex, ntiley) (0x8000 \| (((ntilex) & 0x3ff) << 4) \| (((sa) >> 21) & 0xf))
#define	X313_SDCHAN_REG2(mode, wnr, dep, sa, ntilex, ntiley) ((ntiley) & 0xfff)
#define	X313_CHN_EN_D(x) ((0x30 << (((x)& 3)<<1)) \| 0xf)
	mode=1, wnr=1 - photofinish
#define	X313_CHN_DIS_D(x) (0x20 << (((x)& 3)<<1))
#define	X313_CHN_DISALL_D 0xaa0
#define	X313_SDRAM_OFF_D 0xaaa
#define	X313_SDRAM_ON_D 0xaaf
#define	X313_CHN_EN(x) {X3X3_AFTERWRITE ; port_csp0_addr[X313_WA_SD_MODE] = X313_CHN_EN_D(x); }
#define	X313_CHN_DIS(x) {X3X3_AFTERWRITE ; port_csp0_addr[X313_WA_SD_MODE] = X313_CHN_DIS_D(x); }
#define	X313_CHN_DISALL {X3X3_AFTERWRITE ; port_csp0_addr[X313_WA_SD_MODE] = X313_CHN_DISALL_D ; }
#define	X313_SDRAM_OFF {port_csp0_addr[X313_WA_SD_MODE]= X313_SDRAM_OFF_D;}
#define	X313_SDRAM_ON {port_csp0_addr[X313_WA_SD_MODE]= X313_SDRAM_ON_D;}
#define	X313_IS_SDRAM_ON (port_csp0_addr[X313_WA_SD_MODE],((port_csp0_addr[X313_WA_SD_MODE] & 3)==3))
#define	X313_CHN0_BOUND (port_csp0_addr[X313_WA_SDCH2_CTL0],(port_csp0_addr[X313_WA_SDCH2_CTL0] & 0x2000))
#define	X313_XFERCNTR (port_csp0_addr[X313__RA__XFERCNTR],port_csp0_addr[X313__RA__XFERCNTR])
#define	X313_HIGHFREQ (port_csp0_addr[X313__RA__HIGHFREQ],port_csp0_addr[X313__RA__HIGHFREQ])
#define	X313_IRQSTATE (port_csp0_addr[0x11],port_csp0_addr[0x11])
#define	X313_IOPINS (port_csp0_addr[X313__RA__IOPINS],port_csp0_addr[X313__RA__IOPINS])
#define	X313_CHN0_USED
	X313_WA_SDCH0_CTL2 bits 12..15 are coming from dynamic register and do not depend on the written data.
#define	X313_CHN0_SET_USED { port_csp0_addr[X313_WA_SDCH0_CTL1]=0x8000; }
#define	X313_CHN0_SET_UNUSED { port_csp0_addr[X313_WA_SDCH0_CTL1]=0; }
#define	X313_SET_FPGA_TIME(x, y) { port_csp0_addr[X313_WA_RTC_USEC]= ( y ); port_csp0_addr[X313_WA_RTC_SEC]= ( x ); }
#define	X313_GET_FPGA_TIME(x, y) { port_csp0_addr[X313_WA_RTC_LATCH]= 0; X3X3_AFTERWRITE ; x = port_csp0_addr[X313_WA_RTC_SEC]; y = port_csp0_addr[X313_WA_RTC_USEC];}
#define	X313_GET_FPGA_SECONDS(x) { port_csp0_addr[X313_WA_RTC_LATCH]= 0; X3X3_AFTERWRITE ; x = port_csp0_addr[X313_WA_RTC_SEC]}
#define	X313_MAP_FPN 0
#define	X313_SDRAM_SIZE 0x4000000
#define	X313_MAXWIDTH 4096
#define	X313_MAXHEIGHT 4096
#define	X313_MAP_FRAME ((X313_MAP_FPN) + (X313_MAXWIDTH) * (X313_MAXHEIGHT))
#define	X313_MARGINS 4
#define	X313_TILEHOR 16
#define	X313_TILEVERT 16