os/linux-2.6-tag--devboard-R2_10-4/arch/cris/arch-v32/drivers/elphel/fpga_io.c

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/*!***************************************************************************
*! FILE NAME  : fpga_io.c
*! DESCRIPTION: TBD
*! Copyright (C) 2002-2006 Elphel, Inc.
*! -----------------------------------------------------------------------------**
*!  This program is free software: you can redistribute it and/or modify
*!  it under the terms of the GNU General Public License as published by
*!  the Free Software Foundation, either version 3 of the License, or
*!  (at your option) any later version.
*!
*!  This program is distributed in the hope that it will be useful,
*!  but WITHOUT ANY WARRANTY; without even the implied warranty of
*!  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
*!  GNU General Public License for more details.
*!
*!  You should have received a copy of the GNU General Public License
*!  along with this program.  If not, see <http://www.gnu.org/licenses/>.
*! -----------------------------------------------------------------------------**
*!  $Log: fpga_io.c,v $
*!  Revision 1.1.1.1  2008/11/27 20:04:00  elphel
*!
*!
*!  Revision 1.10  2008/10/29 04:18:28  elphel
*!  v.8.0.alpha10 made a separate structure for global parameters (not related to particular frames in a frame queue)
*!
*!  Revision 1.9  2008/10/25 20:01:00  elphel
*!  bug fixed: removed reference to file->f_pos in write() and replaced with *ofs
*!
*!  Revision 1.8  2008/10/23 08:02:23  elphel
*!  fpga_read_hist_nice() bug fix
*!
*!  Revision 1.7  2008/10/04 16:10:12  elphel
*!  snapshot
*!
*!  Revision 1.6  2008/09/16 00:49:30  elphel
*!  snapshot
*!
*!  Revision 1.5  2008/09/12 00:23:59  elphel
*!  removed cc353.c, cc353.h
*!
*!  Revision 1.4  2008/08/25 19:07:23  elphel
*!  just a snapshot
*!
*!  Revision 1.3  2008/07/27 23:25:07  elphel
*!  next snapshot
*!
*!  Revision 1.2  2008/07/27 04:27:49  elphel
*!  next snapshot
*!
*!  Revision 1.1.1.1  2008/05/12 01:00:59  elphel
*!
*!
*!  Revision 1.6  2008/04/29 05:49:27  elphel
*!  typo
*!
*!  Revision 1.5  2008/04/14 17:15:52  spectr_rain
*!  200 gamma tables, correct 257 values tables
*!
*!  Revision 1.4  2008/04/11 23:16:51  elphel
*!  removed unneeded local_irq_disable() after local_irq_save_flags()
*!
*!  Revision 1.3  2008/04/09 21:01:25  elphel
*!  added access to individual wait state registers
*!
*!  Revision 1.2  2007/10/23 16:58:51  elphel
*!  Improved r/w access to FPGA registers (available from PHP)
*!
*!  Revision 1.1.1.1  2007/08/17 10:23:18  elphel
*!  This is a fresh tree based on elphel353-2.10
*!
*!  Revision 1.7  2007/08/17 10:23:18  spectr_rain
*!  switch to GPL3 license
*!
*!  Revision 1.6  2007/07/20 10:17:46  spectr_rain
*!  *** empty log message ***
*!
*!  Revision 1.2  2007/05/21 17:45:10  elphel
*!  boundary scan support, added 359/347 detection
*!
*!  Revision 1.1.1.1  2007/02/23 10:11:48  elphel
*!  initial import into CVS
*!
*!  Revision 1.3  2006/04/06 07:46:33  elphel
*!  control for canon lenses
*!
*/

/****************** INCLUDE FILES SECTION ***********************************/

#include <linux/module.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/autoconf.h>

#include <asm/system.h>
//#include <asm/svinto.h>
#include <asm/io.h>
//#include <linux/interrupt.h>


#include <asm/irq.h>

#include <asm/delay.h>
#include <asm/uaccess.h>
#include <asm/elphel/fpgaconfa.h> // defines port_csp0_addr, port_csp4_addr
#include <asm/elphel/c313a.h> // just for CX313_FPGA_TABLES_SIZE, DEBUG
#include "framepars.h"        // for debug mask

#include <asm/arch/hwregs/reg_map.h>
#include <asm/arch/hwregs/bif_core_defs.h>

#include "x3x3.h"

#include "fpgactrl.h"
#include "fpga_io.h"

#define D(x)
//#define D(x) printk("%s:%d:",__FILE__,__LINE__);x

// extern volatile unsigned long ccam_cr_shadow;



//#define FPGACONF_RD_WAITSTATES     150    // read R_WAITSTATES
//#define FPGACONF_WR_WAITSTATES     151    // write R_WAITSTATES
#if ELPHEL_DEBUG
  #define D12(x) { if (GLOBALPARS(G_DEBUG) & (1 <<12)) { x ;} }
  #define D13(x) { if (GLOBALPARS(G_DEBUG) & (1 <<13)) { x ;} }
  #define MDF12(x) { if (GLOBALPARS(G_DEBUG) & (1 <<12)) {printk("%s:%d:%s ",__FILE__,__LINE__,__FUNCTION__);x ;} }
// read_nice
  #define MDF13(x) { if (GLOBALPARS(G_DEBUG) & (1 <<13)) {printk("%s:%d:%s ",__FILE__,__LINE__,__FUNCTION__);x ;} }
#else
  #define D12(x)
  #define MDF12(x)
  #define MDF13(x)
#endif

unsigned long fpga_tables_buffer[CX313_FPGA_TABLES_SIZE];

#define CAPTURE_SIZE 8192
static char capture_buf[CAPTURE_SIZE];
static int capture_length;
static int capture_pointer;
int fpga_io_open(void) {
  return 0;
}
int fpga_io_close (void){
  return 0;
}

// will use 1.2-us "debounce/metastability" filter, so minimal pulse width detected will be 2.5us
int canon_lens_io (int d) {
  unsigned long flags;
  int res,i,j;

// make sure pins initialized
   if ((port_csp0_addr[0x70] & 5) !=5) {
     port_csp0_addr[0x70]=0x33;
     udelay (200);
   } 
   res=0;
// start condition   
   port_csp0_addr[0x70]=0x23;
   udelay (60);
   local_irq_save(flags);
   //local_irq_disable();  //disable all interrupts for the time of capture
   for (i=0; i<8; i++) {
     port_csp0_addr[0x70]= 0x22 | ((d & 0x80)?0x10:0);
     udelay (6);
     res=(res<<1) | ( (port_csp0_addr[0x70] & 2)>>1);
     port_csp0_addr[0x70]= 0x23 | ((d & 0x80)?0x10:0);
     udelay (6);
// wait clock is high here
     for (j=0;j<1000000;j++) {  // timeout
       if (port_csp0_addr[0x70] & 8) break;
       udelay (1);
     }  
     d<<=1;
   }
// wait clock low (by the lens)
   for (j=0;j<1000000;j++) {  // timeout
     if (!(port_csp0_addr[0x70] & 8)) break;
     udelay (1);
   }
   udelay (6);  
   port_csp0_addr[0x70]=0x33;
   local_irq_restore(flags);
   udelay (200);  
   return res;
}


int capture_pins (int n, int m) {
  int i;
  unsigned long flags;
  char b0,b1,b;
  int msk;
  msk=0xff& ((m!=0)?m:0xff);

  capture_length=0;
  capture_pointer=0;
  b0=b1=0xff;
  
   local_irq_save(flags);
   //local_irq_disable();  //disable all interrupts for the time of capture
   for (i=0; (i < n) && (capture_length < CAPTURE_SIZE); i++) {
    b=msk & port_csp0_addr[0x70]; //X313__RA__IOPINS
    if (b==b1) {
     if (b!=b0) capture_buf[capture_length++]=b;
     b0=b;
    }
    b1=b; 
    udelay(1);
   }
   local_irq_restore(flags);
   return capture_length;
}

int capture_read (void) {
  if (capture_pointer < capture_length) {
    return capture_buf[capture_pointer++];
  } else return -EINVAL;
}
#if 0
/* Register rw_grp2_cfg, scope bif_core, type rw */
typedef struct {
  unsigned int lw        : 6;
  unsigned int ew        : 3;
  unsigned int zw        : 3;
  unsigned int aw        : 2;
  unsigned int dw        : 2;
  unsigned int ewb       : 2;
  unsigned int bw        : 1;
  unsigned int wr_extend : 1;
  unsigned int erc_en    : 1;
  unsigned int mode      : 1;
  unsigned int dummy1    : 10;
} reg_bif_core_rw_grp2_cfg;
#define REG_RD_ADDR_bif_core_rw_grp2_cfg 4
#define REG_WR_ADDR_bif_core_rw_grp2_cfg 4
   reg_bif_core_rw_grp3_cfg bif_cfg = REG_RD(bif_core, regi_bif_core, rw_grp3_cfg);
   REG_WR(bif_core, regi_bif_core, rw_grp3_cfg, bif_cfg);


#endif





int fpga_io_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg){
  reg_bif_core_rw_grp1_cfg csr1_cfg;
  reg_bif_core_rw_grp2_cfg csr2_cfg;
  reg_bif_core_rw_grp3_cfg csr3_cfg;
  reg_bif_core_rw_grp4_cfg csr4_cfg;
//  unsigned long flags;
//  int i1;
  int d;
   D(printk("csp0rw_ioctl cmd= %x, arg= %x\n\r",cmd,arg));
   D(printk("csp0rw_ioctl:  ((int *)file->private_data)[0]= %x\n\r",((int *)file->private_data)[0]));
  D(printk("fpga_io.c:fpga_io_ioctl:_IOC_NR(cmd)=%x\n",(int) _IOC_NR(cmd)));
        switch (_IOC_TYPE(cmd)) {

                case FPGACONF_READREG:
                        d=(int)port_csp0_addr[_IOC_NR(cmd)];
                         D(printk ("port_csp0_addr[%x]=%x\n",(int) _IOC_NR(cmd),d));
                        return d;
                case FPGACONF_READREG_L:
                        d=(int)port_csp0_addr[_IOC_NR(cmd)] & 0x0000ffff;
                         D(printk ("port_csp0_addr[%x]=%x\n",(int) _IOC_NR(cmd),d));
                        return d;
                case FPGACONF_READREG_H:
                        d=((int)port_csp0_addr[_IOC_NR(cmd)]>>16) & 0x0000ffff;
                         D(printk ("port_csp0_addr[%x]=%x\n",(int) _IOC_NR(cmd),d));
                        return d;
                case FPGACONF_READREG4:
                        d=(int)port_csp4_addr[_IOC_NR(cmd)];
                         D(printk ("port_csp4_addr[%x]=%x\n",(int) _IOC_NR(cmd),d));
                        return d;
                case FPGACONF_READREG_L4:
                        return (long ) ( port_csp4_addr[_IOC_NR(cmd)] & 0x0000ffff);
                case FPGACONF_READREG_H4:
                        return (long ) ((port_csp4_addr[_IOC_NR(cmd)]>>16) & 0x0000ffff);

                case FPGACONF_WRITEREG:
                        if (_IOC_NR(cmd)==0) arg |= ((arg & 0x40000000)<<1);    // control MSB of CR
//                      return (long )   port_csp0_addr[_IOC_NR(cmd)]=arg; // read back after write
                        port_csp0_addr[_IOC_NR(cmd)]=arg;
                        return (long )   arg;
                case FPGACONF_WRITEREG4:
//                      return (long )   port_csp4_addr[_IOC_NR(cmd)]=arg; // read back after write
                        port_csp4_addr[_IOC_NR(cmd)]=arg;
                        return (long )  arg;
      case FPGACONF_WR_WAITSTATES:
         ((int *) &csr1_cfg)[0]=arg;
         ((int *) &csr2_cfg)[0]=arg;
         ((int *) &csr3_cfg)[0]=arg;
         ((int *) &csr4_cfg)[0]=arg;
         switch (_IOC_NR(cmd)) {
           case 1:
            REG_WR(bif_core, regi_bif_core, rw_grp1_cfg, csr1_cfg); // and fall through
            break;
           case 2:
            REG_WR(bif_core, regi_bif_core, rw_grp2_cfg, csr2_cfg); // and fall through
            break;
           case 3:
            REG_WR(bif_core, regi_bif_core, rw_grp3_cfg, csr3_cfg); // and fall through
            break;
           case 4:
            REG_WR(bif_core, regi_bif_core, rw_grp4_cfg, csr4_cfg); // and fall through
            break;
           default:
            printk ("address should be 1,2,3, or 4\n");
            return -EINVAL;
         }
                case FPGACONF_RD_WAITSTATES:
         switch (_IOC_NR(cmd)) {
           case 1:
            csr1_cfg=REG_RD(bif_core, regi_bif_core, rw_grp1_cfg);
            d=((int *) &csr1_cfg)[0];
            break;
           case 2:
            csr2_cfg=REG_RD(bif_core, regi_bif_core, rw_grp2_cfg);
            d=((int *) &csr2_cfg)[0];
            break;
           case 3:
            csr3_cfg=REG_RD(bif_core, regi_bif_core, rw_grp3_cfg);
            d=((int *) &csr3_cfg)[0];
            break;
           case 4:
            csr4_cfg=REG_RD(bif_core, regi_bif_core, rw_grp4_cfg);
            d=((int *) &csr4_cfg)[0];
            break;
           default:
             printk ("address should be 1,2,3, or 4\n");
             return -EINVAL;
         }
                        printk ("rw_grp%d_cfg=%x\n",_IOC_NR(cmd),d);
                        return d;
      case FPGACONF_CANON_IOBYTE:
         return canon_lens_io (arg); // second agrument - mask. 0 will be the same as 0xff
      case FPGACONF_START_CAPTURE:
         return capture_pins (arg, _IOC_NR(cmd)); // second agrument - mask. 0 will be the same as 0xff
      case FPGACONF_READ_CAPTURE:
         return capture_read();
      default:
         return -EINVAL;
      }
  return 0;
}

loff_t  fpga_io_lseek  (struct file * file, loff_t offset, int orig) {
   size_t size=0x4000; 
   switch (orig) {
   case SEEK_SET:
      file->f_pos = offset;
      break;
   case SEEK_CUR:
      file->f_pos += offset;
      break;
   case SEEK_END:
      file->f_pos = size + offset;
      break;
   default:
      return -EINVAL;
   }
   /* truncate position */
   if (file->f_pos < 0) {
      file->f_pos = 0;
      return (-EOVERFLOW);
   }
   if (file->f_pos > size) {
      file->f_pos = size;
      return (-EOVERFLOW);
   }
   D(printk("fpga_io_lseek, file->f_pos= 0x%x\n", (int) file->f_pos));
   return (file->f_pos);
}





ssize_t fpga_io_read   (struct file * file, char * buf, size_t count, loff_t *off){
  int l;
  unsigned long rbuf[1024]; // up to 4096 bytes/read
 D(printk("fpga_io_read: buf address=%lx count=%lx *offs=%lx\r\n", (long) buf, (long) count, (long) *off));
  if (count > sizeof(rbuf)) count =sizeof(rbuf);
  for (l=0; (l<<2) < count; l++)
   rbuf[l]=((*off) & 0x2000)?
            (unsigned long) port_csp4_addr[(*off) & 0x1fff]:
            (unsigned long) port_csp0_addr[(*off) & 0x1fff];
   if (copy_to_user(buf,rbuf,count)) return -EFAULT;
  return count;
}


ssize_t fpga_io_write  (struct file * file, const char * buf, size_t count, loff_t *off){
  int l,n;
  unsigned long wbuf[1024]; // up to 4096 bytes/write
  D(printk("fpga_io_write: buf address=%lx count=%lx *offs=%lx\r\n",(long) buf, (long) count, (long) *off));
  if (count > sizeof(wbuf)) count =sizeof(wbuf);
  n=count>>2;
  if (count & 3) {
     wbuf[count>>2]=0; 
     n++;
  }
  if (copy_from_user(wbuf,buf,count)) return -EFAULT;
  if ((*off) & 0x2000) for (l=0; l < n; l++)  port_csp4_addr[(*off) & 0x1fff]= wbuf[l];
  else                 for (l=0; l < n; l++)  port_csp0_addr[(*off) & 0x1fff]= wbuf[l];
  return count;
}


#define FPGA_TABLE_CHUNK 64 // up to 64 words to send to the table/from histogram on a single IRQ-off transfer
void fpga_table_write_nice (int addr, int len, unsigned long * data) {
  unsigned long flags;
  int l,i;
  MDF12(printk("addr=0x%x, len=0x%x, data=0x%08lx 0x%08lx 0x%08lx 0x%08lx...\n", addr, len, data[0], data[1], data[2], data[3]));
  while (len>0) {
    l=(len < FPGA_TABLE_CHUNK)?len:FPGA_TABLE_CHUNK;
    local_irq_save(flags);
    port_csp0_addr[X313_WA_COMP_TA]=addr; // open fpga for writing table(s)
    for (i=0; i<l; i++) port_csp0_addr[X313_WA_COMP_TD]=data[i]; 
    local_irq_restore(flags);
    len  -=l;
    addr +=l;
    data +=l;
  }
}

void fpga_hist_read_nice (int addr, int len, unsigned long * data) {
  unsigned long flags;
  int l,i;
  MDF13(printk("addr=0x%x, len=0x%x, ",addr, len));
  while (len>0) {
    l=(len < FPGA_TABLE_CHUNK)?len:FPGA_TABLE_CHUNK;
    local_irq_save(flags);
//  #define   X313_WA_HIST_ADDR   0x44
//  #define   X313_RA_HIST_DATA   0x45  /// use CSP4 with wait cycles to have a pulse
    port_csp0_addr[X313_WA_HIST_ADDR]=addr; 
    X3X3_AFTERWRITE ; 
    for (i=0; i<l; i++) data[i]=port_csp4_addr[X313_RA_HIST_DATA]; 
    local_irq_restore(flags);
    len  -=l;
    addr +=l;
    data +=l;
  }
  D13(printk("data=0x%08lx 0x%08lx 0x%08lx 0x%08lx...\n", data[0], data[1], data[2], data[3]));
}

ssize_t fpga_io_table_write  (struct file * file, const char * buf, size_t count, loff_t *off) {
  unsigned long p;
  char * fpga_tables_char= (char *)  fpga_tables_buffer;
  int sa,l;
  D(printk("fpga_io_table_write, count= %x\n", (int) count));
  p = *off;
  if (p >= (CX313_FPGA_TABLES_SIZE<<2))  p = (CX313_FPGA_TABLES_SIZE<<2);
  if( (p + count) > (CX313_FPGA_TABLES_SIZE<<2)) { // truncate count
    count = (CX313_FPGA_TABLES_SIZE<<2) - p;
  }
  D(printk("fpga_io_table_write, p=%x, count= %x\n", (int) p,(int) count));
  if (count) {
    if (copy_from_user(&fpga_tables_char[p],buf, count)) return -EFAULT;
    *off+=count;
    sa= p>>2;
    l=count>>2;
    fpga_table_write_nice (sa, l, &fpga_tables_buffer[sa]);
  }
  return count;
}


loff_t  fpga_io_table_lseek  (struct file * file, loff_t offset, int orig) {
  int l;
  l=(CX313_FPGA_TABLES_SIZE<<2);
  switch (orig)
  {
   case 0:
     file->f_pos = offset;
     break;
   case 1:
     file->f_pos += offset;
     break;
   case 2:
     file->f_pos = l + offset;
     break;
   default:
     return -EINVAL;
  }
  // truncate position
  if (file->f_pos < 0) {
    file->f_pos = 0;
    return(-EOVERFLOW);
  }
  if (file->f_pos > l) {
    file->f_pos = l;
  }
  return ( file->f_pos );
}

---