os/linux-2.6-tag--devboard-R2_10-4/arch/cris/arch-v32/drivers/elphel/quantization_tables.c

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/*!********************************************************************************
 *! FILE NAME  : quantization_tables.c
 *! DESCRIPTION: Generation and handling quantization tables:
 *! - direct - to be included in the JPEG headers and
 *! - reverse - to go to the FPGA. Reverse are calculated as 0x10000/direct
 *! Based on standard JPEG quality quantization tables, with the following differences
 *! - FPGA uses multiplication by 65536/x instead of division by x
 *! - (to better handle JP4 flavors) it is possible to use Y tables for other components
 *!    possibly with different quality.
 *!
 *! Quality is represented by 2-byte value. Each byte uses Y table if the value is Q<128,
 *! and C table with (Q-128) if it is Q>=128.
 *! If the High byte is zero, it is treated as Q^0x80  (Q|=(Q^0x80)<<8) for compatibility
 *!  with a standard single-byte Q value
 *! FPGA table accomodates 8 pairs of quantization coefficients, so software tries
 *! to reuse loaded tables when possible
 *!
 *! Copyright (C) 2008 Elphel, Inc.
 *! -----------------------------------------------------------------------------**
 *!
 *!  This program is free software: you can redistribute it and/or modify
 *!  it under the terms of the GNU General Public License as published by
 *!  the Free Software Foundation, either version 3 of the License, or
 *!  (at your option) any later version.
 *!
 *!  This program is distributed in the hope that it will be useful,
 *!  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *!  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *!  GNU General Public License for more details.
 *!  You should have received a copy of the GNU General Public License
 *!  along with this program.  If not, see <http://www.gnu.org/licenses/>.
 *! -----------------------------------------------------------------------------**
 *!  $Log: quantization_tables.c,v $
 *!  Revision 1.1.1.1  2008/11/27 20:04:01  elphel
 *!
 *!
 *!  Revision 1.8  2008/10/29 04:18:28  elphel
 *!  v.8.0.alpha10 made a separate structure for global parameters (not related to particular frames in a frame queue)
 *!
 *!  Revision 1.7  2008/10/23 08:08:41  elphel
 *!  reenabled irq in debug mode
 *!
 *!  Revision 1.6  2008/10/05 05:13:33  elphel
 *!  snapshot003
 *!
 *!  Revision 1.5  2008/09/12 00:24:00  elphel
 *!  removed cc353.c, cc353.h
 *!
 *!  Revision 1.4  2008/09/11 01:05:32  elphel
 *!  snapshot
 *!
 *!  Revision 1.3  2008/09/05 23:20:26  elphel
 *!  just a snapshot
 *!
 *!  Revision 1.2  2008/07/27 23:25:07  elphel
 *!  next snapshot
 *!
 *!  Revision 1.1  2008/06/08 23:46:45  elphel
 *!  added drivers files for handling quantization tables, gamma tables and the histograms
 *!
 *!
 */

//copied from cxi2c.c - TODO:remove unneeded 

#include <linux/module.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/autoconf.h>
#include <linux/vmalloc.h>

#include <asm/system.h>
#include <asm/byteorder.h> // endians
#include <asm/io.h>

#include <asm/irq.h>

#include <asm/delay.h>
#include <asm/uaccess.h>
#include <asm/elphel/c313a.h>
#include <asm/elphel/exifa.h>
#include "fpgactrl.h"  // defines port_csp0_addr, port_csp4_addr 
//#include "cc3x3.h"
#include "fpga_io.h"

#include "x3x3.h" // just for FPGA_NQTAB

#include "framepars.h"
//#include "fpga_io.h"//fpga_table_write_nice

#include "quantization_tables.h"

#if ELPHEL_DEBUG
  #define D15(x) { if (GLOBALPARS(G_DEBUG) & (1 <<15)) { x ;} }
  #define MDF15(x) { if (GLOBALPARS(G_DEBUG) & (1 <<15)) {printk("%s:%d:%s ",__FILE__,__LINE__,__FUNCTION__);x ;} }
  #define D14(x) { if (GLOBALPARS(G_DEBUG) & (1 <<14)) { x ;} }
  #define MDF14(x) { if (GLOBALPARS(G_DEBUG) & (1 <<14)) {printk("%s:%d:%s ",__FILE__,__LINE__,__FUNCTION__);x ;} }
  #define MDF(x) {printk("%s:%d:%s ",__FILE__,__LINE__,__FUNCTION__);x ;}
//  #define D1I(x)
  #define D1I(x) x
#else
  #define D1I(x) x
  #define D15(x)
  #define MDF15(x)
  #define D14(x)
  #define MDF14(x)
  #define MDF(x)
#endif


#define QTABLE_SIZE 64 
#define QTABLE_HEAD_CACHE 8 
   static unsigned int std_quant_tbls[2 * QTABLE_SIZE] = { 

    16,  11,  10,  16,  24,  40,  51,  61,
    12,  12,  14,  19,  26,  58,  60,  55,
    14,  13,  16,  24,  40,  57,  69,  56,
    14,  17,  22,  29,  51,  87,  80,  62,
    18,  22,  37,  56,  68, 109, 103,  77,
    24,  35,  55,  64,  81, 104, 113,  92,
    49,  64,  78,  87, 103, 121, 120, 101,
    72,  92,  95,  98, 112, 100, 103,  99,

    17,  18,  24,  47,  99,  99,  99,  99,
    18,  21,  26,  66,  99,  99,  99,  99,
    24,  26,  56,  99,  99,  99,  99,  99,
    47,  66,  99,  99,  99,  99,  99,  99,
    99,  99,  99,  99,  99,  99,  99,  99,
    99,  99,  99,  99,  99,  99,  99,  99,
    99,  99,  99,  99,  99,  99,  99,  99,
    99,  99,  99,  99,  99,  99,  99,  99
  };

static unsigned char  qtable_cache [QTABLE_SIZE * 2 * QTABLE_HEAD_CACHE]; 
static int            qtable_cache_values [QTABLE_HEAD_CACHE]; 
static int            qtable_cache_next[QTABLE_HEAD_CACHE] ; 
static int            qtable_cache_mre; 

static int            qtable_fpga_values [FPGA_NQTAB]; 
static int            qtable_fpga_next[FPGA_NQTAB] ; 
static int            qtable_fpga_mre; 

static int            qtable_cache_initialized;
static int            qtable_fpga_initialized;

void reset_qtables(void) {
 qtable_cache_initialized=0;
 qtable_fpga_initialized=0;
}


void init_qtable_head_cache (void) {
  D1I(unsigned long flags);
  int i;
  MDF(printk("\n"));
  D1I(local_irq_save(flags));
  for (i=0; i < QTABLE_HEAD_CACHE; i++) {
    qtable_cache_values[i]=-1; 
    qtable_cache_next[i]=i+1; 
    qtable_cache_mre=0;
  }
  qtable_cache_initialized=1;
  D1I(local_irq_restore(flags));
}

int get_qtable (int quality2, unsigned char *y_tab, unsigned char *c_tab) {
  D1I(unsigned long flags);
  int i,cache_index,cache_index_prev,q_type,quality,temp,tstart;
  int rslt=0;
  unsigned char * tab;
  const unsigned int zig_zag[QTABLE_SIZE] = {
       0, 1, 5, 6,14,15,27,28,
       2, 4, 7,13,16,26,29,42,
       3, 8,12,17,25,30,41,43,
       9,11,18,24,31,40,44,53,
      10,19,23,32,39,45,52,54,
      20,22,33,38,46,51,55,60,
      21,34,37,47,50,56,59,61,
      35,36,48,49,57,58,62,63   
   };
  if (qtable_cache_initialized==0) init_qtable_head_cache();


  MDF14(printk("quality2=0x%x\n",quality2));
  if (quality2<0) return -1;
  if (quality2<256) quality2 |= (quality2^0x80)<<8;
  MDF14(printk("quality2=0x%x\n",quality2));
  D1I(local_irq_save(flags));
  cache_index=qtable_cache_mre;
  cache_index_prev=-1;
  for (i=0; (i<(QTABLE_HEAD_CACHE-1)) && (qtable_cache_values[cache_index] != quality2) && (qtable_cache_values[cache_index]>=0); i++) {
   cache_index_prev=cache_index;
   cache_index=qtable_cache_next[cache_index];
  D14(printk("    ---i=%d, cache_index_prev=%d, cache_index=%d\n",i, cache_index_prev, cache_index));
  }
  if (i==(QTABLE_HEAD_CACHE-1)) { 
    qtable_cache_next[cache_index_prev]=qtable_cache_mre;
    qtable_cache_mre=cache_index_prev;
  MDF14(printk("qtable_cache_mre=%d\n",qtable_cache_mre));
  } else if (cache_index_prev>=0){ 
    qtable_cache_next[cache_index_prev]=qtable_cache_next[cache_index]; 
    qtable_cache_next[cache_index]=qtable_cache_mre; 
    qtable_cache_mre=cache_index; 
  MDF14(printk("qtable_cache_mre=%d\n",qtable_cache_mre));
  }
  if (qtable_cache_values[qtable_cache_mre] != quality2) { 
    rslt=1;
    for (q_type=0;q_type<2;q_type++) { //Y/C
      quality=(quality2>>(q_type?8:0)) & 0xff;
      tstart=(quality & 0x80)?QTABLE_SIZE:0;
      tab = & qtable_cache [QTABLE_SIZE * (2 * qtable_cache_mre + q_type)];
      quality &= 0x7f;
  MDF14(printk("tstart=%d, quality=%d\n",tstart,quality));
      if(quality <= 0)
        quality = 1;
      if(quality > 100)
        quality = 100;
      if(quality < 50)
        quality = 5000 / quality;
      else
        quality = 200 - quality * 2;
  MDF14(printk("q_type=%d, quality=%d\n",q_type,quality));
      for(i = 0; i < QTABLE_SIZE; i++) {
        temp = (std_quant_tbls[i+tstart] * quality + 50) / 100;
        if(temp <= 0) temp = 1;
        if(temp > 255) temp = 255;
        tab[zig_zag[i]]=temp;
      }
    }
  } 

  if (y_tab) memcpy (y_tab, & qtable_cache [QTABLE_SIZE * (2 * qtable_cache_mre + 0)],QTABLE_SIZE) ;
  if (c_tab) memcpy (c_tab, & qtable_cache [QTABLE_SIZE * (2 * qtable_cache_mre + 1)],QTABLE_SIZE) ;
  D1I(local_irq_restore(flags));
  MDF14(printk("y_tab=0x%x, c_tab=0x%x, rslt=%d\n",(int) y_tab, (int) c_tab, rslt));
  MDF15(if (y_tab) {printk("y_tab\n"); for (i=0;i<64;i++){if ((i & 7)==0) printk("\n");printk(" %02x",(int) y_tab[i]);} printk("\n");});
  MDF15(if (c_tab) {printk("c_tab\n"); for (i=0;i<64;i++){if ((i & 7)==0) printk("\n");printk(" %02x",(int) c_tab[i]);} printk("\n");});
  return rslt;
}
#if 0
//Initialize quantization tables cache/FPGA
   init_qtable_head_cache();
   init_qtable_fpga();
#endif

void init_qtable_fpga(void) {
  D1I(unsigned long flags);
  int i;
  MDF14(printk("\n"));
  D1I(local_irq_save(flags));  
  for (i=0; i < FPGA_NQTAB; i++) {
    qtable_fpga_values[i]=-1; // undefined
    qtable_fpga_next[i]=i+1; // last value is invalid, but that's OK - it should not be used
    qtable_fpga_mre=0;
  }
  qtable_fpga_initialized=1;
  D1I(local_irq_restore(flags));
}

int set_qtable_fpga(int quality2) {
  D1I(unsigned long flags);
  int i,fpga_index,fpga_index_prev,q_type,quality,temp,tstart;
  unsigned short qtable_fpga[QTABLE_SIZE *2];
  unsigned short * tab;
  if (qtable_fpga_initialized==0) init_qtable_fpga();
  if (quality2<0) return -1;
  if (quality2<256) quality2 |= (quality2 ^ 0x80)<<8;
  MDF14(printk("quality2=0x%x\n",quality2)); // d050
  D1I(local_irq_save(flags));
  fpga_index=qtable_fpga_mre;
  fpga_index_prev=-1;
  for (i=0; (i<(FPGA_NQTAB-1)) && (qtable_fpga_values[fpga_index] != quality2) && (qtable_fpga_values[fpga_index]>=0); i++) {
   fpga_index_prev=fpga_index;
   fpga_index=qtable_fpga_next[fpga_index];
  D14(printk("    ---i=%d, fpga_index_prev=%d, fpga_index=%d\n",i, fpga_index_prev, fpga_index)); 

  }
  if (i==(FPGA_NQTAB-1)) { 
    qtable_fpga_next[fpga_index_prev]=qtable_fpga_mre;
    qtable_fpga_mre=fpga_index_prev;
  MDF14(printk("qtable_fpga_mre=%d\n",qtable_fpga_mre));  
  } else if (fpga_index_prev>=0) { 
    qtable_fpga_next[fpga_index_prev]=qtable_fpga_next[fpga_index]; 
    qtable_fpga_next[fpga_index]=qtable_fpga_mre; 
    qtable_fpga_mre=fpga_index; 
  MDF14(printk("qtable_fpga_mre=%d\n",qtable_fpga_mre));  
  }
  if (qtable_fpga_values[qtable_fpga_mre] != quality2) { 
    for (q_type=0;q_type<2;q_type++) { //Y/C
      quality=(quality2>>(q_type?8:0)) & 0xff;
  MDF14(printk("q_type=%d, quality=%d quality2=0x%x\n",q_type,quality,quality2));
      tstart=(quality & 0x80)?QTABLE_SIZE:0;
      tab = &qtable_fpga [QTABLE_SIZE * q_type];
      quality &= 0x7f;
  MDF14(printk("tstart=%d, quality=%d\n",tstart,quality)); //0, 1 - both times
      if(quality <= 0)
        quality = 1;
      if(quality > 100)
        quality = 100;
      if(quality < 50)
        quality = 5000 / quality;
      else
        quality = 200 - quality * 2;
  MDF14(printk("q_type=%d, quality=%d\n",q_type,quality));
      for(i = 0; i < QTABLE_SIZE; i++) {
        temp = (std_quant_tbls[i+tstart] * quality + 50) / 100;
        D15(if ((i & 7)==0) printk("\n");if (i==0) printk("\n");printk(" %08x",(int) temp));
        if(temp <= 0) temp = 1;
        if(temp > 255) temp = 255;
        temp = ((0x20000/temp) + 1) >> 1;
        if(temp > 0xffff) temp = 0xffff;
        tab[i]=temp;
      }
    }
    D15(printk("\n"));
    fpga_table_write_nice (CX313_FPGA_TABLES_QUANT+qtable_fpga_mre*QTABLE_SIZE, QTABLE_SIZE, (unsigned long *) qtable_fpga);
    MDF15(for (i=0;i<128;i++){if ((i & 7)==0) printk("\n");if ((i & 63)==0) printk("\n");printk(" %04x",(int) qtable_fpga[i]);} printk("\n"));
    MDF15(for (i=0;i<128;i++){if ((i & 7)==0) printk("\n");if ((i & 63)==0) printk("\n");printk(" %04x",std_quant_tbls[i]);} printk("\n"));
  } 

  D1I(local_irq_restore(flags));
  MDF14(printk("qtable_fpga_mre=%d\n",qtable_fpga_mre));
  return qtable_fpga_mre;
}

---