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Defines |
#define | X313_MINMODREV 0x03534000 |
#define | X313_MAXMODREV 0x035340ff |
#define | X313__RA__STATUS 0x10 |
#define | X313__RA__IRQS 0x11 |
#define | X313__RA__TRIGPH 0x12 |
#define | X313__RA__MODEL 0x13 |
#define | X313__RA__TABLE 0x14 |
#define | X313__RA__XFERCNTR 0x14 |
#define | X313__RA__HIGHFREQ 0x15 |
#define | X313__RA__IOPINS 0x70 |
#define | X313__RA__SENSFPGA 0x74 |
#define | SFPGA_RD_BIT 16 |
#define | I2C_FRAME_NUMBER 0x16 |
#define | X313__RA__SDCH0 0x20 |
#define | X313__RA__SDCH1 0x24 |
#define | X313__RA__SDCH2 0x28 |
#define | X313__RA__SDCH3 0x2c |
#define | X313__RA__SDBUF3 0x30 |
#define | X313_SR__CLK_LOCKED 28 |
#define | X313_SR__SENS_DCM_OVFL 27 |
#define | X313_SR__SENS_DCM_LOCKED 26 |
#define | X313_SR__SENS_DCM_RDY 25 |
#define | X313_SR__SENS_DCM_EARLY 24 |
#define | X313_SR__SENS_DCM_LATE 23 |
#define | X313_SR__SENS_DCM_ERROR 24 |
#define | X313_SR__SENS_DCM_LATE 23 |
#define | X313_SENSOR_PHASE ((port_csp0_addr[X313__RA__STATUS] >> X313_SR__SENS_DCM_LATE ) & 3) |
#define | X313_SR__DCM_OVFL 22 |
#define | X313_SR__DCM_LOCKED 21 |
#define | X313_SR__DCM_RDY 20 |
#define | X313_SR__DCM_EARLY 19 |
#define | X313_SR__DCM_LATE 18 |
#define | X313_SR__DMA_EMPTY 17 |
#define | X313_SR__DONE_CMPRS 16 |
#define | X313_SR__DONE_CI 15 |
#define | X313_SR__DCCRDY 14 |
#define | X313_SR__DONE 13 |
#define | X313_SR__SENST1 12 |
#define | X313_SR__SENST0 11 |
#define | X313_SR__NXTFR3 10 |
#define | X313_SR__NXTFR2 9 |
#define | X313_SR__NXTFR1 8 |
#define | X313_SR__NXTFR0 7 |
#define | X313_SR__PIOWEMPTY 6 |
#define | X313_SR__PIORDY 5 |
#define | X313_SR__CH2RDY 4 |
#define | X313_SR__CH1RDY 3 |
#define | X313_SR__CH0RDY 2 |
#define | X313_SR__SCL0 1 |
#define | X313_SR__SDA0 0 |
#define | X313_PIOR__SCL1 0 |
#define | X313_PIOR__SDA1 1 |
#define | X313_PIOR__XRST 2 |
#define | X313_PIOR__AUXCLK 3 |
#define | X313_PIOR__EXPS 4 |
#define | X313_PIOR__TRIG 5 |
#define | X313_SR__X323_SI 0 |
#define | X313_SR(x) ((port_csp0_addr[X313__RA__STATUS] >> X313_SR__##x ) & 1) |
#define | X313_PIOR(x) ((port_csp0_addr[X313__RA__IOPINS] >> X313_PIOR__##x ) & 1) |
#define | X313_IR__VACT 0 |
#define | X313_IR__XINT 1 |
#define | X313_IR__XFEROVR 2 |
#define | X313_IR__DONE 3 |
#define | X313_IR__EOT 4 |
#define | X313_IR__DCC 5 |
#define | X313_IR__DONE_INPUT 6 |
#define | X313_IR__DONE_COMPRESS 7 |
#define | X313_IR__SMART 8 |
#define | X313_IR(x) ((port_csp0_addr[X313__RA__IRQS] >> ( X313_IR__##x ) + 8) & 1) |
#define | EN_INTERRUPT(x) port_csp0_addr[X313_WA_IRQ_ENA]= (1<< ( X313_IR__##x )) |
#define | DIS_INTERRUPT(x) {port_csp0_addr[X313_WA_IRQ_DIS]= (1<< ( X313_IR__##x ) ); port_csp0_addr[X313_WA_IRQ_RST]= (1<< ( X313_IR__##x ) );} |
#define | DIS_INTERRUPTS {port_csp0_addr[X313_WA_IRQ_DIS]= 0xffff; port_csp0_addr[X313_WA_IRQ_RST]= 0xffff;} |
#define | X313_WA_WCTL 0 |
#define | X313_WA_DMACR 1 |
#define | X313_WA_SENSFPN 2 |
#define | X313_SENSFPN_D(t, s, m, d, l) |
#define | X313_WA_VIRTTRIG 3 |
#define | X313_WA_TRIG 4 |
#define | X313_WA_NLINES 5 |
#define | X313_WA_WCTL24 6 |
#define | X313_WA_DCDC 7 |
#define | X313_WA_DCM 8 |
#define | X3X3_RSTSENSDCM {port_csp0_addr[X313_WA_DCM]=0xf0;} |
#define | X3X3_SENSDCM_INC90 {port_csp0_addr[X313_WA_DCM]=0x80;} |
#define | X3X3_SENSDCM_DEC90 {port_csp0_addr[X313_WA_DCM]=0x40;} |
#define | X3X3_SENSDCM_INC {port_csp0_addr[X313_WA_DCM]=0x20;} |
#define | X3X3_SENSDCM_DEC {port_csp0_addr[X313_WA_DCM]=0x10;} |
#define | X3X3_SENSDCM_NOP {port_csp0_addr[X313_WA_DCM]=0x0;} |
#define | X313_WA_COLOR_SAT 9 |
#define | DEFAULT_COLOR_SATURATION_BLUE 0x90 |
#define | DEFAULT_COLOR_SATURATION_RED 0xb6 |
#define | X313_WA_FRAMESYNC_DLY 0x0a |
#define | X313_WA_QUANTIZER_MODE 0x0b |
#define | X313_WA_COMP_CMD 0x0c |
#define | COMPCMD_FOCUS(x) ((1<<23) | (((x) & 3) << 21)) |
#define | COMPCMD_BAYERSHIFT(x) ((1<<20) | (((x) & 3) << 18)) |
#define | COMPCMD_TILESHIFT(x) ((1<<17) | (((x) & 7) << 14)) |
#define | COMPCMD_DEMOS(x) ((1<<13) | (((x) & 0x0f) << 9)) |
#define | DEMOS_MONO6 0 |
#define | DEMOS_COLOR18 1 |
#define | DEMOS_JP46 2 |
#define | DEMOS_JP46DC 3 |
#define | DEMOS_COLOR20 4 |
#define | DEMOS_JP4 5 |
#define | DEMOS_JP4DC 6 |
#define | DEMOS_JP4DIFF 7 |
#define | DEMOS_JP4HDR 8 |
#define | DEMOS_JP4DIFF2 9 |
#define | DEMOS_JP4HDR2 10 |
#define | DEMOS_MONO4 14 |
#define | COMPCMD_DCSUB(x) ((1<<8) | (((x) & 1) << 7)) |
#define | COMPCMD_QTAB(x) ((1<<6) | (((x) & 7) << 3)) |
#define | FPGA_NQTAB 8 |
#define | COMPCMD_RESET 4 |
#define | COMPCMD_STOP 5 |
#define | COMPCMD_SINGLE 6 |
#define | COMPCMD_RUN 7 |
#define | X313_WA_COMP_TA 0x0e |
#define | X313_WA_COMP_TD 0x0f |
#define | X313_WA_MCUNUM 0x0d |
#define | X313_WA_SMART_IRQ 0x1a |
| FIXME: (in FPGA) - now if "smart" mode is disabled, VACT will not cause interrupt on smart bit. So smart mode will be always enabled for now.
|
#define | X313_WA_DCM_RST 0x1b |
#define | X313_WA_IRQ_RST 0x1c |
#define | X313_WA_IRQ_DIS 0x1d |
#define | X313_WA_IRQ_ENA 0x1e |
#define | X313_WA_IRQ_WVECT 0x1f |
#define | EN_INTERRUPT(x) port_csp0_addr[X313_WA_IRQ_ENA]= (1<< ( X313_IR__##x )) |
#define | DIS_INTERRUPT(x) {port_csp0_addr[X313_WA_IRQ_DIS]= (1<< ( X313_IR__##x ) ); port_csp0_addr[X313_WA_IRQ_RST]= (1<< ( X313_IR__##x ) );} |
#define | DIS_INTERRUPTS {port_csp0_addr[X313_WA_IRQ_DIS]= 0xffff; port_csp0_addr[X313_WA_IRQ_RST]= 0xffff;} |
#define | X313_WA_HIST_LEFT 0x40 |
#define | X313_WA_HIST_TOP 0x41 |
#define | X313_WA_HIST_WIDTH 0x42 |
#define | X313_WA_HIST_HEIGHT 0x43 |
#define | X313_WA_HIST_ADDR 0x44 |
#define | X313_RA_HIST_DATA 0x45 |
#define | X313_WA_RTC_USEC 0x48 |
#define | X313_WA_RTC_SEC 0x49 |
#define | X313_WA_RTC_CORR 0x4a |
#define | X313_WA_RTC_LATCH 0x4b |
#define | X313_RA_RTC_USEC 0x48 |
#define | X313_RA_RTC_SEC 0x49 |
#define | X313_WA_TIMESTAMP 0x4c |
#define | X313_TIMESTAMPLEN 28 |
#define | X313_WA_DCR0 0x4e |
#define | X313_WA_DCR1 0x4f |
#define | X353_DCR0(x, y) (((((y) & ((1 << X353DCR0__##x##__WIDTH)-1))) | (1 << X353DCR0__##x##__WIDTH) ) << X353DCR0__##x##__BITNM) |
#define | X353_DCR1(x, y) (((((y) & ((1 << X353DCR1__##x##__WIDTH)-1))) | (1 << X353DCR1__##x##__WIDTH) ) << X353DCR1__##x##__BITNM) |
#define | X353DCR0__BAYER_PHASE__BITNM 0 |
| ============ X313_WA_DCR0 ==============
|
#define | X353DCR0__BAYER_PHASE__WIDTH 2 |
#define | X353DCR0__FILLFACTORY__BITNM 3 |
#define | X353DCR0__FILLFACTORY__WIDTH 1 |
#define | X353DCR0__DLYHOR__BITNM 5 |
#define | X353DCR0__DLYHOR__WIDTH 1 |
#define | X353DCR0__NEGRST__BITNM 7 |
#define | X353DCR0__NEGRST__WIDTH 1 |
#define | X353DCR0__SKIPLINEL__BITNM 9 |
#define | X353DCR0__SKIPLINE__WIDTH 1 |
#define | X353DCR0__XT_POL__BITNM 11 |
#define | X353DCR0__XT_POL__WIDTH 1 |
#define | X353DCR0__ARST__BITNM 13 |
#define | X353DCR0__ARST__WIDTH 1 |
#define | X353DCR0__ARO__BITNM 15 |
#define | X353DCR0__ARO__WIDTH 1 |
#define | X353DCR0__CNVEN__BITNM 17 |
#define | X353DCR0__CNVEN__WIDTH 1 |
#define | X353DCR0__SENSTRIGEN__BITNM 19 |
#define | X353DCR0__SENSTRIGEN__WIDTH 1 |
#define | X353DCR1__MRST__BITNM 0 |
| ============ X313_WA_DCR1 ==============
|
#define | X353DCR1__MRST__WIDTH 1 |
#define | X353DCR1__EARLYTRIG__BITNM 2 |
#define | X353DCR1__EARLYTRIG__WIDTH 1 |
#define | X353DCR1__DCLKMODE__BITNM 4 |
#define | X353DCR1__DCLKMODE__WIDTH 1 |
#define | X353DCR1__PXD14__BITNM 6 |
#define | X353DCR1__PXD14__WIDTH 1 |
#define | X353DCR1__HACT_PHASE__BITNM 8 |
#define | X353DCR1__HACT_PHASE__WIDTH 2 |
#define | X353DCR1__PCLKSRC__BITNM 11 |
#define | X353DCR1__PCLKSRC__WIDTH 2 |
#define | X353DCR1__HFCOMP__BITNM 14 |
#define | X353DCR1__HFCOMP__WIDTH 3 |
#define | X353DCR1__BLOCKVSYNC__BITNM 18 |
#define | X353DCR1__BLOCKVSYNC__WIDTH 1 |
#define | CCAM_ARO_ON port_csp0_addr[X313_WA_DCR0]=X353_DCR0(ARO,1) |
#define | CCAM_ARO_OFF port_csp0_addr[X313_WA_DCR0]=X353_DCR0(ARO,0) |
#define | CCAM_DCLK_OFF port_csp0_addr[X313_WA_DCR1]=X353_DCR1(DCLKMODE,1) |
| turn clock to sensor on/off (default - on)
|
#define | CCAM_DCLK_ON port_csp0_addr[X313_WA_DCR1]=X353_DCR1(DCLKMODE,0) |
#define | CCAM_ARST_OFF port_csp0_addr[X313_WA_DCR0]=X353_DCR0(ARST,1) |
#define | CCAM_ARST_ON port_csp0_addr[X313_WA_DCR0]=X353_DCR0(ARST,0) |
#define | CCAM_MRST_OFF port_csp0_addr[X313_WA_DCR1]=X353_DCR1(MRST,1) |
#define | CCAM_MRST_ON port_csp0_addr[X313_WA_DCR1]=X353_DCR1(MRST,0) |
#define | CCAM_NEGRST port_csp0_addr[X313_WA_DCR0]=X353_DCR0(NEGRST,1) |
#define | CCAM_POSRST port_csp0_addr[X313_WA_DCR0]=X353_DCR0(NEGRST,0) |
#define | CCAM_CNVEN_ON port_csp0_addr[X313_WA_DCR0]=X353_DCR0(CNVEN,1) |
| enable power converter control. *** Only if it is not MT9P001 !!! ***
|
#define | CCAM_CNVEN_OFF port_csp0_addr[X313_WA_DCR0]=X353_DCR0(CNVEN,0) |
#define | CCAM_TRIG_INT port_csp0_addr[X313_WA_DCR0]=X353_DCR0(SENSTRIGEN,0) |
| Sensor (MT9X001) trigger source selection (internal/external).
|
#define | CCAM_TRIG_EXT port_csp0_addr[X313_WA_DCR0]=X353_DCR0(SENSTRIGEN,1) |
#define | CCAM_TIMESTAMP_NORMAL port_csp0_addr[X313_WA_DCR1]=X353_DCR1(EARLYTRIG,0) |
| early/normal timestamp in async mode
|
#define | CCAM_TIMESTAMP_EARLY port_csp0_addr[X313_WA_DCR1]=X353_DCR1(EARLYTRIG,1) |
#define | CCAM_SET_HACT_PHASE(x) port_csp0_addr[X313_WA_DCR1]=X353_DCR1(HACT_PHASE,(x)) |
| Set HACT phase (90 degrees increments - needed for MT9P001.
|
#define | CCAM_VSYNC_ON port_csp0_addr[X313_WA_DCR1]=X353_DCR1(BLOCKVSYNC,0) |
#define | CCAM_VSYNC_OFF port_csp0_addr[X313_WA_DCR1]=X353_DCR1(BLOCKVSYNC,1) |
#define | X313_I2C_FRAME0 0x50 |
| =============================
|
#define | X313_I2C_FRAME1 0x51 |
#define | X313_I2C_FRAME2 0x52 |
#define | X313_I2C_FRAME3 0x53 |
#define | X313_I2C_FRAME4 0x54 |
#define | X313_I2C_FRAME5 0x55 |
#define | X313_I2C_FRAME6 0x56 |
#define | X313_I2C_FRAME7 0x57 |
#define | X313_I2C_ASAP 0x58 |
#define | X313_I2C_NEXT 0x59 |
#define | X313_I2C_NEXT2 0x5a |
#define | X313_I2C_NEXT3 0x5b |
#define | X313_I2C_NEXT4 0x5c |
#define | X313_I2C_NEXT5 0x5d |
#define | X313_I2C_NEXT6 0x5e |
#define | X313_I2C_CMD 0x5f |
#define | X3X3_SET_I2C_DLY(x) (0x100 | ((x) & 0xff)) |
#define | X3X3_SET_I2C_BYTES(x) (0x800 | (((x)<<9) & 0x600)) |
#define | X3X3_I2C_RUN_BITS 0x3000 |
#define | X3X3_I2C_STOP_BITS 0x2000 |
#define | X3X3_I2C_RESET_BITS 0x4000 |
#define | X3X3_I2C_SCL_0_BITS 0x10000 |
| software control of SDA0, SCL0 lines (when hardware i2c is off)
|
#define | X3X3_I2C_SCL_1_BITS 0x20000 |
#define | X3X3_I2C_SCL_Z_BITS 0x30000 |
#define | X3X3_I2C_SDA_0_BITS 0x40000 |
#define | X3X3_I2C_SDA_1_BITS 0x80000 |
#define | X3X3_I2C_SDA_Z_BITS 0xc0000 |
#define | X3X3_I2C_IS_BUSY |
#define | X3X3_I2C_FRAME (port_csp0_addr[I2C_FRAME_NUMBER] & 0x7) |
#define | X3X3_I2C_SEND2(a, s, r, d) {port_csp0_addr[a] = ((s)<<24) | (((r) & 0xff) << 16) | ((d) & 0xffff) ; X3X3_AFTERWRITE ;} |
#define | X3X3_I2C_SEND1(a, s, r, d) {port_csp0_addr[a] = ((s)<<24) | (((r) & 0xff) << 16) | (((d) & 0xff) << 8) ; X3X3_AFTERWRITE ;} |
#define | X3X3_GAMMA_PAGE ((port_csp0_addr[I2C_FRAME_NUMBER] & 0x20000)?1:0) |
#define | X3X3_I2C_STOP_WAIT {port_csp0_addr[X313_I2C_CMD]=X3X3_I2C_STOP_BITS; while (X3X3_I2C_IS_BUSY) ; } |
| X3X3_I2C_STOP_WAIT does not stop frame counter - it still counts frame pulses.
|
#define | X3X3_I2C_RUN {port_csp0_addr[X313_I2C_CMD]=X3X3_I2C_RUN_BITS ; X3X3_AFTERWRITE ;} |
#define | X3X3_I2C_RESET_WAIT {port_csp0_addr[X313_I2C_CMD]=X3X3_I2C_RESET_BITS; while (X3X3_I2C_IS_BUSY) ; } |
#define | X313_SEQ_FRAME0 0x60 |
#define | X313_SEQ_FRAME1 0x61 |
#define | X313_SEQ_FRAME2 0x62 |
#define | X313_SEQ_FRAME3 0x63 |
#define | X313_SEQ_FRAME4 0x64 |
#define | X313_SEQ_FRAME5 0x65 |
#define | X313_SEQ_FRAME6 0x66 |
#define | X313_SEQ_FRAME7 0x67 |
#define | X313_SEQ_ASAP 0x68 |
#define | X313_SEQ_NEXT 0x69 |
#define | X313_SEQ_NEXT2 0x6a |
#define | X313_SEQ_NEXT3 0x6b |
#define | X313_SEQ_NEXT4 0x6c |
#define | X313_SEQ_NEXT5 0x6d |
#define | X313_SEQ_NEXT6 0x6e |
#define | X313_SEQ_CMD 0x6f |
#define | X3X3_SEQ_RUN_BITS 0x3000 |
#define | X3X3_SEQ_STOP_BITS 0x2000 |
#define | X3X3_SEQ_RESET_BITS 0x4000 |
#define | X3X3_SEQ_SEND1(f, a, d) {port_csp0_addr[f] = ((a)<<24) | ((d) & 0xffffff) ; X3X3_AFTERWRITE ;} |
#define | X3X3_SEQ_STOP {port_csp0_addr[X313_SEQ_CMD]=X3X3_SEQ_STOP_BITS;} |
#define | X3X3_SEQ_RUN {port_csp0_addr[X313_SEQ_CMD]=X3X3_SEQ_RUN_BITS ; X3X3_AFTERWRITE ;} |
#define | X3X3_SEQ_RESET {port_csp0_addr[X313_SEQ_CMD]=X3X3_SEQ_RESET_BITS; X3X3_AFTERWRITE ; X3X3_AFTERWRITE ; X3X3_AFTERWRITE ; X3X3_AFTERWRITE ; } |
#define | X313_WA_IOPINS 0x70 |
#define | X313_WA_SENSFPGA 0x74 |
#define | X313_WA_CAMSYNCTRIG 0x78 |
#define | X313_WA_CAMSYNCDLY 0x79 |
#define | X313_WA_CAMSYNCOUT 0x7a |
#define | X313_WA_CAMSYNCPER 0x7b |
#define | SFPGA_TDI_BIT 0x0 |
#define | SFPGA_TMS_BIT 0x2 |
#define | SFPGA_TCK_BIT 0x4 |
#define | SFPGA_PROG_BIT 0x6 |
#define | SFPGA_PGMEN_BIT 0x8 |
#define | SFPGA_RD_SENSPGMPIN 0x80000 |
#define | SFPGA_RD_TDO 0x90000 |
#define | SFPGA_RD_DONE 0xa0000 |
#define | X3X3_AFTERWRITE {if (!port_csp0_addr[X313__RA__MODEL]) printk ("model=0");} |
#define | x3x3_DELAY(x) {int iiii; for (iiii=0; iiii < (x); iiii++) X3X3_AFTERWRITE ; } |
#define | X313_WA_SDCH0_CTL0 0x20 |
#define | X313_WA_SDCH0_CTL1 0x21 |
#define | X313_WA_SDCH0_CTL2 0x22 |
#define | X313_WA_SD_MANCMD 0x23 |
#define | X313_WA_SDCH1_CTL0 0x24 |
#define | X313_WA_SDCH1_CTL1 0x25 |
#define | X313_WA_SDCH1_CTL2 0x26 |
#define | X313_WA_SD_MODE 0x27 |
#define | X313_WA_SDCH2_CTL0 0x28 |
#define | X313_WA_SDCH2_CTL1 0x29 |
#define | X313_WA_SDCH2_CTL2 0x2a |
#define | X313_WA_SDCH3_CTL0 0x2c |
#define | X313_WA_SDCH3_CTL1 0x2d |
#define | X313_WA_SDCH3_CTL2 0x2e |
#define | X313_WA_SDPIO_NEXT 0x2f |
#define | X313_WA_SD_PIOWIN 0x30 |
#define | X313_WA_LENSCORR 0x31 |
#define | X313_LENS_AX(x) ( 0x0 | ((x)& 0x7ffff)) |
#define | X313_LENS_AY(x) ( 0x80000 | ((x)& 0x7ffff)) |
#define | X313_LENS_C(x) (0x100000 | ((x)& 0x7ffff)) |
#define | X313_LENS_BX(x) (0x200000 | ((x)& 0x1fffff)) |
#define | X313_LENS_BY(x) (0x400000 | ((x)& 0x1fffff)) |
#define | X313_LENS_SCALES(color, x) (0x600000 | (((color)&3)<<17) | ((x)& 0x1ffff)) |
#define | X313_LENS_FATZERO_IN(x) (0x680000 | ((x)& 0xffff)) |
#define | X313_LENS_FATZERO_OUT(x) (0x690000 | ((x)& 0xffff)) |
#define | X313_LENS_POSTSCALE(x) (0x6a0000 | ((x)& 0x7)) |
#define | RD_SD_PIOWIN port_csp4_addr[X313_WA_SD_PIOWIN] |
#define | X313_PREINIT_SDCHAN(num, mode, wnr, dep, sa, ntilex, ntiley) |
| Old style memory channel programming.
|
#define | X313_POSTINIT_SDCHAN(num, cmd) {port_csp0_addr[X313_WA_SDCH0_CTL0+0+((num)<<2)] = cmd; X3X3_AFTERWRITE} |
#define | X313_INIT_SDCHAN(num, mode, wnr, dep, sa, ntilex, ntiley) {X313_POSTINIT_SDCHAN ( num, X313_PREINIT_SDCHAN ( num,mode,wnr,dep,sa,ntilex,ntiley ))} |
#define | X313_SDCHAN_REG0(mode, wnr, dep, sa, ntilex, ntiley) ((((mode) & 1) << 15) | (((wnr) & 1) << 14) | (((dep) & 1) << 13) | (((sa) >> 8) & 0x1fff)) |
| data to be programmed to the memory registers through the sequencer (all arguments are the same, not all are used for all registers)
|
#define | X313_SDCHAN_REG1(mode, wnr, dep, sa, ntilex, ntiley) (0x8000 | (((ntilex) & 0x3ff) << 4) | (((sa) >> 21) & 0xf)) |
#define | X313_SDCHAN_REG2(mode, wnr, dep, sa, ntilex, ntiley) ((ntiley) & 0xfff) |
#define | X313_CHN_EN_D(x) ((0x30 << (((x)& 3)<<1)) | 0xf) |
| mode=1, wnr=1 - photofinish
|
#define | X313_CHN_DIS_D(x) (0x20 << (((x)& 3)<<1)) |
#define | X313_CHN_DISALL_D 0xaa0 |
#define | X313_SDRAM_OFF_D 0xaaa |
#define | X313_SDRAM_ON_D 0xaaf |
#define | X313_CHN_EN(x) {X3X3_AFTERWRITE ; port_csp0_addr[X313_WA_SD_MODE] = X313_CHN_EN_D(x); } |
#define | X313_CHN_DIS(x) {X3X3_AFTERWRITE ; port_csp0_addr[X313_WA_SD_MODE] = X313_CHN_DIS_D(x); } |
#define | X313_CHN_DISALL {X3X3_AFTERWRITE ; port_csp0_addr[X313_WA_SD_MODE] = X313_CHN_DISALL_D ; } |
#define | X313_SDRAM_OFF {port_csp0_addr[X313_WA_SD_MODE]= X313_SDRAM_OFF_D;} |
#define | X313_SDRAM_ON {port_csp0_addr[X313_WA_SD_MODE]= X313_SDRAM_ON_D;} |
#define | X313_IS_SDRAM_ON (port_csp0_addr[X313_WA_SD_MODE],((port_csp0_addr[X313_WA_SD_MODE] & 3)==3)) |
#define | X313_CHN0_BOUND (port_csp0_addr[X313_WA_SDCH2_CTL0],(port_csp0_addr[X313_WA_SDCH2_CTL0] & 0x2000)) |
#define | X313_XFERCNTR (port_csp0_addr[X313__RA__XFERCNTR],port_csp0_addr[X313__RA__XFERCNTR]) |
#define | X313_HIGHFREQ (port_csp0_addr[X313__RA__HIGHFREQ],port_csp0_addr[X313__RA__HIGHFREQ]) |
#define | X313_IRQSTATE (port_csp0_addr[0x11],port_csp0_addr[0x11]) |
#define | X313_IOPINS (port_csp0_addr[X313__RA__IOPINS],port_csp0_addr[X313__RA__IOPINS]) |
#define | X313_CHN0_USED |
| X313_WA_SDCH0_CTL2 bits 12..15 are coming from dynamic register and do not depend on the written data.
|
#define | X313_CHN0_SET_USED { port_csp0_addr[X313_WA_SDCH0_CTL1]=0x8000; } |
#define | X313_CHN0_SET_UNUSED { port_csp0_addr[X313_WA_SDCH0_CTL1]=0; } |
#define | X313_SET_FPGA_TIME(x, y) { port_csp0_addr[X313_WA_RTC_USEC]= ( y ); port_csp0_addr[X313_WA_RTC_SEC]= ( x ); } |
#define | X313_GET_FPGA_TIME(x, y) { port_csp0_addr[X313_WA_RTC_LATCH]= 0; X3X3_AFTERWRITE ; x = port_csp0_addr[X313_WA_RTC_SEC]; y = port_csp0_addr[X313_WA_RTC_USEC];} |
#define | X313_GET_FPGA_SECONDS(x) { port_csp0_addr[X313_WA_RTC_LATCH]= 0; X3X3_AFTERWRITE ; x = port_csp0_addr[X313_WA_RTC_SEC]} |
#define | X313_MAP_FPN 0 |
#define | X313_SDRAM_SIZE 0x4000000 |
#define | X313_MAXWIDTH 4096 |
#define | X313_MAXHEIGHT 4096 |
#define | X313_MAP_FRAME ((X313_MAP_FPN) + (X313_MAXWIDTH) * (X313_MAXHEIGHT)) |
#define | X313_MARGINS 4 |
#define | X313_TILEHOR 16 |
#define | X313_TILEVERT 16 |