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00072 #include <linux/autoconf.h>
00073
00074 #include <linux/module.h>
00075 #include <linux/sched.h>
00076 #include <linux/slab.h>
00077 #include <linux/ioport.h>
00078 #include <linux/errno.h>
00079 #include <linux/kernel.h>
00080 #include <linux/fs.h>
00081 #include <linux/string.h>
00082
00083 #include <linux/init.h>
00084
00085
00086
00087
00088
00089
00090
00091
00092 #include <asm/arch/hwregs/reg_map.h>
00093 #include <asm/arch/hwregs/reg_rdwr.h>
00094 #include <asm/arch/hwregs/gio_defs.h>
00095 #include <asm/arch/hwregs/intr_vect_defs.h>
00096 #include <asm/arch/hwregs/pinmux_defs.h>
00097
00098
00099 #include <asm/io.h>
00100 #include <asm/system.h>
00101 #include <asm/irq.h>
00102
00103 #include <asm/elphel/driver_numbers.h>
00104 #include <asm/elphel/fpgaconfa.h>
00105
00106
00107 #include <asm/delay.h>
00108 #include <asm/uaccess.h>
00109
00110 #include "fpgactrl.h"
00111 #include "x3x3.h"
00112
00113
00114
00115
00116
00117
00118
00119 #define D(x)
00120
00121
00122
00123
00124
00125
00126
00127
00128
00129
00130
00131
00132
00133 #define FPGAJTAG_TDO_BIT 0
00134 #define FPGAJTAG_TDI_BIT 1
00135 #define FPGAJTAG_TMS_BIT 2
00136 #define FPGAJTAG_TCK_BIT 3
00137 #define FPGAJTAG_DONE_BIT 5
00138 #define FPGAJTAG_RSTBTN_BIT 6
00139 #define FPGAJTAG_PGM_BIT 7
00140
00141
00142 #ifndef XC2S300E_BITSIZE
00143 #define XC3S1000_BITSIZE 3223488
00144 #define XC3S1200E_BITSIZE 3841189
00145 #define XC3S1200E_BOUNDARY_SIZE 772
00146
00147 #define FJTAG_BUF_SIZE 0x77000
00148 #define FJTAG_MAX_HEAD 0x1000
00149 #define FJTAG_RAW_WSIZE 0x40000 // shared with bitstream buffer
00150 #define FJTAG_RAW_RSIZE 0x30000 // shared with bitstream buffer
00151 #define FJTAG_IDSIZE 0x40 // bits - ID and User
00152
00153 #endif
00154
00155 #define FPGA_JTAG_DRIVER_NAME "Elphel (R) model 353 FPGA (Xilinx (R) XC3S1200E) configuration driver"
00156 #define FPGA_JTAG_MAXMINOR 10
00157
00158
00159 #define JTAG_RAW 0 // raw JTAG access to any FPGA
00160 #define JTAG_MAIN_FPGA 1 // main board FPGA access (10353)
00161 #define JTAG_SENSOR_FPGA 2 // sensor board FPGA access (10347, 10359)
00162 #define JTAG_AUX_FPGA 3 //
00163 #define JTAG_NCHANNELS 4
00164
00165 #define JTAG_MODE_CLOSED 0 // JTAG channel is closed
00166 #define JTAG_MODE_RDID 1 // JTAG channel read ID
00167 #define JTAG_MODE_PGM 2 // JTAG channel PROGRAM
00168 #define JTAG_MODE_BOUNDARY 3 // JTAG channel boundary scan (just opened, will become one of the 2:JTAG_MODE_SAMPLE, JTAG_MODE_EXTEST
00169 #define JTAG_MODE_SAMPLE 4 // JTAG channel boundary scan - sample (the first operation after open is read)
00170 #define JTAG_MODE_EXTEST 5 // JTAG channel boundary scan - EXTEST (the first operation after open is read)
00171 #define JTAG_MODE_RAW 6 // JTAG raw command mode
00172
00173
00174 struct JTAG_channel_t {
00175 int mode;
00176 unsigned char * dbuf;
00177 int sizew;
00178 int sizer;
00179 int bitsw;
00180 int bitsr;
00181 int wp;
00182 int rp;
00183 int wdirty;
00184 };
00185 static unsigned char bitstream_data[FJTAG_BUF_SIZE];
00186
00187 static unsigned char *raw_fifo_w= &bitstream_data[0];
00188 static unsigned char *raw_fifo_r= &bitstream_data[FJTAG_RAW_WSIZE];
00189 static struct JTAG_channel_t JTAG_channels[JTAG_NCHANNELS];
00190
00191 static int data_modified=0;
00192
00193 static reg_gio_rw_pc_dout pc_dout;
00194 #define PC_DOUT_INITIAL 0
00195
00196
00197
00198
00199
00200
00201
00202
00203 static const char fpga_jtag_name[] = "fpga_jtag_loader";
00204 static int minors[FPGA_JTAG_MAXMINOR+1];
00205
00206 static int fpga_jtag_open (struct inode *inode, struct file *filp);
00207 static int fpga_jtag_release(struct inode *inode, struct file *filp);
00208 static ssize_t fpga_jtag_write (struct file * file, const char * buf, size_t count, loff_t *off);
00209 static loff_t fpga_jtag_lseek (struct file * file, loff_t offset, int orig);
00210 static ssize_t fpga_jtag_read (struct file * file, char * buf, size_t count, loff_t *off);
00211 static int __init fpga_jtag_init(void);
00212
00213 static struct file_operations fpga_jtag_fops = {
00214 owner: THIS_MODULE,
00215 open: fpga_jtag_open,
00216 release: fpga_jtag_release,
00217 llseek: fpga_jtag_lseek,
00218 read: fpga_jtag_read,
00219 write: fpga_jtag_write
00220 };
00221
00222
00223
00224
00225 loff_t fjtag_bitsize (int minor);
00226 loff_t fjtag_bytesize (int minor);
00227 int JTAG_channel(int minor);
00228 void initPortC(void);
00229 void set_pgm_mode (int chn, int en);
00230 void set_pgm (int chn, int pgmon);
00231 int read_done (int chn);
00232 int jtag_send (int chn, int tms, int len, int d);
00233 int jtag_write_bits (int chn,
00234 unsigned char *buf,
00235 int len,
00236 int check,
00237 int last,
00238 int prev[2]);
00239 int JTAG_configure (int chn, unsigned char * buf, int len);
00240 int JTAG_readID (int chn, unsigned char * buf);
00241 int JTAG_openChannel (int chn);
00242 int JTAG_resetChannel (int chn);
00243 int JTAG_CAPTURE (int chn, unsigned char * buf, int len);
00244 int JTAG_EXTEST (int chn, unsigned char * buf, int len);
00245
00246 void JTAG_push_raw (int b);
00247 int JTAG_process_raw(void);
00248
00249
00250 int JTAG_channel(int minor) {
00251 switch (minor) {
00252 case FPGA_JTAG_RESET_MINOR :
00253 return JTAG_RAW;
00254 case FPGA_JTAG_MINOR:
00255 case FPGA_JTAG_BOUNDARY_MINOR:
00256 return JTAG_MAIN_FPGA;
00257 case FPGA_SJTAG_MINOR:
00258 case FPGA_SJTAG_BOUNDARY_MINOR:
00259 return JTAG_SENSOR_FPGA;
00260 case FPGA_AJTAG_MINOR:
00261 case FPGA_AJTAG_BOUNDARY_MINOR:
00262 return JTAG_AUX_FPGA;
00263 }
00264 return 0;
00265 }
00266 static int raw_fifo_w_wp;
00267 static int raw_fifo_w_rp;
00268 static int raw_fifo_r_wp;
00269 static int raw_fifo_r_rp;
00270 static int raw_chn;
00271
00272
00273
00274
00275
00276
00277
00278
00279
00280
00281
00282
00283
00284
00285
00286
00287 #define JTAG_RAW_SEND 0x10
00288 #define JTAG_RAW_SETCHN 0x20
00289 #define JTAG_RAW_DEACT 0x22
00290 #define JTAG_RAW_ACT 0x23
00291 #define JTAG_RAW_PGMOFF 0x24
00292 #define JTAG_RAW_PGMON 0x25
00293 #define JTAG_RAW_WAIT 0x80
00294
00295 void JTAG_push_raw (int b) {
00296 raw_fifo_r[raw_fifo_r_wp++]=b;
00297 if (raw_fifo_r_wp > FJTAG_RAW_RSIZE) raw_fifo_r_wp-=FJTAG_RAW_RSIZE;
00298 }
00299 int JTAG_process_raw(void) {
00300 unsigned char b0, b1;
00301 while (raw_fifo_w_rp != (raw_fifo_w_wp & ~1)) {
00302 b0=raw_fifo_w[raw_fifo_w_rp++];
00303 b1=raw_fifo_w[raw_fifo_w_rp++];
00304 if (raw_fifo_w_rp > FJTAG_RAW_WSIZE) raw_fifo_w_rp-=FJTAG_RAW_WSIZE;
00305 if (b1 == JTAG_RAW_SETCHN) {
00306 raw_chn = b0;
00307 if (raw_chn>=JTAG_NCHANNELS) raw_chn=0;
00308 JTAG_push_raw (raw_chn);
00309 } else if (raw_chn) {
00310 if ((b1 & 0xf0) == JTAG_RAW_SEND) {
00311 JTAG_push_raw (jtag_send(raw_chn, (b1 >> 3) & 1, b1 & 7, (int) b0 ));
00312 } else if ((b1 & 0x80) == JTAG_RAW_WAIT) {
00313 udelay(((b1 & 0x7f) <<8) + b0);
00314 JTAG_push_raw (0x80);
00315 } else switch (b1) {
00316 case JTAG_RAW_DEACT:
00317 set_pgm_mode (raw_chn, 0);
00318 JTAG_push_raw (0x0);
00319 break;
00320 case JTAG_RAW_ACT:
00321 set_pgm_mode (raw_chn, 1);
00322 JTAG_push_raw (0x0);
00323 break;
00324 case JTAG_RAW_PGMOFF:
00325 set_pgm (raw_chn, 0);
00326 JTAG_push_raw (read_done(raw_chn));
00327 case JTAG_RAW_PGMON:
00328 set_pgm (raw_chn, 1);
00329 JTAG_push_raw (0xf0);
00330 break;
00331 default:
00332 JTAG_push_raw (0xff);
00333 }
00334 } else {
00335 JTAG_push_raw (0xf0);
00336 }
00337 }
00338 return 0;
00339 }
00340
00341
00342
00343 int JTAG_whatopen(void) {
00344 int i,r=0;
00345 for (i=0;i<JTAG_NCHANNELS;i++) r |= 1 << JTAG_channels[i].mode;
00346 return r;
00347 }
00348
00349
00350
00351 static int fpga_jtag_open(struct inode *inode, struct file *filp) {
00352 int i;
00353
00354 int p = MINOR(inode->i_rdev);
00355 int chn= JTAG_channel(p);
00356 reg_intr_vect_rw_mask intr_mask;
00357 D(printk("fpga_jtag_open: minor=%x, channel=%x, buf=%p\r\n",p,chn,bitstream_data ));
00358 switch ( p ) {
00359 case FPGA_JTAG_RESET_MINOR :
00360 for (i=1; i<JTAG_NCHANNELS; i++) JTAG_channels[i].mode=JTAG_MODE_CLOSED;
00361 JTAG_channels[chn].mode=JTAG_MODE_RAW;
00362 JTAG_channels[chn].sizew = FJTAG_RAW_WSIZE;
00363 JTAG_channels[chn].sizer = FJTAG_RAW_RSIZE;
00364 JTAG_channels[chn].wp = 0;
00365 JTAG_channels[chn].rp = 0;
00366 raw_fifo_w_wp=0;
00367 raw_fifo_w_rp=0;
00368 raw_fifo_r_wp=0;
00369 raw_fifo_r_rp=0;
00370 raw_chn=0;
00371 break;
00372 case FPGA_JTAG_MINOR :
00373 if ( JTAG_whatopen() & 0x7e) return -EACCES;
00374
00375
00376
00377
00378
00379
00380 fpga_state &= ~FPGA_STATE_LOADED;
00381 fpga_state &= ~FPGA_STATE_SDRAM_INIT;
00382
00383
00384 intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
00385 intr_mask.ext = 0;
00386 REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
00387
00388
00389
00390 case FPGA_SJTAG_MINOR :
00391 case FPGA_AJTAG_MINOR :
00392 if ( JTAG_whatopen() & 0x7e) return -EACCES;
00393 JTAG_channels[chn].mode = JTAG_MODE_PGM;
00394 JTAG_channels[chn].dbuf = &bitstream_data[0];
00395 JTAG_channels[chn].sizew = FJTAG_BUF_SIZE;
00396 JTAG_channels[chn].sizer = FJTAG_IDSIZE >> 3;
00397 JTAG_channels[chn].wp = 0;
00398 JTAG_channels[chn].rp = 0;
00399 JTAG_channels[chn].bitsw = XC3S1200E_BITSIZE;
00400 JTAG_channels[chn].bitsr= FJTAG_IDSIZE;
00401 JTAG_openChannel (chn);
00402 break;
00403 case FPGA_JTAG_BOUNDARY_MINOR :
00404 case FPGA_SJTAG_BOUNDARY_MINOR :
00405 case FPGA_AJTAG_BOUNDARY_MINOR :
00406 if ( JTAG_whatopen() & 0x46) return -EACCES;
00407 if ( JTAG_channels[chn].mode != JTAG_MODE_CLOSED) return -EACCES;
00408 JTAG_channels[chn].mode = JTAG_MODE_BOUNDARY;
00409 JTAG_channels[chn].sizew = (XC3S1200E_BOUNDARY_SIZE+7) >> 3;
00410 JTAG_channels[chn].sizer = (XC3S1200E_BOUNDARY_SIZE+7) >> 3;
00411 JTAG_channels[chn].dbuf = &bitstream_data[JTAG_channels[chn].sizew * chn];
00412 JTAG_channels[chn].wp = 0;
00413 JTAG_channels[chn].rp = 0;
00414 JTAG_channels[chn].bitsw = XC3S1200E_BOUNDARY_SIZE;
00415 JTAG_channels[chn].bitsr= XC3S1200E_BOUNDARY_SIZE;
00416 JTAG_openChannel (chn);
00417 break;
00418 default: return -EINVAL;
00419 }
00420 D(printk("fpga_jtag_open: chn=%x, JTAG_channels[chn].sizew=%x, JTAG_channels[chn].sizer=%x\r\n", chn,JTAG_channels[chn].sizew, JTAG_channels[chn].sizer) );
00421 D(printk("fpga_jtag_open: chn=%x, JTAG_channels[chn].bitsw=%x, JTAG_channels[chn].bitsr=%x\r\n", chn,JTAG_channels[chn].bitsw, JTAG_channels[chn].bitsr) );
00422 JTAG_channels[chn].wdirty=0;
00423
00424 inode->i_size=JTAG_channels[chn].sizer;
00425 minors[p]=p;
00426 filp->private_data = &minors[p];
00427 D(printk("fpga_jtag_open: inode->i_size=%x, chn=%x\r\n", (int) inode->i_size, chn) );
00428 return 0;
00429 }
00430
00431
00432
00433 static int fpga_jtag_release(struct inode *inode, struct file *filp) {
00434 int res=0;
00435 int p = MINOR(inode->i_rdev);
00436 int chn= JTAG_channel(p);
00437
00438 D(printk("fpga_jtag_release: p=%x,chn=%x, wp=0x%x, rp=0x%x\r\n",p,chn, JTAG_channels[chn].wp, JTAG_channels[chn].rp));
00439 switch ( p ) {
00440 case FPGA_JTAG_RESET_MINOR :
00441 break;
00442 case FPGA_JTAG_MINOR :
00443 case FPGA_SJTAG_MINOR :
00444 case FPGA_AJTAG_MINOR :
00445 if (JTAG_channels[chn].wp > 0) {
00446 res=JTAG_configure (chn, JTAG_channels[chn].dbuf, JTAG_channels[chn].wp);
00447 JTAG_resetChannel (chn);
00448 if ((res >=0) & (chn == JTAG_MAIN_FPGA)) {
00449 fpga_state = (fpga_state & ~0xffff) | (port_csp0_addr[X313__RA__MODEL] & 0xffff);
00450 }
00451 } else JTAG_resetChannel (chn);
00452 if (chn == JTAG_MAIN_FPGA) fpga_state &=~FPGA_STATE_INITIALIZED;
00453
00454 break;
00455 case FPGA_JTAG_BOUNDARY_MINOR :
00456 case FPGA_SJTAG_BOUNDARY_MINOR :
00457 case FPGA_AJTAG_BOUNDARY_MINOR :
00458
00459 if (JTAG_channels[chn].wp >0) JTAG_EXTEST (chn, JTAG_channels[chn].dbuf, JTAG_channels[chn].bitsw);
00460 JTAG_resetChannel (chn);
00461 break;
00462 default: return -EINVAL;
00463 }
00464 minors[p]=0;
00465 JTAG_channels[chn].mode=JTAG_MODE_CLOSED;
00466 D(printk("fpga_jtag_release: done\r\n"));
00467 return (res<0)?res:0;
00468 }
00469
00470
00471
00472
00473
00474 static ssize_t fpga_jtag_write(struct file * file, const char * buf, size_t count, loff_t *off) {
00475 int p = ((int *)file->private_data)[0];
00476 int chn= JTAG_channel(p);
00477 size_t size = JTAG_channels[chn].sizew;
00478 D(printk("fpga_jtag_write: p=%x,chn=%x, buf address=%lx count=%lx *offs=%lx, wp=%lx,size=0x%x\r\n",p,chn,(long) buf, (long) count, (long) *off, (long)JTAG_channels[chn].wp, (int) size));
00479
00480 switch (p) {
00481 case FPGA_JTAG_RESET_MINOR :
00482 if (count > size) count= size;
00483 if ((raw_fifo_w_wp+count) > size) {
00484 if (copy_from_user(&raw_fifo_w[raw_fifo_w_wp],buf,size-raw_fifo_w_wp)) return -EFAULT;
00485 if (copy_from_user(&raw_fifo_w[0],&buf[size-raw_fifo_w_wp],count+raw_fifo_w_wp-size)) return -EFAULT;
00486 } else {
00487 if (copy_from_user(&raw_fifo_w[raw_fifo_w_wp],buf,count)) return -EFAULT;
00488 }
00489 raw_fifo_w_wp+=count;
00490 if (raw_fifo_w_wp > size) raw_fifo_w_wp -= size;
00491 JTAG_process_raw();
00492 break;
00493 case FPGA_JTAG_MINOR :
00494 case FPGA_SJTAG_MINOR :
00495 case FPGA_AJTAG_MINOR :
00496 if (*off > size) return -EFAULT;
00497 if ((*off + count) > size) count= (size - *off);
00498 if (copy_from_user(&(JTAG_channels[chn].dbuf[*off]),buf,count)) return -EFAULT;
00499 *off+=count;
00500 if (*off > JTAG_channels[chn].wp) JTAG_channels[chn].wp= *off;
00501 break;
00502 case FPGA_JTAG_BOUNDARY_MINOR :
00503 case FPGA_SJTAG_BOUNDARY_MINOR :
00504 case FPGA_AJTAG_BOUNDARY_MINOR :
00505 if (*off > size) return -EFAULT;
00506 if ((*off + count) > size) count= (size - *off);
00507
00508 if (*off < JTAG_channels[chn].wp) {
00509 JTAG_EXTEST (chn, JTAG_channels[chn].dbuf, JTAG_channels[chn].bitsw);
00510 JTAG_channels[chn].wdirty=0;
00511 }
00512 if (copy_from_user(&(JTAG_channels[chn].dbuf[*off]),buf,count)) return -EFAULT;
00513 *off+=count;
00514 JTAG_channels[chn].wp= *off;
00515 if (*off >= size) {
00516 *off=0;
00517 }
00518 JTAG_channels[chn].mode=JTAG_MODE_EXTEST;
00519 JTAG_channels[chn].wdirty=1;
00520 break;
00521 default: return -EINVAL;
00522 }
00523 D(printk("fpga_jtag_write end: p=%x,chn=%x, buf address=%lx count=%lx *offs=%lx, wp=%lx,size=0x%x\r\n",p,chn,(long) buf, (long) count, (long) *off, (long)JTAG_channels[chn].wp, (int) size));
00524 return count;
00525 }
00526
00527
00528
00529 ssize_t fpga_jtag_read(struct file * file, char * buf, size_t count, loff_t *off) {
00530 int p = ((int *)file->private_data)[0];
00531 int chn= JTAG_channel(p);
00532 size_t size = JTAG_channels[chn].sizer;
00533 int size_av;
00534
00535 D(printk("fpga_jtag_read: p=%x,chn=%x, buf address=%lx count=%lx *offs=%lx, rp=%lx,size=0x%x\r\n",p,chn,(long) buf, (long) count, (long) *off, (long)JTAG_channels[chn].rp, (int) size));
00536 switch (p) {
00537 case FPGA_JTAG_RESET_MINOR :
00538 size_av=(raw_fifo_r_wp >= raw_fifo_r_rp)?(raw_fifo_r_wp - raw_fifo_r_rp):(size+raw_fifo_r_wp - raw_fifo_r_rp);
00539 if (count > size_av) count= size_av;
00540 if ((raw_fifo_r_rp+count) > size) {
00541 if (copy_to_user(buf, &raw_fifo_r[raw_fifo_r_rp],size-raw_fifo_r_rp)) return -EFAULT;
00542 if (copy_to_user(&buf[size-raw_fifo_r_rp],&raw_fifo_r[0],count+raw_fifo_r_rp-size)) return -EFAULT;
00543 } else {
00544 if (copy_to_user(buf,&raw_fifo_w[raw_fifo_w_wp],count)) return -EFAULT;
00545 }
00546 raw_fifo_r_rp+=count;
00547 if (raw_fifo_r_rp > size) raw_fifo_r_rp -= size;
00548 break;
00549 case FPGA_JTAG_MINOR :
00550 case FPGA_SJTAG_MINOR :
00551 case FPGA_AJTAG_MINOR :
00552 if ((JTAG_channels[chn].wp==0) && (JTAG_channels[chn].rp==0)) {
00553 JTAG_channels[chn].mode=JTAG_MODE_RDID;
00554 JTAG_readID (chn, JTAG_channels[chn].dbuf);
00555 }
00556 if (*off > size) return -EFAULT;
00557 if ((*off + count) > size) count= (size - *off);
00558 D(printk("fpga_jtag_read_01: p=%x,chn=%x, buf address=%lx count=%lx *offs=%lx, rp=%lx,size=0x%x\r\n",p,chn,(long) buf, (long) count, (long) *off, (long)JTAG_channels[chn].rp, (int) size));
00559
00560 if (copy_to_user(buf,&(JTAG_channels[chn].dbuf[*off]),count)) return -EFAULT;
00561 *off+=count;
00562 JTAG_channels[chn].rp= *off;
00563 break;
00564 case FPGA_JTAG_BOUNDARY_MINOR :
00565 case FPGA_SJTAG_BOUNDARY_MINOR :
00566 case FPGA_AJTAG_BOUNDARY_MINOR :
00567 if ((JTAG_channels[chn].mode==JTAG_MODE_EXTEST) && (JTAG_channels[chn].wdirty || (*off < JTAG_channels[chn].rp))) {
00568 JTAG_EXTEST (chn, JTAG_channels[chn].dbuf, JTAG_channels[chn].bitsr);
00569 JTAG_channels[chn].wdirty=0;
00570 }
00571
00572 if ((JTAG_channels[chn].mode!=JTAG_MODE_EXTEST) && ((*off < JTAG_channels[chn].rp) || (JTAG_channels[chn].mode==JTAG_MODE_BOUNDARY))) {
00573 JTAG_CAPTURE (chn, JTAG_channels[chn].dbuf, JTAG_channels[chn].bitsr);
00574 }
00575 if (*off > size) return -EFAULT;
00576 if ((*off + count) > size) count= (size - *off);
00577 D(printk("fpga_jtag_read_01: p=%x,chn=%x, buf address=%lx count=%lx *offs=%lx, rp=%lx,size=0x%x\r\n",p,chn,(long) buf, (long) count, (long) *off, (long)JTAG_channels[chn].rp, (int) size));
00578
00579
00580
00581
00582 if (copy_to_user(buf,&(JTAG_channels[chn].dbuf[*off]),count)) return -EFAULT;
00583 *off+=count;
00584 JTAG_channels[chn].rp= *off;
00585 if (*off >= size) {
00586 *off=0;
00587 }
00588 if (JTAG_channels[chn].mode == JTAG_MODE_BOUNDARY) JTAG_channels[chn].mode=JTAG_MODE_SAMPLE;
00589 break;
00590 default: return -EINVAL;
00591 }
00592 D(printk("fpga_jtag_read_end: p=%x,chn=%x, buf address=%lx count=%lx *offs=%lx, rp=%lx,size=0x%x, mode=%x\r\n",p,chn,(long) buf, (long) count, (long) *off, (long)JTAG_channels[chn].rp, (int) size, JTAG_channels[chn].mode));
00593 return count;
00594 }
00595
00596
00597
00598 static loff_t fpga_jtag_lseek(struct file * file, loff_t offset, int orig) {
00599
00600
00601
00602
00603
00604 int p = ((int *)file->private_data)[0];
00605 int chn= JTAG_channel(p);
00606 size_t size;
00607 if (chn==JTAG_RAW) {
00608 size=raw_fifo_r_wp-raw_fifo_r_rp;
00609 if (size<0) size+=FJTAG_RAW_RSIZE;
00610 } else size = JTAG_channels[chn].sizew;
00611 if (JTAG_channels[chn].mode == JTAG_MODE_RDID) size = JTAG_channels[chn].sizer;
00612 D(printk("fpga_jtag_lseek, fsize= 0x%x\n", (int) size));
00613 switch (orig) {
00614 case 0:
00615 file->f_pos = offset;
00616 break;
00617 case 1:
00618 file->f_pos += offset;
00619 break;
00620 case 2:
00621 file->f_pos = size + offset;
00622 break;
00623 default:
00624 return -EINVAL;
00625 }
00626
00627 if (file->f_pos < 0) {
00628 file->f_pos = 0;
00629 return (-EOVERFLOW);
00630 }
00631
00632 if (file->f_pos > size) {
00633 file->f_pos = size;
00634 return (-EOVERFLOW);
00635 }
00636 D(printk("fpga_jtag_lseek, file->f_pos= 0x%x\n", (int) file->f_pos));
00637 return (file->f_pos);
00638 }
00639
00640
00641
00642
00643 void initPortC(void) {
00644
00645 unsigned long tmp;
00646 reg_pinmux_rw_pc_iop pinmux_c_iop;
00647 reg_pinmux_rw_pc_gio pinmux_c_gio;
00648 reg_gio_rw_pc_oe pc_oe;
00649
00650 pinmux_c_iop= REG_RD(pinmux, regi_pinmux, rw_pc_iop);
00651 tmp = REG_TYPE_CONV(unsigned long, reg_pinmux_rw_pc_iop, pinmux_c_iop);
00652 tmp &= ~0xff;
00653 pinmux_c_iop = REG_TYPE_CONV(reg_pinmux_rw_pc_iop, unsigned long, tmp);
00654 REG_WR(pinmux, regi_pinmux, rw_pc_iop, pinmux_c_iop);
00655
00656 pinmux_c_gio= REG_RD(pinmux, regi_pinmux, rw_pc_gio);
00657 tmp = REG_TYPE_CONV(unsigned long, reg_pinmux_rw_pc_gio, pinmux_c_gio);
00658 tmp |= 0xff;
00659 pinmux_c_gio = REG_TYPE_CONV(reg_pinmux_rw_pc_gio, unsigned long, tmp);
00660 REG_WR(pinmux, regi_pinmux, rw_pc_gio, pinmux_c_gio);
00661
00662
00663 pc_dout = REG_RD(gio, regi_gio, rw_pc_dout);
00664 pc_dout.data &= ~0xff;
00665 pc_dout.data |= PC_DOUT_INITIAL;
00666 REG_WR(gio, regi_gio, rw_pc_dout, pc_dout);
00667
00668
00669 pc_oe = REG_RD(gio, regi_gio, rw_pc_oe);
00670 pc_oe.oe &= ~( (1 << FPGAJTAG_TDO_BIT) |
00671 (1 << FPGAJTAG_DONE_BIT) |
00672 (1 << FPGAJTAG_RSTBTN_BIT));
00673 pc_oe.oe |= ( (1 << FPGAJTAG_TDI_BIT) |
00674 (1 << FPGAJTAG_TMS_BIT) |
00675 (1 << FPGAJTAG_TCK_BIT) |
00676 (1 << FPGAJTAG_PGM_BIT));
00677 REG_WR(gio, regi_gio, rw_pc_oe, pc_oe);
00678 }
00679
00680
00681
00682 void set_pgm_mode (int chn, int en) {
00683 D(printk ("set_pgm_mode (%d,%d)\n",chn,en));
00684
00685 switch (chn) {
00686 case JTAG_SENSOR_FPGA:
00687 port_csp0_addr[X313_WA_SENSFPGA] = (en ? (3 << SFPGA_PGMEN_BIT): (SFPGA_RD_SENSPGMPIN | (2 << SFPGA_PGMEN_BIT))) | (2 << SFPGA_TCK_BIT);
00688 break;
00689 }
00690 udelay (2);
00691 }
00692
00693 void set_pgm (int chn, int pgmon) {
00694 D(printk ("set_pgm (%d,%d)\n",chn,pgmon));
00695 switch (chn) {
00696 case JTAG_MAIN_FPGA:
00697 if (pgmon) pc_dout.data &= ~0x80;
00698 else pc_dout.data |= 0x80;
00699 REG_WR(gio, regi_gio, rw_pc_dout, pc_dout);
00700 break;
00701 case JTAG_SENSOR_FPGA:
00702 port_csp0_addr[X313_WA_SENSFPGA] = (2 | (pgmon & 1)) << SFPGA_PROG_BIT;
00703 break;
00704 case JTAG_AUX_FPGA:
00705 break;
00706 }
00707 udelay (2);
00708 }
00709
00710
00711 int read_done (int chn) {
00712 switch (chn) {
00713 case JTAG_MAIN_FPGA:
00714 return ((((REG_RD(gio, regi_gio, r_pc_din)).data & 0x20)==0) ? 0 : 1 );
00715 case JTAG_SENSOR_FPGA:
00716 port_csp0_addr[X313_WA_SENSFPGA] = SFPGA_RD_DONE;
00717 udelay (1);
00718 return (port_csp0_addr[X313__RA__SENSFPGA] >> SFPGA_RD_BIT) & 1 ;
00719 case JTAG_AUX_FPGA:
00720 return 0;
00721 }
00722 return 0;
00723 }
00724
00725
00726 int jtag_send (int chn, int tms, int len, int d) {
00727 int i;
00728 int r=0;
00729 int d0;
00730 i = len & 7;
00731 if (i==0) i=8;
00732 d &= 0xff;
00733 d0=d;
00734 D( printk("jtag_send(0x%x, 0x%x, 0x%x, 0x%x)\r\n", chn, tms,len,d));
00735 switch (chn) {
00736 case JTAG_MAIN_FPGA:
00737
00738 pc_dout.data &= ~0x0e;
00739 pc_dout.data |= (tms & 1) << FPGAJTAG_TMS_BIT;
00740 for (;i>0;i--){
00741 r= (r<<1)+ ((REG_RD(gio, regi_gio, r_pc_din)).data & 1);
00742 pc_dout.data = (pc_dout.data & ~0x0a) | (((d<<=1)>>7) & 2);
00743 REG_WR(gio, regi_gio, rw_pc_dout, pc_dout);
00744 pc_dout.data |= (1 << FPGAJTAG_TCK_BIT);
00745 REG_WR(gio, regi_gio, rw_pc_dout, pc_dout);
00746 pc_dout.data &= ~(1 << FPGAJTAG_TCK_BIT);
00747 REG_WR(gio, regi_gio, rw_pc_dout, pc_dout);
00748 }
00749 break;
00750 case JTAG_SENSOR_FPGA:
00751 port_csp0_addr[X313_WA_SENSFPGA] = SFPGA_RD_TDO;
00752 udelay (1);
00753 for (;i>0;i--){
00754 port_csp0_addr[X313_WA_SENSFPGA] = (2 << SFPGA_TCK_BIT);
00755 port_csp0_addr[X313_WA_SENSFPGA] = ((2 | (tms & 1)) << SFPGA_TMS_BIT) |
00756 (((((d<<=1)>>8) & 1) | 2) << SFPGA_TDI_BIT) |
00757 (2 << SFPGA_TCK_BIT) ;
00758 port_csp0_addr[X313_WA_SENSFPGA] = (2 << SFPGA_TCK_BIT);
00759 port_csp0_addr[X313_WA_SENSFPGA] = (3 << SFPGA_TCK_BIT);
00760 r= (r<<1)+ ((port_csp0_addr[X313__RA__SENSFPGA] >> SFPGA_RD_BIT) & 1);
00761 port_csp0_addr[X313_WA_SENSFPGA] = (2 << SFPGA_TCK_BIT);
00762
00763 }
00764 port_csp0_addr[X313_WA_SENSFPGA] = (2 << SFPGA_TCK_BIT);
00765 break;
00766 case JTAG_AUX_FPGA:
00767 break;
00768 }
00769 return r;
00770 }
00771
00772
00773
00774
00775
00776
00777
00778
00779 int jtag_write_bits (int chn,
00780 unsigned char *buf,
00781 int len,
00782 int check,
00783 int last,
00784 int prev[2])
00785 {
00786 int i,j;
00787 int r=0;
00788 int d,d0;
00789 D( printk("jtag_write_bits(0x%x, 0x%x, 0x%x, 0x%x, 0x%x)\r\n", (int) chn, (int) buf, len, check, last););
00790
00791 switch (chn) {
00792 case JTAG_MAIN_FPGA:
00793
00794 for (i=0; len>0;i++) {
00795 pc_dout.data &= ~0x0e;
00796 d0=(d=buf[i]);
00797 for (j=0;j<8;j++) {
00798
00799 if (len>0) {
00800 r= (r<<1)+ ((REG_RD(gio, regi_gio, r_pc_din)).data & 1);
00801 if ((len==1) && last) pc_dout.data = (pc_dout.data & ~0x0a) | (((d<<=1)>>7) & 2) | (1 << FPGAJTAG_TMS_BIT);
00802 else pc_dout.data = (pc_dout.data & ~0x0a) | (((d<<=1)>>7) & 2);
00803 REG_WR(gio, regi_gio, rw_pc_dout, pc_dout);
00804 pc_dout.data |= (1 << FPGAJTAG_TCK_BIT);
00805 REG_WR(gio, regi_gio, rw_pc_dout, pc_dout);
00806 pc_dout.data &= ~(1 << FPGAJTAG_TCK_BIT);
00807 REG_WR(gio, regi_gio, rw_pc_dout, pc_dout);
00808 } else r= (r<<1);
00809 len--;
00810
00811 }
00812 buf[i]=r;
00813 if (check && ((r ^ (prev[1] >> 24)) & 0xff)) {
00814 return -((r & 0xff) | ((i+1) << 8));
00815 }
00816 if (prev) {
00817
00818
00819 prev[1]= (prev[1]<<8) | ((prev[0]>>24) & 0xff);
00820 prev[0]= (prev[0]<<8) | (d0 & 0xff);
00821 }
00822 }
00823 break;
00824 case JTAG_SENSOR_FPGA:
00825 port_csp0_addr[X313_WA_SENSFPGA] = SFPGA_RD_TDO;
00826 udelay (1);
00827 for (i=0; len>0;i++) {
00828 d0=(d=buf[i]);
00829 for (j=0;j<8;j++) {
00830 port_csp0_addr[X313_WA_SENSFPGA] = (2 << SFPGA_TCK_BIT);
00831 if (len>0) {
00832 if ((len==1) && last) port_csp0_addr[X313_WA_SENSFPGA] =
00833 (3 << SFPGA_TMS_BIT) |
00834 (((((d<<=1)>>8) & 1) | 2) << SFPGA_TDI_BIT) |
00835 (2 << SFPGA_TMS_BIT) |
00836 (2 << SFPGA_TCK_BIT) ;
00837
00838 else port_csp0_addr[X313_WA_SENSFPGA] =
00839 (((((d<<=1)>>8) & 1) | 2) << SFPGA_TDI_BIT) |
00840 (2 << SFPGA_TMS_BIT) |
00841 (2 << SFPGA_TCK_BIT) ;
00842 port_csp0_addr[X313_WA_SENSFPGA] = (2 << SFPGA_TCK_BIT);
00843 port_csp0_addr[X313_WA_SENSFPGA] = (3 << SFPGA_TCK_BIT);
00844
00845 r= ((r<<1)+ ((port_csp0_addr[X313__RA__SENSFPGA] >> SFPGA_RD_BIT) & 1));
00846 port_csp0_addr[X313_WA_SENSFPGA] = (2 << SFPGA_TCK_BIT);
00847 } else r= (r<<1);
00848 len--;
00849 }
00850 buf[i]=r;
00851 if (check && ((r ^ (prev[1]>>24)) & 0xff)) {
00852 return -((r & 0xff) | ((i+1) << 8));
00853 }
00854 if (prev) {
00855
00856
00857 prev[1]= (prev[1]<<8) | ((prev[0]>>24) & 0xff);
00858 prev[0]= (prev[0]<<8) | (d0 & 0xff);
00859 }
00860
00861 }
00862 port_csp0_addr[X313_WA_SENSFPGA] = (2 << SFPGA_TCK_BIT);
00863 break;
00864 case JTAG_AUX_FPGA:
00865 break;
00866
00867 }
00868 return 0;
00869 }
00870
00871
00872 int JTAG_configure (int chn, unsigned char * buf, int len) {
00873 int datastart, i, j ,r;
00874
00875
00876 int prev[2];
00877 #ifdef JTAG_DISABLE_IRQ
00878 unsigned long flags;
00879 #endif
00880 const unsigned char sync[]={0xff,0xff,0xff,0xff,0xaa,0x99,0x55,0x66};
00881 int skipvfy=8;
00882
00883 D(printk("JTAG_configure: chn=%x, wp=0x%x, rp=0x%x, len=0x%x\r\n",chn, JTAG_channels[chn].wp, JTAG_channels[chn].rp, len));
00884
00885
00886
00887
00888 datastart=-1;
00889 for (i=0;i<(FJTAG_MAX_HEAD-8);i++) {
00890 j=0;
00891 while ((j<8) && (buf[i+j]==sync[j])) j++;
00892 if (j==8) {
00893 datastart=i;
00894 break;
00895 }
00896 }
00897 if (datastart<0) {
00898 printk("Bitstream not found - bad file\r\n");
00899 return -EFAULT;
00900 }
00901
00902 if ((len-datastart)!=(XC3S1200E_BITSIZE>>3)) {
00903 printk("Wrong bitstream size - XC3S1200E has bitstream of %d bits (%d bytes)\n",XC3S1200E_BITSIZE,XC3S1200E_BITSIZE>>3);
00904 printk ("header size - %d, data size - %d\r\n",datastart, len-datastart);
00905 return -EFAULT;
00906 }
00907
00908 set_pgm_mode(chn, 1);
00909
00910 set_pgm (chn, 1);
00911 udelay (1000);
00912 set_pgm (chn, 0);
00913
00914 udelay (2500);
00915
00916 D( udelay (100000);printk("JTAG_configure(): IRQ off!\r\n"); udelay (100000););
00917 #ifdef JTAG_DISABLE_IRQ
00918 local_irq_save(flags);
00919
00920 #endif
00921
00922 jtag_send(chn, 1, 5, 0 );
00923 jtag_send(chn, 0, 1, 0 );
00924 jtag_send(chn, 1, 2, 0 );
00925 jtag_send(chn, 0, 2, 0 );
00926 jtag_send(chn, 0, 5, 0xa0);
00927 jtag_send(chn, 1, 1, 0 );
00928 jtag_send(chn, 1, 2, 0 );
00929 jtag_send(chn, 0, 2, 0 );
00930
00931 jtag_write_bits (chn,
00932 &buf[datastart],
00933 skipvfy << 3,
00934 0,
00935 0,
00936 prev);
00937
00938 if ((r=jtag_write_bits (chn,
00939 &buf[datastart+skipvfy],
00940
00941 (len-(datastart+skipvfy)) << 3,
00942 1,
00943 1, prev))<0) {
00944 r= -r;
00945 i= (r>>8) -1 + (datastart+skipvfy);
00946 r &= 0xff;
00947 #ifdef JTAG_DISABLE_IRQ
00948 local_irq_restore(flags);
00949 #endif
00950 set_pgm (chn, 1);
00951 set_pgm (chn, 0);
00952
00953 set_pgm_mode(chn, 0);
00954 printk ("**** Configuration failed at byte # %d (%x)****\n", (i-datastart),(i-datastart));
00955 printk ("**** r= %x, prev64=%x prev32=%x****\n", r,prev[1], prev[0]);
00956 return -EFAULT;
00957 }
00958 jtag_send(chn, 1, 1, 0 );
00959 jtag_send(chn, 1, 2, 0 );
00960 jtag_send(chn, 0, 2, 0 );
00961 jtag_send(chn, 0, 5, 0x30);
00962 jtag_send(chn, 1, 1, 0 );
00963 jtag_send(chn, 1, 2, 0 );
00964 jtag_send(chn, 0, 0, 0 );
00965 jtag_send(chn, 0, 0, 0 );
00966 jtag_send(chn, 1, 2, 0 );
00967 jtag_send(chn, 0, 1, 0 );
00968 jtag_send(chn, 0, 0, 0 );
00969 jtag_send(chn, 0, 0, 0 );
00970
00971 #ifdef JTAG_DISABLE_IRQ
00972 local_irq_restore(flags);
00973 #endif
00974
00975 r=read_done(chn);
00976
00977 set_pgm_mode(chn, 0);
00978
00979 if (r==0) {
00980 printk("*** FPGA did not start after configuration ***\r\n");
00981 return -EFAULT;
00982 }
00983
00984 D( udelay (100000);printk("\nJTAG_configure() OK!\r\n"));
00985 return 0;
00986 }
00987
00988
00989
00990
00991
00992
00993 int JTAG_openChannel (int chn) {
00994 D(printk ("JTAG_openChannel (%d)\n",chn));
00995
00996 set_pgm_mode(chn, 1);
00997
00998 switch (chn) {
00999 case JTAG_SENSOR_FPGA:
01000
01001 set_pgm (chn, 1);
01002 set_pgm (chn, 0);
01003
01004 udelay (2500);
01005 break;
01006 }
01007 jtag_send(chn, 1, 5, 0 );
01008 jtag_send(chn, 0, 1, 0 );
01009 }
01010
01011 int JTAG_resetChannel (int chn) {
01012 D(printk ("JTAG_resetChannel (%d)\n",chn));
01013 jtag_send(chn, 1, 5, 0 );
01014
01015 set_pgm_mode(chn, 0);
01016 }
01017
01018 int JTAG_readID (int chn, unsigned char * buf) {
01019 int i;
01020 unsigned long d1,d2=0;
01021 unsigned long * dp;
01022 #ifdef JTAG_DISABLE_IRQ
01023 unsigned long flags;
01024 #endif
01025
01026
01027
01028 #ifdef JTAG_DISABLE_IRQ
01029 local_irq_save(flags);
01030
01031 #endif
01032
01033 jtag_send(chn, 1, 5, 0 );
01034 jtag_send(chn, 0, 1, 0 );
01035 jtag_send(chn, 1, 2, 0 );
01036 jtag_send(chn, 0, 2, 0 );
01037 jtag_send(chn, 0, 5, 0x90);
01038 jtag_send(chn, 1, 1, 0 );
01039 jtag_send(chn, 1, 2, 0 );
01040 jtag_send(chn, 0, 2, 0 );
01041 jtag_write_bits (chn,
01042 &buf[0],
01043 32,
01044 0,
01045 1, 0) ;
01046 jtag_send(chn, 1, 5, 0 );
01047 jtag_send(chn, 0, 1, 0 );
01048 jtag_send(chn, 1, 2, 0 );
01049 jtag_send(chn, 0, 2, 0 );
01050 jtag_send(chn, 0, 5, 0x10);
01051 jtag_send(chn, 1, 1, 0 );
01052 jtag_send(chn, 1, 2, 0 );
01053 jtag_send(chn, 0, 2, 0 );
01054 jtag_write_bits (chn,
01055 &buf[4],
01056 32,
01057 0,
01058 1,0) ;
01059 jtag_send(chn,1, 5, 0 );
01060 #ifdef JTAG_DISABLE_IRQ
01061 local_irq_restore(flags);
01062 #endif
01063
01064
01065 dp = (unsigned long *) &buf[0];
01066 d1= *dp;
01067 for (i=0;i<32;i++){
01068 d2 = (d2 << 1) | (d1 & 1);
01069 d1 >>= 1;
01070 }
01071 *dp=d2;
01072 dp = (unsigned long *) &buf[4];
01073 d1= *dp;
01074 for (i=0;i<32;i++){
01075 d2 = (d2 << 1) | (d1 & 1);
01076 d1 >>= 1;
01077 }
01078 *dp=d2;
01079 D(for (i=0; i<8;i++) {printk("%3x ",(int) buf[i]); if ((i & 0xf) == 0xf) printk ("\n");} );
01080 data_modified=0;
01081 return 0;
01082 }
01083
01084
01085
01086
01087
01088
01089 int JTAG_CAPTURE (int chn, unsigned char * buf, int len) {
01090
01091 #ifdef JTAG_DISABLE_IRQ
01092 unsigned long flags;
01093 #endif
01094 D(printk("buf=%p\n",buf));
01095
01096 #ifdef JTAG_DISABLE_IRQ
01097 local_irq_save(flags);
01098
01099 #endif
01100
01101
01102
01103 jtag_send(chn, 1, 2, 0 );
01104 jtag_send(chn, 0, 2, 0 );
01105 jtag_send(chn, 0, 5, 0x80);
01106 jtag_send(chn, 1, 1, 0 );
01107 jtag_send(chn, 1, 2, 0 );
01108 jtag_send(chn, 0, 2, 0 );
01109 jtag_write_bits (chn,
01110 buf,
01111 len,
01112 0,
01113 1,0) ;
01114
01115
01116 jtag_send(chn, 1, 1, 0 );
01117
01118
01119 #ifdef JTAG_DISABLE_IRQ
01120 local_irq_restore(flags);
01121 #endif
01122
01123 D(printk ("\n"); for (i=0; i<((len+7)>>3) ;i++) {printk("%3x ",(int) buf[i]); if ((i & 0xf) == 0xf) printk ("\n");}printk ("\n"); );
01124 data_modified=0;
01125 return 0;
01126
01127 }
01128
01129
01130
01131
01132
01133
01134
01135 int JTAG_EXTEST (int chn, unsigned char * buf, int len) {
01136 #ifdef JTAG_DISABLE_IRQ
01137 unsigned long flags;
01138 #endif
01139
01140 #ifdef JTAG_DISABLE_IRQ
01141 local_irq_save(flags);
01142
01143 #endif
01144 D(printk("EXTEST: buf=%p, len=0x%x\n",buf,len));
01145
01146
01147
01148 jtag_send(chn, 1, 2, 0 );
01149 jtag_send(chn, 0, 2, 0 );
01150 jtag_send(chn, 0, 5, 0xf0);
01151 jtag_send(chn, 1, 1, 0 );
01152 jtag_send(chn, 1, 2, 0 );
01153 jtag_send(chn, 0, 2, 0 );
01154
01155 jtag_write_bits (chn,
01156 buf,
01157 len,
01158 0,
01159 1,0);
01160 jtag_send(chn, 1, 1, 0 );
01161 #ifdef JTAG_DISABLE_IRQ
01162 local_irq_restore(flags);
01163 #endif
01164 D(printk ("\n"); for (i=0; i<((len+7)>>3) ;i++) {printk("%3x ",(int) buf[i]); if ((i & 0xf) == 0xf) printk ("\n");}printk ("\n"); );
01165
01166 return 0;
01167 }
01168
01169 static int __init fpga_jtag_init(void) {
01170 int i,res;
01171 res = register_chrdev(FPGA_JTAG_MAJOR, fpga_jtag_name, &fpga_jtag_fops);
01172 if(res < 0) {
01173 printk(KERN_ERR "\nfpga_jtag_init: couldn't get a major number %d.\n",FPGA_JTAG_MAJOR);
01174 return res;
01175 }
01176 printk(FPGA_JTAG_DRIVER_NAME" - %d\n",FPGA_JTAG_MAJOR);
01177 for (i=0;i<=FPGA_JTAG_MAXMINOR;i++) minors[i]=0;
01178 initPortC();
01179 fpga_state&=~0xffff;
01180 return 0;
01181 }
01182
01183
01184
01185
01186
01187 module_init(fpga_jtag_init);
01188 MODULE_LICENSE("GPL");
01189 MODULE_AUTHOR("Andrey Filippov <andrey@elphel.com>.");
01190 MODULE_DESCRIPTION(FPGA_JTAG_DRIVER_NAME);
01191