os/linux-2.6-tag--devboard-R2_10-4/arch/cris/arch-v32/drivers/elphel/fpga_sdram.c

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/*!***************************************************************************
*! FILE NAME  : fpga_sdram333.c
*! DESCRIPTION: TBD
*! Copyright (C) 2002-2006 Elphel, Inc.
*! -----------------------------------------------------------------------------**
*!
*!  This program is free software: you can redistribute it and/or modify
*!  it under the terms of the GNU General Public License as published by
*!  the Free Software Foundation, either version 3 of the License, or
*!  (at your option) any later version.
*!
*!  This program is distributed in the hope that it will be useful,
*!  but WITHOUT ANY WARRANTY; without even the implied warranty of
*!  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
*!  GNU General Public License for more details.
*!
*!  You should have received a copy of the GNU General Public License
*!  along with this program.  If not, see <http://www.gnu.org/licenses/>.
*! -----------------------------------------------------------------------------**
*!  $Log: fpga_sdram353.c,v $
*!  Revision 1.1.1.1  2008/11/27 20:04:00  elphel
*!
*!
*!  Revision 1.5  2008/10/25 20:01:33  elphel
*!  just put notes about not using file->f_pos in read() and write()
*!
*!  Revision 1.4  2008/09/22 22:55:48  elphel
*!  snapshot
*!
*!  Revision 1.3  2008/09/16 00:49:31  elphel
*!  snapshot
*!
*!  Revision 1.2  2008/06/16 06:51:21  elphel
*!  work in progress, intermediate commit
*!
*!  Revision 1.1.1.1  2007/08/17 10:23:18  elphel
*!  This is a fresh tree based on elphel353-2.10
*!
*!  Revision 1.7  2007/08/17 10:23:18  spectr_rain
*!  switch to GPL3 license
*!
*!  Revision 1.6  2007/07/20 10:17:46  spectr_rain
*!  *** empty log message ***
*!
*!  Revision 1.1.1.1  2007/02/23 10:11:48  elphel
*!  initial import into CVS
*!
*!  Revision 1.2  2005/05/10 21:08:49  elphel
*!  *** empty log message ***
*!
*/
/****************** INCLUDE FILES SECTION ***********************************/

#include <linux/module.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/autoconf.h>

#include <asm/system.h>
//#include <asm/svinto.h>
#include <asm/io.h>

#include <asm/irq.h>

#include <asm/delay.h>
#include <asm/uaccess.h>
#include <asm/elphel/c313a.h> // just for LSEEK_FSDRAM_RESET
#include <asm/elphel/fpgaconfa.h>

#include "fpgactrl.h"
#include "fpga_sdram.h"
#include "x3x3.h"

#define D(x)
//#define MD2(x) printk("%s:%d:",__FILE__,__LINE__);x
#define MD2(x)

#define DEBUG_MODE1
static int sdbuf[128];
static char * sdbytebuf= (char *) sdbuf;

void fpga_resetSDRAM(void) {
    X313_SDRAM_OFF;
    fpga_state &= ~FPGA_STATE_SDRAM_INIT;
    MD2(printk("fpga_resetSDRAM()\n"));
}

void fpga_initSDRAM(void) {
//         | 31-18 | not used 
//         |    17 | RAS
//         |    16 | CAS
//         |    15 | WE
//         | 14-13 | bank address [1:0]
//         | 12-00 | address[12:0]
// 0x20000 - RAS
// 0x10000 - CAS
// 0x08000 - WE
// 0x00100 - (in mode register) - reset DLL
// 0x00003 - (in mode register) - burst=8
// 0x00060 - (in mode register) - CL=2.5
// 0x02000 - ext mode register
// 0x00001 - ext mode (OR with 0x2000) - disable DLL (0 - enable)
// 0x00002 - ext mode (OR with 0x2000) - reduced drive strength (try it)


    X313_SDRAM_OFF;
    // wait 100usec
    udelay (100);
    port_csp0_addr[X313_WA_SD_MANCMD] = 0x17fff; // precharge, a[10]=1 - all banks
    udelay (1);
//    port_csp0_addr[X313_WA_SD_MANCMD] = 0x02000; // load extended mode register - enable DLL
    port_csp0_addr[X313_WA_SD_MANCMD] = 0x02002; // load extended mode register - enable DLL, reduced drive strength
    udelay (1);
    port_csp0_addr[X313_WA_SD_MANCMD] = 0x00163; // load mode register - CL=2.5, burst=8 (no full fage available), reset DLL
    udelay (1);
    port_csp0_addr[X313_WA_SD_MANCMD] = 0x8000; // refresh
    udelay (1);
    port_csp0_addr[X313_WA_SD_MANCMD] = 0x8000; // refresh
    udelay (1);
    port_csp0_addr[X313_WA_SD_MANCMD] = 0x00063; // (not needed for Micron) - clear reset DLL bit in mode register
    udelay (1);
    X313_SDRAM_ON; // enable+refresh
    MD2(printk("fpga_initSDRAM\n"));
    fpga_state |= FPGA_STATE_SDRAM_INIT;
}


int     fsdram_ioctl(struct inode *inode, struct file *file,  unsigned int cmd, unsigned long arg) {
 return 0;
}

ssize_t fsdram_read(struct file * file, char * buf, size_t count, loff_t *off) {
  unsigned long p,sa,left,i,j,nb,ibp;
  char * bp=buf;

  D(printk("fsdram_read from 0x%x\n", (int) *off));
  if (!X313_IS_SDRAM_ON) return -EFAULT;    // SDRAM was not enabled or refresh was not on
  p = *off;
  if (p >= X313_SDRAM_SIZE)  return -EINVAL; // bigger than SDRAM
  if( (p + count) > X313_SDRAM_SIZE) { // truncate count 
    count = X313_SDRAM_SIZE - p;
  }
  left=count;
  if (left==0) return 0;
// find start address for the sdram channel (512 bytes page aligned)
  sa=(p>>1) & 0x01ffff00;
    // program channel 3 to read maximal length
#ifdef DEBUG_MODE1
  if (port_csp0_addr[0x2b] & 1){ X313_INIT_SDCHAN( 3, 1, 0, 0, sa , 0x3ff, 0xfff); }
  else                         { X313_INIT_SDCHAN( 3, 0, 0, 0, sa , 0x3ff, 0xfff); }
#else
  X313_INIT_SDCHAN( 3, 0, 0, 0, sa , 0x3ff, 0xfff);   // 4096 rows of 32x256 16-bit words each - 64MB > than memory
#endif
// enable channel if it was not already
   X313_CHN_EN(3);
//MD2(printk("0x27 <- 0x%x", (int) X313_CHN_EN_D(3)));

  while (left >0) {
// wait SDRAM ready
    j=10000;
    while (((j--)>0) && !X313_SR(PIORDY));
    if (j==0) return -EFAULT;  // page not ready
// read the whole page (128x32) to the buffer
    i=port_csp4_addr[X313_WA_SD_PIOWIN]; // will return garbage (because of latency), prepares to the next read, increments address
    for (i=0;i<128;i++)        sdbuf[i]=port_csp4_addr[X313_WA_SD_PIOWIN];
    port_csp0_addr[X313_WA_SDPIO_NEXT]=0; // advance to the next page
// copy data
    ibp=p-(sa<<1);
    nb=left;
    if ((ibp+nb)>512) nb=512-ibp;
//    D(printk ("copytouser, ibp=%x, nb=%x\n", (int) ibp, (int) nb));
    if (copy_to_user(bp, &sdbytebuf[ibp], nb)) return -EFAULT;
    left -=nb;
    bp+=nb;
    p+=nb;
    sa+=256;
  } // while (left>0)
  *off+=count;
  D(printk("count= 0x%x, pos= 0x%x\n", (int) count, (int)*off));
  return count;  
}
int read_page_to_buffer(unsigned long sa) {
  unsigned long i;
  X313_INIT_SDCHAN( 3, 0, 0, 0, sa , 0x3ff, 0xfff);   // 4096 rows of 32x256 16-bit words each
  // enable channel if it was not already
  X313_CHN_EN(3);
//MD2(printk("0x27 <- 0x%x", (int) X313_CHN_EN_D(3)));
// wait SDRAM ready
  i=10000;
  while (((i--)>0) && !X313_SR(PIORDY));
  D(printk("ready, i=%d\n",(int) i));
  if (i==0) return -EFAULT;
// stop channel 3 from reading more data to the cache.
  X313_CHN_DIS(3);  // disable channel 3 access to SDRAM
  i=port_csp4_addr[X313_WA_SD_PIOWIN]; // will return garbage (because of latency), prepares to the next read, increments address
  for (i=0;i<128;i++){
   sdbuf[i]=port_csp4_addr[X313_WA_SD_PIOWIN];
  } 
  return 0;  
}

ssize_t fsdram_write(struct file * file, const char * buf, size_t count, loff_t *off) {
//  unsigned long p,sa,left,n,i,j,bi,nb,ibp;
  unsigned long p,sa,left,i,nb,ibp;
  const char * bp=buf;
  int fp=1; // first page
  D(printk("fsdram_write to 0x%x\n", (int) *off));
  if (!X313_IS_SDRAM_ON) return -EFAULT;    // SDRAM was not enabled or refresh was not on
  p = *off;
  if (p >= X313_SDRAM_SIZE)  return -EINVAL; // bigger than SDRAM
  if( (p + count) > X313_SDRAM_SIZE) { // truncate count 
    count = X313_SDRAM_SIZE - p;
  }
  left=count;
  if (left==0) return 0;
// if the write starts not from the beginning of a page or is smaller than a page - read page to an internal buffer first
 D(printk ("p=%x, left=%x\n", (int) p, (int) left));
  if ((p & 0x1ff) || (left<0x200)) {
    sa=(p>>1) & 0x01ffff00;
    if (read_page_to_buffer(sa)<0) return -EFAULT;  // page not ready
  }
// now process pages, loooking if it is a partial last (but not first, as it is already read in)
  while (left >0) {
// find start address for the sdram channel (512 bytes page aligned)
    sa=(p>>1) & 0x01ffff00;
// wait for write buffer empty (if not the first page)
    if (!fp) {
      i=1000;
      while (((i--)>0) && !X313_SR(PIOWEMPTY)) udelay(1);
      if (i==0) return -EFAULT;  // page not ready
// is it partial (but not first) page?
      if ((left<0x200) && (read_page_to_buffer(sa)<0)) return -EFAULT;  // page not ready
    }
// program channel 3 to write maximal frame size
    X313_INIT_SDCHAN( 3, 0, 1, 0, sa , 0x3ff, 0xfff);   // 4096 rows of 32x256 16-bit words each
// enable channel if it was not already
    X313_CHN_EN(3);
    while ((left>0) && ((left>=512) || fp)) { // will be false for the last page if !fp (force to outer loop that reads buffer)
// copy from user to internal buffer
      ibp=p-(sa<<1);
      nb=left;
      if ((ibp+nb)>512) nb=512-ibp;
      if (copy_from_user(&sdbytebuf[ibp], bp, nb)) return -EFAULT;
      bp+=nb;
// wait SDRAM ready
      i=10000;
      while (((i--)>0) && !X313_SR(PIORDY));
      if (i==0) return -EFAULT;  // page not ready
// send the whole page to SDRAM buffer
      for (i=0;i<128;i++)  port_csp0_addr[X313_WA_SD_PIOWIN]=sdbuf[i];
      port_csp0_addr[X313_WA_SDPIO_NEXT]=0; // next page - write current page to SDRAM
      left -=nb;
      p+=nb;
      sa+=256;
      fp=0;
    } // while ((left>0) && ((left>=256) || !fp))
  } // while (left >0)
  i=1000;
  while (((i--)>0) && !X313_SR(PIOWEMPTY)) udelay(1);
  if (i==0) return -EFAULT;  // page not ready
  *off+=count;
  D(printk("count= 0x%x, pos= 0x%x\n", (int) count, (int) *off));
  return count;
}


loff_t  fsdram_lseek(struct file * file, loff_t offset, int orig)
{
/*
 *  orig 0: position from begning
 *  orig 1: relative from current position
 *  orig 2: position from last address
 */
  D(printk("fsdram_lseek\n"));
  
  switch (orig)
  {
   case SEEK_SET:
     file->f_pos = offset;
     break;
   case SEEK_CUR:
     file->f_pos += offset;
     break;
   case SEEK_END:
     if (offset <=0) file->f_pos = X313_SDRAM_SIZE + offset;
     else {
       switch (offset) {
         case LSEEK_FSDRAM_RESET:
           fpga_resetSDRAM();
           break;
         default:
           return -EINVAL; 
       }
     }
     break;
   default:
     return -EINVAL;
  }

  /* truncate position */
  if (file->f_pos < 0) {
    file->f_pos = 0;    
    return(-EOVERFLOW);
  }
  if (file->f_pos >= X313_SDRAM_SIZE) {
    file->f_pos = X313_SDRAM_SIZE - 1;
    return(-EOVERFLOW);
  }
  return ( file->f_pos );
}

int     fsdram_open(struct inode *inode, struct file *filp) {
// add initializing SDRAM if it was off
    if (!X313_IS_SDRAM_ON)  { // now will init even if only refresh was off
      fpga_initSDRAM();
      D(printk("fpga_initSDRAM\n"));
    }

 D(printk("fsdram_open\n"));

inode->i_size=X313_SDRAM_SIZE;
  return 0;
}
int     fsdram_release (void){
 D(printk("fsdram_release\n"));
  return 0;
}


//  if (copy_from_user(&bitstream_data[buf8i],buf,count)) return -EFAULT;
//     bytes_left = copy_from_user(void*to, const void *from, unsigned long n );
//     bytes_left = copy_to_user(void*to, const void *from,   unsigned long n );

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