58 // Assuming 100MHz input clock, 800MHz Fvco, 400MHz clk, 200MHz clk_div, 200MHz mclk 60 parameter CLKFBOUT_MULT =
8,
// Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE 62 parameter CLKFBOUT_USE_FINE_PS =
1,
// if 1 move CLKFBOUT_PHASE and SDCLK_PHASE, if 0 - other outputs (moved phases should be 0/same) 74 output ddr3_clk,
// DDR3 clock differential output, positive 75 output ddr3_nclk,
// DDR3 clock differential output, negative 77 output [
2:
0]
ddr3_ba,
// output bank address ports 84 inout [
15:
0]
dq,
// DQ I/O pads 85 output dml,
// LDM I/O pad (actually only output) 86 inout dqsl,
// LDQS I/O pad 88 output dmu,
// UDM I/O pad (actually only output) 89 inout dqsu,
// UDQS I/O pad 92 input clk_in,
// master input clock, initially assuming 100MHz 93 output clk,
// free-running system clock, same frequency as iclk (shared for R/W), BUFR output 94 output clk_div,
// free-running half clk frequency, front aligned to clk (shared for R/W), BUFR output 95 output mclk,
// same as clk_div, through separate BUFG and static phase adjust 96 input mrst,
// @posedge mclk synchronous reset - should not interrupt mclk generation 97 input ref_clk,
// global clock for idelay_ctrl calibration 99 input rst_in,
// reset delays/serdes - global reset? 100 input ddr_rst,
// active high - generate NRST to memory 101 input dci_rst,
// active high - reset DCI circuitry 102 input dly_rst,
// active high - delay calibration circuitry 104 input [
2*
ADDRESS_NUMBER-
1:
0]
in_a,
// input address, 2 bits per signal (first, second) (29:0) for 4Gb device 105 input [
5:
0]
in_ba,
// input bank address, 2 bits per signal (first, second) 106 input [
1:
0]
in_we,
// input WE, 2 bits (first, second) 107 input [
1:
0]
in_ras,
// input RAS, 2 bits (first, second) 108 input [
1:
0]
in_cas,
// input CAS, 2 bits (first, second) 109 input [
1:
0]
in_cke,
// input CKE, 2 bits (first, second) 110 input [
1:
0]
in_odt,
// input ODT, 2 bits (first, second) 111 // input [1:0] in_tri, // tristate command/address outputs - same timing, but no odelay 112 input in_tri,
// tristate command/address outputs - same timing, but no odelay 114 input [
63:
0]
din,
// parallel data to be sent out (4 bits per DG I/)) 115 input [
7:
0]
din_dm,
// parallel data to be sent out over DM 116 input [
7:
0]
tin_dq,
// tristate for data out (sent out earlier than data!) and dm 117 input [
7:
0]
din_dqs,
// parallel data to be sent out over DQS 118 input [
7:
0]
tin_dqs,
// tristate for DQS out (sent out earlier than data!) 119 output [
63:
0]
dout,
// parallel data received from DDR3 memory, 4 bits per DQ I/O 122 input inv_clk_div,
// invert clk_div for R channels (clk_div is shared between R and W) 124 input dci_disable_dq,
// disable DCI termination during writes and idle for dq and dm signals 126 input [
7:
0]
dly_data,
// delay value (3 LSB - fine delay) 127 input [
6:
0]
dly_addr,
// select which delay to program 128 input ld_delay,
// load delay data to selected iodelayl (clk_div synchronous) 129 input set,
// clk_div synchronous set all delays from previously loaded values 139 assign locked_pll =
1;
// not used anymore, reference clock generation moved to other module 142 always @(
posedge clk_div)
begin // Why is it @ negedge clk_div? 151 // wire clkfb_ref, clk_ref_pre; 177 mrst,
// rst_in, rst_in - is it global clock? 184 .
CAPACITANCE(
"DONT_CARE"),
208 .
clk (
clk),
// free-running system clock, same frequency as iclk (shared for R/W) 209 .
clk_div (
clk_div),
// free-running half clk frequency, front aligned to clk (shared for R/W) 210 .
rst (
rst),
// reset delays/serdes 211 .
in_a (
in_a[
2*
ADDRESS_NUMBER-
1:
0]),
// input address, 2 bits per signal (first, second) (29:0) for 4Gb device 212 .
in_ba (
in_ba[
5:
0]),
// input bank address, 2 bits per signal (first, second) 213 .
in_we (
in_we[
1:
0]),
// input WE, 2 bits (first, second) 214 .
in_ras (
in_ras[
1:
0]),
// input RAS, 2 bits (first, second) 215 .
in_cas (
in_cas[
1:
0]),
// input CAS, 2 bits (first, second) 216 .
in_cke (
in_cke[
1:
0]),
// input CKE, 2 bits (first, second) 217 .
in_odt (
in_odt[
1:
0]),
// input ODT, 2 bits (first, second) 218 // .in_tri (in_tri[1:0]), // tristate command/address outputs - same timing, but no odelay 219 .
in_tri (
in_tri),
// tristate command/address outputs - same timing, but no odelay 222 .
ld_delay (
ld_cmda),
// load delay data to selected iodelayl (clk_div synchronous) 223 .
set (
set)
// clk_div synchronous set all delays from previously loaded values 237 .
dq (
dq[
7:
0]),
// DQ I/O pads 238 .
dm (
dml),
// DM I/O pad (actually only output) 241 .
clk (
clk),
// free-running system clock, same frequency as iclk (shared for R/W) 242 .
clk_div (
clk_div),
// free-running half clk frequency, front aligned to clk (shared for R/W) 247 .
din (
din[
31:
0]),
// parallel data to be sent out (4 bits per DQ I/O)) 248 .
din_dm (
din_dm[
3:
0]),
// parallel data to be sent out over DM 249 .
tin_dq (
tin_dq[
3:
0]),
// tristate for data out (sent out earlier than data!) and dm 251 .
tin_dqs (
tin_dqs[
3:
0]),
// tristate for DQS out (sent out earlier than data!) 252 .
dout (
dout[
31:
0]),
// parallel data received from DDR3 memory, 4 bits per DQ I/O 255 .
ld_delay (
ld_data_l),
// load delay data to selected iodelayl (clk_div synchronous) 256 .
set (
set)
// clk_div synchronous set all delays from previously loaded values 270 .
dq (
dq[
15:
8]),
// DQ I/O pads 271 .
dm (
dmu),
// DM I/O pad (actually only output) 274 .
clk (
clk),
// free-running system clock, same frequency as iclk (shared for R/W) 275 .
clk_div (
clk_div),
// free-running half clk frequency, front aligned to clk (shared for R/W) 280 .
din (
din[
63:
32]),
// parallel data to be sent out (4 bits per DQ I/O)) 281 .
din_dm (
din_dm[
7:
4]),
// parallel data to be sent out over DM 282 .
tin_dq (
tin_dq[
7:
4]),
// tristate for data out (sent out earlier than data!) and dm 284 .
tin_dqs (
tin_dqs[
7:
4]),
// tristate for DQS out (sent out earlier than data!) 285 .
dout (
dout[
63:
32]),
// parallel data received from DDR3 memory, 4 bits per DQ I/O 288 .
ld_delay (
ld_data_h),
// load delay data to selected iodelayl (clk_div synchronous) 289 .
set (
set)
// clk_div synchronous set all delays from previously loaded values 299 .
rst(
1'b0),
//rst_n_clk), // input no need to reset? 301 .
din(
2'b01),
// input[1:0] 302 .
tin(
rst),
// tristate at reset 306 // Clocks: MMCM is used to generate ddr3 differential clock (no dynamic phase shift), 307 // clk - write bit clock, phase dynamically adjusted, BUFR (initially 400MHz) 308 // clk_div half bit frequency clock, phase dynamically adjusted, BUFR. Used also for delay/phase control (200MHz) 309 // mclk - same frequency as clk_div (same dynamic phase adjust), but with BUFG to be used in other regions. Phase to be 310 // statically adjusted for clock boundary crossing 311 // Phase control included, allowing setting phase in +/- 127 steps, each 1/56 of 1/Fvco (~22ps for Fvco=800MHz) 312 // So shifting phase dynamically by plus/- 113 moves SDCLK by a full period (2.5ns) forward and backward (113= 0x71) 315 //BUFIO clk_buf_i (.O(clk), .I(clk_pre)); 318 ///BUFG clk_ref_i (.O(ref_clk), .I(clk_ref_pre)); 331 //ERROR: [DRC 23-20] Rule violation (AVAL-139) Phase shift check - The MMCME2_ADV cell mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i has a fractional CLKOUT3_PHASE value (75.000) with CLKOUT3_USE_FINE_PS set to FALSE. It should be a multiple of [45 / CLKOUT3_DIVIDE] = [45 / 4] = 11.250. 333 // .CLKOUT4_PHASE (0.000), 334 // .CLKOUT5_PHASE (0.000), 335 // .CLKOUT6_PHASE (0.000), 341 // .CLKOUT4_USE_FINE_PS("FALSE"), 342 // .CLKOUT5_USE_FINE_PS("FALSE"), 343 // .CLKOUT6_USE_FINE_PS("FALSE"), 344 .
CLKOUT0_DIVIDE_F (
2.000),
348 // .CLKOUT4_DIVIDE(1), 349 // .CLKOUT5_DIVIDE(1), 350 // .CLKOUT6_DIVIDE(1), 351 .
COMPENSATION (
"ZHOLD"),
353 // .REF_JITTER2(0.010), 357 .
STARTUP_WAIT (
"FALSE")
358 )
mmcm_phase_cntr_i (
363 // .rst (rst), // input 389 // Does it need to be re-calibrated periodically - yes when temperature changes, same as dci_reset 402 //assign dci_ready= !(rst || dci_rst);
[ADDRESS_NUMBER-1:0] 6559ddr3_a
real 6538REFCLK_FREQUENCY300.0
[2*ADDRESS_NUMBER-1:0] 6042in_a
6537IODELAY_GRP"IODELAY_MEMORY"
6531IOSTANDARD_CLK"DIFF_SSTL15"
6527IOSTANDARD_DQ"SSTL15_T_DCI"
6528IOSTANDARD_DM"SSTL15"
6530IOSTANDARD_CMDA"SSTL15"
mmcm_phase_cntr_i mmcm_phase_cntr
6617clkin_stopped_mmcmwire
[PHASE_WIDTH-1:0] 11433ps_dout
6546CLKFBOUT_USE_FINE_PS1
6539HIGH_PERFORMANCE_MODE"FALSE"
[PHASE_WIDTH-1:0] 11431ps_din
[2*ADDRESS_NUMBER-1:0] 6584in_a
idelay_ctrl_i idelay_ctrl
[ADDRESS_NUMBER-1:0] 6032ddr3_a
6529IOSTANDARD_DQS"DIFF_SSTL15_T_DCI"
[PHASE_WIDTH-1:0] 6611ps_out
integer 6540ADDRESS_NUMBER15
6618clkfb_stopped_mmcmwire