56 // output dqs_di, // debugging: 57 //Input buffer ddrc_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dqs_i/iobufs_dqs_i/IBUFDS/IBUFDS_S (in ddrc_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dqs_i/iobufs_dqs_i macro) has no loads. An input buffer must drive an internal load. 59 input dci_disable,
// disable DCI termination during writes and idle 75 .
clk(
clk),
// serial output clock 78 .
din(
din[
3:
0]),
// parallel data in 79 .
tin(
tin[
3:
0]),
// parallel tri-state in 81 .
dout_iob(),
// data out to be connected directly to the output buffer 82 .
tout_dly(),
// tristate out to be connected to odelay input 83 .
tout_iob(
dqs_tri)
// tristate out to be connected directly to the tristate control of the output buffer 102 .
DQS_BIAS(
"TRUE"),
// outputs 1'b0 when IOB is floating 106 .
USE_IBUFDISABLE(
"FALSE")
iobufs_dqs_i IOBUFDS_DCIEN
real 6140REFCLK_FREQUENCY300.0
dqs_out_dly_i odelay_fine_pipe
6134IODELAY_GRP"IODELAY_MEMORY"
[MODE_DDR=="TRUE"?3:1:0] 11538din
integer 6135IDELAY_VALUE0
[MODE_DDR=="TRUE"?3:0:0] 11539tin
6138IOSTANDARD"DIFF_SSTL15_T_DCI"
6141HIGH_PERFORMANCE_MODE"FALSE"
integer 6136ODELAY_VALUE0
dqs_in_dly_i idelay_fine_pipe